target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27 #include "hw/pc.h"
  28 #include "hw/apic.h"
  29 #include "ioport.h"
  30 #include "kvm_x86.h"
  31
  32 #ifdef CONFIG_KVM_PARA
  33 #include <linux/kvm_para.h>
  34 #endif
  35 //
  36 //#define DEBUG_KVM
  37
  38 #ifdef DEBUG_KVM
  39 #define DPRINTF(fmt, ...) \
  40     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #define MSR_KVM_WALL_CLOCK  0x11
  47 #define MSR_KVM_SYSTEM_TIME 0x12
  48
  49 #ifndef BUS_MCEERR_AR
  50 #define BUS_MCEERR_AR 4
  51 #endif
  52 #ifndef BUS_MCEERR_AO
  53 #define BUS_MCEERR_AO 5
  54 #endif
  55
  56 #ifdef KVM_CAP_EXT_CPUID
  57
  58 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  59 {
  60     struct kvm_cpuid2 *cpuid;
  61     int r, size;
  62
  63     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  64     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  65     cpuid->nent = max;
  66     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  67     if (r == 0 && cpuid->nent >= max) {
  68         r = -E2BIG;
  69     }
  70     if (r < 0) {
  71         if (r == -E2BIG) {
  72             qemu_free(cpuid);
  73             return NULL;
  74         } else {
  75             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  76                     strerror(-r));
  77             exit(1);
  78         }
  79     }
  80     return cpuid;
  81 }
  82
  83 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  84                                       uint32_t index, int reg)
  85 {
  86     struct kvm_cpuid2 *cpuid;
  87     int i, max;
  88     uint32_t ret = 0;
  89     uint32_t cpuid_1_edx;
  90
  91     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  92         return -1U;
  93     }
  94
  95     max = 1;
  96     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  97         max *= 2;
  98     }
  99
 100     for (i = 0; i < cpuid->nent; ++i) {
 101         if (cpuid->entries[i].function == function &&
 102             cpuid->entries[i].index == index) {
 103             switch (reg) {
 104             case R_EAX:
 105                 ret = cpuid->entries[i].eax;
 106                 break;
 107             case R_EBX:
 108                 ret = cpuid->entries[i].ebx;
 109                 break;
 110             case R_ECX:
 111                 ret = cpuid->entries[i].ecx;
 112                 break;
 113             case R_EDX:
 114                 ret = cpuid->entries[i].edx;
 115                 switch (function) {
 116                 case 1:
 117                     /* KVM before 2.6.30 misreports the following features */
 118                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 119                     break;
 120                 case 0x80000001:
 121                     /* On Intel, kvm returns cpuid according to the Intel spec,
 122                      * so add missing bits according to the AMD spec:
 123                      */
 124                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 125                     ret |= cpuid_1_edx & 0x183f7ff;
 126                     break;
 127                 }
 128                 break;
 129             }
 130         }
 131     }
 132
 133     qemu_free(cpuid);
 134
 135     return ret;
 136 }
 137
 138 #else
 139
 140 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
 141                                       uint32_t index, int reg)
 142 {
 143     return -1U;
 144 }
 145
 146 #endif
 147
 148 #ifdef CONFIG_KVM_PARA
 149 struct kvm_para_features {
 150         int cap;
 151         int feature;
 152 } para_features[] = {
 153 #ifdef KVM_CAP_CLOCKSOURCE
 154         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 155 #endif
 156 #ifdef KVM_CAP_NOP_IO_DELAY
 157         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 158 #endif
 159 #ifdef KVM_CAP_PV_MMU
 160         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 161 #endif
 162         { -1, -1 }
 163 };
 164
 165 static int get_para_features(CPUState *env)
 166 {
 167         int i, features = 0;
 168
 169         for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 170                 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
 171                         features |= (1 << para_features[i].feature);
 172         }
 173
 174         return features;
 175 }
 176 #endif
 177
 178 #ifdef KVM_CAP_MCE
 179 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 180                                      int *max_banks)
 181 {
 182     int r;
 183
 184     r = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_MCE);
 185     if (r > 0) {
 186         *max_banks = r;
 187         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 188     }
 189     return -ENOSYS;
 190 }
 191
 192 static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
 193 {
 194     return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
 195 }
 196
 197 static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
 198 {
 199     return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
 200 }
 201
 202 static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n)
 203 {
 204     struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
 205     int r;
 206
 207     kmsrs->nmsrs = n;
 208     memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
 209     r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
 210     memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
 211     free(kmsrs);
 212     return r;
 213 }
 214
 215 /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
 216 static int kvm_mce_in_exception(CPUState *env)
 217 {
 218     struct kvm_msr_entry msr_mcg_status = {
 219         .index = MSR_MCG_STATUS,
 220     };
 221     int r;
 222
 223     r = kvm_get_msr(env, &msr_mcg_status, 1);
 224     if (r == -1 || r == 0) {
 225         return -1;
 226     }
 227     return !!(msr_mcg_status.data & MCG_STATUS_MCIP);
 228 }
 229
 230 struct kvm_x86_mce_data
 231 {
 232     CPUState *env;
 233     struct kvm_x86_mce *mce;
 234     int abort_on_error;
 235 };
 236
 237 static void kvm_do_inject_x86_mce(void *_data)
 238 {
 239     struct kvm_x86_mce_data *data = _data;
 240     int r;
 241
 242     /* If there is an MCE excpetion being processed, ignore this SRAO MCE */
 243     r = kvm_mce_in_exception(data->env);
 244     if (r == -1)
 245         fprintf(stderr, "Failed to get MCE status\n");
 246     else if (r && !(data->mce->status & MCI_STATUS_AR))
 247         return;
 248
 249     r = kvm_set_mce(data->env, data->mce);
 250     if (r < 0) {
 251         perror("kvm_set_mce FAILED");
 252         if (data->abort_on_error) {
 253             abort();
 254         }
 255     }
 256 }
 257 #endif
 258
 259 void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status,
 260                         uint64_t mcg_status, uint64_t addr, uint64_t misc,
 261                         int abort_on_error)
 262 {
 263 #ifdef KVM_CAP_MCE
 264     struct kvm_x86_mce mce = {
 265         .bank = bank,
 266         .status = status,
 267         .mcg_status = mcg_status,
 268         .addr = addr,
 269         .misc = misc,
 270     };
 271     struct kvm_x86_mce_data data = {
 272             .env = cenv,
 273             .mce = &mce,
 274     };
 275
 276     if (!cenv->mcg_cap) {
 277         fprintf(stderr, "MCE support is not enabled!\n");
 278         return;
 279     }
 280
 281     run_on_cpu(cenv, kvm_do_inject_x86_mce, &data);
 282 #else
 283     if (abort_on_error)
 284         abort();
 285 #endif
 286 }
 287
 288 int kvm_arch_init_vcpu(CPUState *env)
 289 {
 290     struct {
 291         struct kvm_cpuid2 cpuid;
 292         struct kvm_cpuid_entry2 entries[100];
 293     } __attribute__((packed)) cpuid_data;
 294     uint32_t limit, i, j, cpuid_i;
 295     uint32_t unused;
 296     struct kvm_cpuid_entry2 *c;
 297 #ifdef KVM_CPUID_SIGNATURE
 298     uint32_t signature[3];
 299 #endif
 300
 301     env->mp_state = KVM_MP_STATE_RUNNABLE;
 302
 303     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 304
 305     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 306     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 307     env->cpuid_ext_features |= i;
 308
 309     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 310                                                              0, R_EDX);
 311     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 312                                                              0, R_ECX);
 313     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
 314                                                              0, R_EDX);
 315
 316
 317     cpuid_i = 0;
 318
 319 #ifdef CONFIG_KVM_PARA
 320     /* Paravirtualization CPUIDs */
 321     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 322     c = &cpuid_data.entries[cpuid_i++];
 323     memset(c, 0, sizeof(*c));
 324     c->function = KVM_CPUID_SIGNATURE;
 325     c->eax = 0;
 326     c->ebx = signature[0];
 327     c->ecx = signature[1];
 328     c->edx = signature[2];
 329
 330     c = &cpuid_data.entries[cpuid_i++];
 331     memset(c, 0, sizeof(*c));
 332     c->function = KVM_CPUID_FEATURES;
 333     c->eax = env->cpuid_kvm_features & get_para_features(env);
 334 #endif
 335
 336     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 337
 338     for (i = 0; i <= limit; i++) {
 339         c = &cpuid_data.entries[cpuid_i++];
 340
 341         switch (i) {
 342         case 2: {
 343             /* Keep reading function 2 till all the input is received */
 344             int times;
 345
 346             c->function = i;
 347             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 348                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 349             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 350             times = c->eax & 0xff;
 351
 352             for (j = 1; j < times; ++j) {
 353                 c = &cpuid_data.entries[cpuid_i++];
 354                 c->function = i;
 355                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 356                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 357             }
 358             break;
 359         }
 360         case 4:
 361         case 0xb:
 362         case 0xd:
 363             for (j = 0; ; j++) {
 364                 c->function = i;
 365                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 366                 c->index = j;
 367                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 368
 369                 if (i == 4 && c->eax == 0)
 370                     break;
 371                 if (i == 0xb && !(c->ecx & 0xff00))
 372                     break;
 373                 if (i == 0xd && c->eax == 0)
 374                     break;
 375
 376                 c = &cpuid_data.entries[cpuid_i++];
 377             }
 378             break;
 379         default:
 380             c->function = i;
 381             c->flags = 0;
 382             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 383             break;
 384         }
 385     }
 386     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 387
 388     for (i = 0x80000000; i <= limit; i++) {
 389         c = &cpuid_data.entries[cpuid_i++];
 390
 391         c->function = i;
 392         c->flags = 0;
 393         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 394     }
 395
 396     cpuid_data.cpuid.nent = cpuid_i;
 397
 398 #ifdef KVM_CAP_MCE
 399     if (((env->cpuid_version >> 8)&0xF) >= 6
 400         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 401         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 402         uint64_t mcg_cap;
 403         int banks;
 404
 405         if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks))
 406             perror("kvm_get_mce_cap_supported FAILED");
 407         else {
 408             if (banks > MCE_BANKS_DEF)
 409                 banks = MCE_BANKS_DEF;
 410             mcg_cap &= MCE_CAP_DEF;
 411             mcg_cap |= banks;
 412             if (kvm_setup_mce(env, &mcg_cap))
 413                 perror("kvm_setup_mce FAILED");
 414             else
 415                 env->mcg_cap = mcg_cap;
 416         }
 417     }
 418 #endif
 419
 420     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 421 }
 422
 423 void kvm_arch_reset_vcpu(CPUState *env)
 424 {
 425     env->exception_injected = -1;
 426     env->interrupt_injected = -1;
 427     env->nmi_injected = 0;
 428     env->nmi_pending = 0;
 429     if (kvm_irqchip_in_kernel()) {
 430         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 431                                           KVM_MP_STATE_UNINITIALIZED;
 432     } else {
 433         env->mp_state = KVM_MP_STATE_RUNNABLE;
 434     }
 435 }
 436
 437 static int kvm_has_msr_star(CPUState *env)
 438 {
 439     static int has_msr_star;
 440     int ret;
 441
 442     /* first time */
 443     if (has_msr_star == 0) {
 444         struct kvm_msr_list msr_list, *kvm_msr_list;
 445
 446         has_msr_star = -1;
 447
 448         /* Obtain MSR list from KVM.  These are the MSRs that we must
 449          * save/restore */
 450         msr_list.nmsrs = 0;
 451         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 452         if (ret < 0 && ret != -E2BIG) {
 453             return 0;
 454         }
 455         /* Old kernel modules had a bug and could write beyond the provided
 456            memory. Allocate at least a safe amount of 1K. */
 457         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 458                                               msr_list.nmsrs *
 459                                               sizeof(msr_list.indices[0])));
 460
 461         kvm_msr_list->nmsrs = msr_list.nmsrs;
 462         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 463         if (ret >= 0) {
 464             int i;
 465
 466             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 467                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 468                     has_msr_star = 1;
 469                     break;
 470                 }
 471             }
 472         }
 473
 474         free(kvm_msr_list);
 475     }
 476
 477     if (has_msr_star == 1)
 478         return 1;
 479     return 0;
 480 }
 481
 482 static int kvm_init_identity_map_page(KVMState *s)
 483 {
 484 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 485     int ret;
 486     uint64_t addr = 0xfffbc000;
 487
 488     if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 489         return 0;
 490     }
 491
 492     ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
 493     if (ret < 0) {
 494         fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
 495         return ret;
 496     }
 497 #endif
 498     return 0;
 499 }
 500
 501 int kvm_arch_init(KVMState *s, int smp_cpus)
 502 {
 503     int ret;
 504
 505     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 506      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 507      * must be part of guest physical memory, we need to allocate it.  Older
 508      * versions of KVM just assumed that it would be at the end of physical
 509      * memory but that doesn't work with more than 4GB of memory.  We simply
 510      * refuse to work with those older versions of KVM. */
 511     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 512     if (ret <= 0) {
 513         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 514         return ret;
 515     }
 516
 517     /* this address is 3 pages before the bios, and the bios should present
 518      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 519      * this?
 520      */
 521     /*
 522      * Tell fw_cfg to notify the BIOS to reserve the range.
 523      */
 524     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 525         perror("e820_add_entry() table is full");
 526         exit(1);
 527     }
 528     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 529     if (ret < 0) {
 530         return ret;
 531     }
 532
 533     return kvm_init_identity_map_page(s);
 534 }
 535
 536 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 537 {
 538     lhs->selector = rhs->selector;
 539     lhs->base = rhs->base;
 540     lhs->limit = rhs->limit;
 541     lhs->type = 3;
 542     lhs->present = 1;
 543     lhs->dpl = 3;
 544     lhs->db = 0;
 545     lhs->s = 1;
 546     lhs->l = 0;
 547     lhs->g = 0;
 548     lhs->avl = 0;
 549     lhs->unusable = 0;
 550 }
 551
 552 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 553 {
 554     unsigned flags = rhs->flags;
 555     lhs->selector = rhs->selector;
 556     lhs->base = rhs->base;
 557     lhs->limit = rhs->limit;
 558     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 559     lhs->present = (flags & DESC_P_MASK) != 0;
 560     lhs->dpl = rhs->selector & 3;
 561     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 562     lhs->s = (flags & DESC_S_MASK) != 0;
 563     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 564     lhs->g = (flags & DESC_G_MASK) != 0;
 565     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 566     lhs->unusable = 0;
 567 }
 568
 569 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 570 {
 571     lhs->selector = rhs->selector;
 572     lhs->base = rhs->base;
 573     lhs->limit = rhs->limit;
 574     lhs->flags =
 575         (rhs->type << DESC_TYPE_SHIFT)
 576         | (rhs->present * DESC_P_MASK)
 577         | (rhs->dpl << DESC_DPL_SHIFT)
 578         | (rhs->db << DESC_B_SHIFT)
 579         | (rhs->s * DESC_S_MASK)
 580         | (rhs->l << DESC_L_SHIFT)
 581         | (rhs->g * DESC_G_MASK)
 582         | (rhs->avl * DESC_AVL_MASK);
 583 }
 584
 585 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 586 {
 587     if (set)
 588         *kvm_reg = *qemu_reg;
 589     else
 590         *qemu_reg = *kvm_reg;
 591 }
 592
 593 static int kvm_getput_regs(CPUState *env, int set)
 594 {
 595     struct kvm_regs regs;
 596     int ret = 0;
 597
 598     if (!set) {
 599         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 600         if (ret < 0)
 601             return ret;
 602     }
 603
 604     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 605     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 606     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 607     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 608     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 609     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 610     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 611     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 612 #ifdef TARGET_X86_64
 613     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 614     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 615     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 616     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 617     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 618     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 619     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 620     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 621 #endif
 622
 623     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 624     kvm_getput_reg(&regs.rip, &env->eip, set);
 625
 626     if (set)
 627         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 628
 629     return ret;
 630 }
 631
 632 static int kvm_put_fpu(CPUState *env)
 633 {
 634     struct kvm_fpu fpu;
 635     int i;
 636
 637     memset(&fpu, 0, sizeof fpu);
 638     fpu.fsw = env->fpus & ~(7 << 11);
 639     fpu.fsw |= (env->fpstt & 7) << 11;
 640     fpu.fcw = env->fpuc;
 641     for (i = 0; i < 8; ++i)
 642         fpu.ftwx |= (!env->fptags[i]) << i;
 643     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 644     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 645     fpu.mxcsr = env->mxcsr;
 646
 647     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 648 }
 649
 650 #ifdef KVM_CAP_XSAVE
 651 #define XSAVE_CWD_RIP     2
 652 #define XSAVE_CWD_RDP     4
 653 #define XSAVE_MXCSR       6
 654 #define XSAVE_ST_SPACE    8
 655 #define XSAVE_XMM_SPACE   40
 656 #define XSAVE_XSTATE_BV   128
 657 #define XSAVE_YMMH_SPACE  144
 658 #endif
 659
 660 static int kvm_put_xsave(CPUState *env)
 661 {
 662 #ifdef KVM_CAP_XSAVE
 663     int i;
 664     struct kvm_xsave* xsave;
 665     uint16_t cwd, swd, twd, fop;
 666
 667     if (!kvm_has_xsave())
 668         return kvm_put_fpu(env);
 669
 670     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 671     memset(xsave, 0, sizeof(struct kvm_xsave));
 672     cwd = swd = twd = fop = 0;
 673     swd = env->fpus & ~(7 << 11);
 674     swd |= (env->fpstt & 7) << 11;
 675     cwd = env->fpuc;
 676     for (i = 0; i < 8; ++i)
 677         twd |= (!env->fptags[i]) << i;
 678     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 679     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 680     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 681             sizeof env->fpregs);
 682     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 683             sizeof env->xmm_regs);
 684     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 685     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 686     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 687             sizeof env->ymmh_regs);
 688     return kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 689 #else
 690     return kvm_put_fpu(env);
 691 #endif
 692 }
 693
 694 static int kvm_put_xcrs(CPUState *env)
 695 {
 696 #ifdef KVM_CAP_XCRS
 697     struct kvm_xcrs xcrs;
 698
 699     if (!kvm_has_xcrs())
 700         return 0;
 701
 702     xcrs.nr_xcrs = 1;
 703     xcrs.flags = 0;
 704     xcrs.xcrs[0].xcr = 0;
 705     xcrs.xcrs[0].value = env->xcr0;
 706     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 707 #else
 708     return 0;
 709 #endif
 710 }
 711
 712 static int kvm_put_sregs(CPUState *env)
 713 {
 714     struct kvm_sregs sregs;
 715
 716     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 717     if (env->interrupt_injected >= 0) {
 718         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 719                 (uint64_t)1 << (env->interrupt_injected % 64);
 720     }
 721
 722     if ((env->eflags & VM_MASK)) {
 723             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 724             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 725             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 726             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 727             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 728             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 729     } else {
 730             set_seg(&sregs.cs, &env->segs[R_CS]);
 731             set_seg(&sregs.ds, &env->segs[R_DS]);
 732             set_seg(&sregs.es, &env->segs[R_ES]);
 733             set_seg(&sregs.fs, &env->segs[R_FS]);
 734             set_seg(&sregs.gs, &env->segs[R_GS]);
 735             set_seg(&sregs.ss, &env->segs[R_SS]);
 736
 737             if (env->cr[0] & CR0_PE_MASK) {
 738                 /* force ss cpl to cs cpl */
 739                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 740                         (sregs.cs.selector & 3);
 741                 sregs.ss.dpl = sregs.ss.selector & 3;
 742             }
 743     }
 744
 745     set_seg(&sregs.tr, &env->tr);
 746     set_seg(&sregs.ldt, &env->ldt);
 747
 748     sregs.idt.limit = env->idt.limit;
 749     sregs.idt.base = env->idt.base;
 750     sregs.gdt.limit = env->gdt.limit;
 751     sregs.gdt.base = env->gdt.base;
 752
 753     sregs.cr0 = env->cr[0];
 754     sregs.cr2 = env->cr[2];
 755     sregs.cr3 = env->cr[3];
 756     sregs.cr4 = env->cr[4];
 757
 758     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 759     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 760
 761     sregs.efer = env->efer;
 762
 763     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 764 }
 765
 766 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 767                               uint32_t index, uint64_t value)
 768 {
 769     entry->index = index;
 770     entry->data = value;
 771 }
 772
 773 static int kvm_put_msrs(CPUState *env, int level)
 774 {
 775     struct {
 776         struct kvm_msrs info;
 777         struct kvm_msr_entry entries[100];
 778     } msr_data;
 779     struct kvm_msr_entry *msrs = msr_data.entries;
 780     int n = 0;
 781
 782     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 783     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 784     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 785     if (kvm_has_msr_star(env))
 786         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 787 #ifdef TARGET_X86_64
 788     /* FIXME if lm capable */
 789     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 790     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 791     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 792     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 793 #endif
 794     if (level == KVM_PUT_FULL_STATE) {
 795         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 796         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 797                           env->system_time_msr);
 798         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 799     }
 800
 801     msr_data.info.nmsrs = n;
 802
 803     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 804
 805 }
 806
 807
 808 static int kvm_get_fpu(CPUState *env)
 809 {
 810     struct kvm_fpu fpu;
 811     int i, ret;
 812
 813     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 814     if (ret < 0)
 815         return ret;
 816
 817     env->fpstt = (fpu.fsw >> 11) & 7;
 818     env->fpus = fpu.fsw;
 819     env->fpuc = fpu.fcw;
 820     for (i = 0; i < 8; ++i)
 821         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 822     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 823     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 824     env->mxcsr = fpu.mxcsr;
 825
 826     return 0;
 827 }
 828
 829 static int kvm_get_xsave(CPUState *env)
 830 {
 831 #ifdef KVM_CAP_XSAVE
 832     struct kvm_xsave* xsave;
 833     int ret, i;
 834     uint16_t cwd, swd, twd, fop;
 835
 836     if (!kvm_has_xsave())
 837         return kvm_get_fpu(env);
 838
 839     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 840     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 841     if (ret < 0)
 842         return ret;
 843
 844     cwd = (uint16_t)xsave->region[0];
 845     swd = (uint16_t)(xsave->region[0] >> 16);
 846     twd = (uint16_t)xsave->region[1];
 847     fop = (uint16_t)(xsave->region[1] >> 16);
 848     env->fpstt = (swd >> 11) & 7;
 849     env->fpus = swd;
 850     env->fpuc = cwd;
 851     for (i = 0; i < 8; ++i)
 852         env->fptags[i] = !((twd >> i) & 1);
 853     env->mxcsr = xsave->region[XSAVE_MXCSR];
 854     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 855             sizeof env->fpregs);
 856     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 857             sizeof env->xmm_regs);
 858     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 859     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 860             sizeof env->ymmh_regs);
 861     return 0;
 862 #else
 863     return kvm_get_fpu(env);
 864 #endif
 865 }
 866
 867 static int kvm_get_xcrs(CPUState *env)
 868 {
 869 #ifdef KVM_CAP_XCRS
 870     int i, ret;
 871     struct kvm_xcrs xcrs;
 872
 873     if (!kvm_has_xcrs())
 874         return 0;
 875
 876     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
 877     if (ret < 0)
 878         return ret;
 879
 880     for (i = 0; i < xcrs.nr_xcrs; i++)
 881         /* Only support xcr0 now */
 882         if (xcrs.xcrs[0].xcr == 0) {
 883             env->xcr0 = xcrs.xcrs[0].value;
 884             break;
 885         }
 886     return 0;
 887 #else
 888     return 0;
 889 #endif
 890 }
 891
 892 static int kvm_get_sregs(CPUState *env)
 893 {
 894     struct kvm_sregs sregs;
 895     uint32_t hflags;
 896     int bit, i, ret;
 897
 898     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 899     if (ret < 0)
 900         return ret;
 901
 902     /* There can only be one pending IRQ set in the bitmap at a time, so try
 903        to find it and save its number instead (-1 for none). */
 904     env->interrupt_injected = -1;
 905     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 906         if (sregs.interrupt_bitmap[i]) {
 907             bit = ctz64(sregs.interrupt_bitmap[i]);
 908             env->interrupt_injected = i * 64 + bit;
 909             break;
 910         }
 911     }
 912
 913     get_seg(&env->segs[R_CS], &sregs.cs);
 914     get_seg(&env->segs[R_DS], &sregs.ds);
 915     get_seg(&env->segs[R_ES], &sregs.es);
 916     get_seg(&env->segs[R_FS], &sregs.fs);
 917     get_seg(&env->segs[R_GS], &sregs.gs);
 918     get_seg(&env->segs[R_SS], &sregs.ss);
 919
 920     get_seg(&env->tr, &sregs.tr);
 921     get_seg(&env->ldt, &sregs.ldt);
 922
 923     env->idt.limit = sregs.idt.limit;
 924     env->idt.base = sregs.idt.base;
 925     env->gdt.limit = sregs.gdt.limit;
 926     env->gdt.base = sregs.gdt.base;
 927
 928     env->cr[0] = sregs.cr0;
 929     env->cr[2] = sregs.cr2;
 930     env->cr[3] = sregs.cr3;
 931     env->cr[4] = sregs.cr4;
 932
 933     cpu_set_apic_base(env->apic_state, sregs.apic_base);
 934
 935     env->efer = sregs.efer;
 936     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
 937
 938 #define HFLAG_COPY_MASK ~( \
 939                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 940                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 941                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 942                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 943
 944
 945
 946     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 947     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 948     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 949             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 950     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 951     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 952             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 953
 954     if (env->efer & MSR_EFER_LMA) {
 955         hflags |= HF_LMA_MASK;
 956     }
 957
 958     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 959         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 960     } else {
 961         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 962                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 963         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 964                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 965         if (!(env->cr[0] & CR0_PE_MASK) ||
 966                    (env->eflags & VM_MASK) ||
 967                    !(hflags & HF_CS32_MASK)) {
 968                 hflags |= HF_ADDSEG_MASK;
 969             } else {
 970                 hflags |= ((env->segs[R_DS].base |
 971                                 env->segs[R_ES].base |
 972                                 env->segs[R_SS].base) != 0) <<
 973                     HF_ADDSEG_SHIFT;
 974             }
 975     }
 976     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 977
 978     return 0;
 979 }
 980
 981 static int kvm_get_msrs(CPUState *env)
 982 {
 983     struct {
 984         struct kvm_msrs info;
 985         struct kvm_msr_entry entries[100];
 986     } msr_data;
 987     struct kvm_msr_entry *msrs = msr_data.entries;
 988     int ret, i, n;
 989
 990     n = 0;
 991     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 992     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 993     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 994     if (kvm_has_msr_star(env))
 995         msrs[n++].index = MSR_STAR;
 996     msrs[n++].index = MSR_IA32_TSC;
 997 #ifdef TARGET_X86_64
 998     /* FIXME lm_capable_kernel */
 999     msrs[n++].index = MSR_CSTAR;
1000     msrs[n++].index = MSR_KERNELGSBASE;
1001     msrs[n++].index = MSR_FMASK;
1002     msrs[n++].index = MSR_LSTAR;
1003 #endif
1004     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1005     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1006
1007     msr_data.info.nmsrs = n;
1008     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1009     if (ret < 0)
1010         return ret;
1011
1012     for (i = 0; i < ret; i++) {
1013         switch (msrs[i].index) {
1014         case MSR_IA32_SYSENTER_CS:
1015             env->sysenter_cs = msrs[i].data;
1016             break;
1017         case MSR_IA32_SYSENTER_ESP:
1018             env->sysenter_esp = msrs[i].data;
1019             break;
1020         case MSR_IA32_SYSENTER_EIP:
1021             env->sysenter_eip = msrs[i].data;
1022             break;
1023         case MSR_STAR:
1024             env->star = msrs[i].data;
1025             break;
1026 #ifdef TARGET_X86_64
1027         case MSR_CSTAR:
1028             env->cstar = msrs[i].data;
1029             break;
1030         case MSR_KERNELGSBASE:
1031             env->kernelgsbase = msrs[i].data;
1032             break;
1033         case MSR_FMASK:
1034             env->fmask = msrs[i].data;
1035             break;
1036         case MSR_LSTAR:
1037             env->lstar = msrs[i].data;
1038             break;
1039 #endif
1040         case MSR_IA32_TSC:
1041             env->tsc = msrs[i].data;
1042             break;
1043         case MSR_KVM_SYSTEM_TIME:
1044             env->system_time_msr = msrs[i].data;
1045             break;
1046         case MSR_KVM_WALL_CLOCK:
1047             env->wall_clock_msr = msrs[i].data;
1048             break;
1049         }
1050     }
1051
1052     return 0;
1053 }
1054
1055 static int kvm_put_mp_state(CPUState *env)
1056 {
1057     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1058
1059     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1060 }
1061
1062 static int kvm_get_mp_state(CPUState *env)
1063 {
1064     struct kvm_mp_state mp_state;
1065     int ret;
1066
1067     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1068     if (ret < 0) {
1069         return ret;
1070     }
1071     env->mp_state = mp_state.mp_state;
1072     return 0;
1073 }
1074
1075 static int kvm_put_vcpu_events(CPUState *env, int level)
1076 {
1077 #ifdef KVM_CAP_VCPU_EVENTS
1078     struct kvm_vcpu_events events;
1079
1080     if (!kvm_has_vcpu_events()) {
1081         return 0;
1082     }
1083
1084     events.exception.injected = (env->exception_injected >= 0);
1085     events.exception.nr = env->exception_injected;
1086     events.exception.has_error_code = env->has_error_code;
1087     events.exception.error_code = env->error_code;
1088
1089     events.interrupt.injected = (env->interrupt_injected >= 0);
1090     events.interrupt.nr = env->interrupt_injected;
1091     events.interrupt.soft = env->soft_interrupt;
1092
1093     events.nmi.injected = env->nmi_injected;
1094     events.nmi.pending = env->nmi_pending;
1095     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1096
1097     events.sipi_vector = env->sipi_vector;
1098
1099     events.flags = 0;
1100     if (level >= KVM_PUT_RESET_STATE) {
1101         events.flags |=
1102             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1103     }
1104
1105     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1106 #else
1107     return 0;
1108 #endif
1109 }
1110
1111 static int kvm_get_vcpu_events(CPUState *env)
1112 {
1113 #ifdef KVM_CAP_VCPU_EVENTS
1114     struct kvm_vcpu_events events;
1115     int ret;
1116
1117     if (!kvm_has_vcpu_events()) {
1118         return 0;
1119     }
1120
1121     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1122     if (ret < 0) {
1123        return ret;
1124     }
1125     env->exception_injected =
1126        events.exception.injected ? events.exception.nr : -1;
1127     env->has_error_code = events.exception.has_error_code;
1128     env->error_code = events.exception.error_code;
1129
1130     env->interrupt_injected =
1131         events.interrupt.injected ? events.interrupt.nr : -1;
1132     env->soft_interrupt = events.interrupt.soft;
1133
1134     env->nmi_injected = events.nmi.injected;
1135     env->nmi_pending = events.nmi.pending;
1136     if (events.nmi.masked) {
1137         env->hflags2 |= HF2_NMI_MASK;
1138     } else {
1139         env->hflags2 &= ~HF2_NMI_MASK;
1140     }
1141
1142     env->sipi_vector = events.sipi_vector;
1143 #endif
1144
1145     return 0;
1146 }
1147
1148 static int kvm_guest_debug_workarounds(CPUState *env)
1149 {
1150     int ret = 0;
1151 #ifdef KVM_CAP_SET_GUEST_DEBUG
1152     unsigned long reinject_trap = 0;
1153
1154     if (!kvm_has_vcpu_events()) {
1155         if (env->exception_injected == 1) {
1156             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1157         } else if (env->exception_injected == 3) {
1158             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1159         }
1160         env->exception_injected = -1;
1161     }
1162
1163     /*
1164      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1165      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1166      * by updating the debug state once again if single-stepping is on.
1167      * Another reason to call kvm_update_guest_debug here is a pending debug
1168      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1169      * reinject them via SET_GUEST_DEBUG.
1170      */
1171     if (reinject_trap ||
1172         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1173         ret = kvm_update_guest_debug(env, reinject_trap);
1174     }
1175 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1176     return ret;
1177 }
1178
1179 static int kvm_put_debugregs(CPUState *env)
1180 {
1181 #ifdef KVM_CAP_DEBUGREGS
1182     struct kvm_debugregs dbgregs;
1183     int i;
1184
1185     if (!kvm_has_debugregs()) {
1186         return 0;
1187     }
1188
1189     for (i = 0; i < 4; i++) {
1190         dbgregs.db[i] = env->dr[i];
1191     }
1192     dbgregs.dr6 = env->dr[6];
1193     dbgregs.dr7 = env->dr[7];
1194     dbgregs.flags = 0;
1195
1196     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1197 #else
1198     return 0;
1199 #endif
1200 }
1201
1202 static int kvm_get_debugregs(CPUState *env)
1203 {
1204 #ifdef KVM_CAP_DEBUGREGS
1205     struct kvm_debugregs dbgregs;
1206     int i, ret;
1207
1208     if (!kvm_has_debugregs()) {
1209         return 0;
1210     }
1211
1212     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1213     if (ret < 0) {
1214        return ret;
1215     }
1216     for (i = 0; i < 4; i++) {
1217         env->dr[i] = dbgregs.db[i];
1218     }
1219     env->dr[4] = env->dr[6] = dbgregs.dr6;
1220     env->dr[5] = env->dr[7] = dbgregs.dr7;
1221 #endif
1222
1223     return 0;
1224 }
1225
1226 int kvm_arch_put_registers(CPUState *env, int level)
1227 {
1228     int ret;
1229
1230     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1231
1232     ret = kvm_getput_regs(env, 1);
1233     if (ret < 0)
1234         return ret;
1235
1236     ret = kvm_put_xsave(env);
1237     if (ret < 0)
1238         return ret;
1239
1240     ret = kvm_put_xcrs(env);
1241     if (ret < 0)
1242         return ret;
1243
1244     ret = kvm_put_sregs(env);
1245     if (ret < 0)
1246         return ret;
1247
1248     ret = kvm_put_msrs(env, level);
1249     if (ret < 0)
1250         return ret;
1251
1252     if (level >= KVM_PUT_RESET_STATE) {
1253         ret = kvm_put_mp_state(env);
1254         if (ret < 0)
1255             return ret;
1256     }
1257
1258     ret = kvm_put_vcpu_events(env, level);
1259     if (ret < 0)
1260         return ret;
1261
1262     /* must be last */
1263     ret = kvm_guest_debug_workarounds(env);
1264     if (ret < 0)
1265         return ret;
1266
1267     ret = kvm_put_debugregs(env);
1268     if (ret < 0)
1269         return ret;
1270
1271     return 0;
1272 }
1273
1274 int kvm_arch_get_registers(CPUState *env)
1275 {
1276     int ret;
1277
1278     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1279
1280     ret = kvm_getput_regs(env, 0);
1281     if (ret < 0)
1282         return ret;
1283
1284     ret = kvm_get_xsave(env);
1285     if (ret < 0)
1286         return ret;
1287
1288     ret = kvm_get_xcrs(env);
1289     if (ret < 0)
1290         return ret;
1291
1292     ret = kvm_get_sregs(env);
1293     if (ret < 0)
1294         return ret;
1295
1296     ret = kvm_get_msrs(env);
1297     if (ret < 0)
1298         return ret;
1299
1300     ret = kvm_get_mp_state(env);
1301     if (ret < 0)
1302         return ret;
1303
1304     ret = kvm_get_vcpu_events(env);
1305     if (ret < 0)
1306         return ret;
1307
1308     ret = kvm_get_debugregs(env);
1309     if (ret < 0)
1310         return ret;
1311
1312     return 0;
1313 }
1314
1315 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1316 {
1317     /* Try to inject an interrupt if the guest can accept it */
1318     if (run->ready_for_interrupt_injection &&
1319         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1320         (env->eflags & IF_MASK)) {
1321         int irq;
1322
1323         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1324         irq = cpu_get_pic_interrupt(env);
1325         if (irq >= 0) {
1326             struct kvm_interrupt intr;
1327             intr.irq = irq;
1328             /* FIXME: errors */
1329             DPRINTF("injected interrupt %d\n", irq);
1330             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1331         }
1332     }
1333
1334     /* If we have an interrupt but the guest is not ready to receive an
1335      * interrupt, request an interrupt window exit.  This will
1336      * cause a return to userspace as soon as the guest is ready to
1337      * receive interrupts. */
1338     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1339         run->request_interrupt_window = 1;
1340     else
1341         run->request_interrupt_window = 0;
1342
1343     DPRINTF("setting tpr\n");
1344     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1345
1346     return 0;
1347 }
1348
1349 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1350 {
1351     if (run->if_flag)
1352         env->eflags |= IF_MASK;
1353     else
1354         env->eflags &= ~IF_MASK;
1355
1356     cpu_set_apic_tpr(env->apic_state, run->cr8);
1357     cpu_set_apic_base(env->apic_state, run->apic_base);
1358
1359     return 0;
1360 }
1361
1362 int kvm_arch_process_irqchip_events(CPUState *env)
1363 {
1364     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1365         kvm_cpu_synchronize_state(env);
1366         do_cpu_init(env);
1367         env->exception_index = EXCP_HALTED;
1368     }
1369
1370     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1371         kvm_cpu_synchronize_state(env);
1372         do_cpu_sipi(env);
1373     }
1374
1375     return env->halted;
1376 }
1377
1378 static int kvm_handle_halt(CPUState *env)
1379 {
1380     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1381           (env->eflags & IF_MASK)) &&
1382         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1383         env->halted = 1;
1384         env->exception_index = EXCP_HLT;
1385         return 0;
1386     }
1387
1388     return 1;
1389 }
1390
1391 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1392 {
1393     int ret = 0;
1394
1395     switch (run->exit_reason) {
1396     case KVM_EXIT_HLT:
1397         DPRINTF("handle_hlt\n");
1398         ret = kvm_handle_halt(env);
1399         break;
1400     }
1401
1402     return ret;
1403 }
1404
1405 #ifdef KVM_CAP_SET_GUEST_DEBUG
1406 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1407 {
1408     static const uint8_t int3 = 0xcc;
1409
1410     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1411         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
1412         return -EINVAL;
1413     return 0;
1414 }
1415
1416 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1417 {
1418     uint8_t int3;
1419
1420     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1421         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1422         return -EINVAL;
1423     return 0;
1424 }
1425
1426 static struct {
1427     target_ulong addr;
1428     int len;
1429     int type;
1430 } hw_breakpoint[4];
1431
1432 static int nb_hw_breakpoint;
1433
1434 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1435 {
1436     int n;
1437
1438     for (n = 0; n < nb_hw_breakpoint; n++)
1439         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1440             (hw_breakpoint[n].len == len || len == -1))
1441             return n;
1442     return -1;
1443 }
1444
1445 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1446                                   target_ulong len, int type)
1447 {
1448     switch (type) {
1449     case GDB_BREAKPOINT_HW:
1450         len = 1;
1451         break;
1452     case GDB_WATCHPOINT_WRITE:
1453     case GDB_WATCHPOINT_ACCESS:
1454         switch (len) {
1455         case 1:
1456             break;
1457         case 2:
1458         case 4:
1459         case 8:
1460             if (addr & (len - 1))
1461                 return -EINVAL;
1462             break;
1463         default:
1464             return -EINVAL;
1465         }
1466         break;
1467     default:
1468         return -ENOSYS;
1469     }
1470
1471     if (nb_hw_breakpoint == 4)
1472         return -ENOBUFS;
1473
1474     if (find_hw_breakpoint(addr, len, type) >= 0)
1475         return -EEXIST;
1476
1477     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1478     hw_breakpoint[nb_hw_breakpoint].len = len;
1479     hw_breakpoint[nb_hw_breakpoint].type = type;
1480     nb_hw_breakpoint++;
1481
1482     return 0;
1483 }
1484
1485 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1486                                   target_ulong len, int type)
1487 {
1488     int n;
1489
1490     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1491     if (n < 0)
1492         return -ENOENT;
1493
1494     nb_hw_breakpoint--;
1495     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1496
1497     return 0;
1498 }
1499
1500 void kvm_arch_remove_all_hw_breakpoints(void)
1501 {
1502     nb_hw_breakpoint = 0;
1503 }
1504
1505 static CPUWatchpoint hw_watchpoint;
1506
1507 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1508 {
1509     int handle = 0;
1510     int n;
1511
1512     if (arch_info->exception == 1) {
1513         if (arch_info->dr6 & (1 << 14)) {
1514             if (cpu_single_env->singlestep_enabled)
1515                 handle = 1;
1516         } else {
1517             for (n = 0; n < 4; n++)
1518                 if (arch_info->dr6 & (1 << n))
1519                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1520                     case 0x0:
1521                         handle = 1;
1522                         break;
1523                     case 0x1:
1524                         handle = 1;
1525                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1526                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1527                         hw_watchpoint.flags = BP_MEM_WRITE;
1528                         break;
1529                     case 0x3:
1530                         handle = 1;
1531                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1532                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1533                         hw_watchpoint.flags = BP_MEM_ACCESS;
1534                         break;
1535                     }
1536         }
1537     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1538         handle = 1;
1539
1540     if (!handle) {
1541         cpu_synchronize_state(cpu_single_env);
1542         assert(cpu_single_env->exception_injected == -1);
1543
1544         cpu_single_env->exception_injected = arch_info->exception;
1545         cpu_single_env->has_error_code = 0;
1546     }
1547
1548     return handle;
1549 }
1550
1551 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1552 {
1553     const uint8_t type_code[] = {
1554         [GDB_BREAKPOINT_HW] = 0x0,
1555         [GDB_WATCHPOINT_WRITE] = 0x1,
1556         [GDB_WATCHPOINT_ACCESS] = 0x3
1557     };
1558     const uint8_t len_code[] = {
1559         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1560     };
1561     int n;
1562
1563     if (kvm_sw_breakpoints_active(env))
1564         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1565
1566     if (nb_hw_breakpoint > 0) {
1567         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1568         dbg->arch.debugreg[7] = 0x0600;
1569         for (n = 0; n < nb_hw_breakpoint; n++) {
1570             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1571             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1572                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1573                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1574         }
1575     }
1576     /* Legal xcr0 for loading */
1577     env->xcr0 = 1;
1578 }
1579 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1580
1581 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1582 {
1583       return !(env->cr[0] & CR0_PE_MASK) ||
1584               ((env->segs[R_CS].selector  & 3) != 3);
1585 }
1586
1587 static void hardware_memory_error(void)
1588 {
1589     fprintf(stderr, "Hardware memory error!\n");
1590     exit(1);
1591 }
1592
1593 int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
1594 {
1595 #if defined(KVM_CAP_MCE)
1596     struct kvm_x86_mce mce = {
1597             .bank = 9,
1598     };
1599     void *vaddr;
1600     ram_addr_t ram_addr;
1601     target_phys_addr_t paddr;
1602     int r;
1603
1604     if ((env->mcg_cap & MCG_SER_P) && addr
1605         && (code == BUS_MCEERR_AR
1606             || code == BUS_MCEERR_AO)) {
1607         if (code == BUS_MCEERR_AR) {
1608             /* Fake an Intel architectural Data Load SRAR UCR */
1609             mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1610                 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1611                 | MCI_STATUS_AR | 0x134;
1612             mce.misc = (MCM_ADDR_PHYS << 6) | 0xc;
1613             mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV;
1614         } else {
1615             /*
1616              * If there is an MCE excpetion being processed, ignore
1617              * this SRAO MCE
1618              */
1619             r = kvm_mce_in_exception(env);
1620             if (r == -1) {
1621                 fprintf(stderr, "Failed to get MCE status\n");
1622             } else if (r) {
1623                 return 0;
1624             }
1625             /* Fake an Intel architectural Memory scrubbing UCR */
1626             mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1627                 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1628                 | 0xc0;
1629             mce.misc = (MCM_ADDR_PHYS << 6) | 0xc;
1630             mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
1631         }
1632         vaddr = (void *)addr;
1633         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1634             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) {
1635             fprintf(stderr, "Hardware memory error for memory used by "
1636                     "QEMU itself instead of guest system!\n");
1637             /* Hope we are lucky for AO MCE */
1638             if (code == BUS_MCEERR_AO) {
1639                 return 0;
1640             } else {
1641                 hardware_memory_error();
1642             }
1643         }
1644         mce.addr = paddr;
1645         r = kvm_set_mce(env, &mce);
1646         if (r < 0) {
1647             fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1648             abort();
1649         }
1650     } else
1651 #endif
1652     {
1653         if (code == BUS_MCEERR_AO) {
1654             return 0;
1655         } else if (code == BUS_MCEERR_AR) {
1656             hardware_memory_error();
1657         } else {
1658             return 1;
1659         }
1660     }
1661     return 0;
1662 }
1663
1664 int kvm_on_sigbus(int code, void *addr)
1665 {
1666 #if defined(KVM_CAP_MCE)
1667     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
1668         uint64_t status;
1669         void *vaddr;
1670         ram_addr_t ram_addr;
1671         target_phys_addr_t paddr;
1672         CPUState *cenv;
1673
1674         /* Hope we are lucky for AO MCE */
1675         vaddr = addr;
1676         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1677             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) {
1678             fprintf(stderr, "Hardware memory error for memory used by "
1679                     "QEMU itself instead of guest system!: %p\n", addr);
1680             return 0;
1681         }
1682         status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1683             | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1684             | 0xc0;
1685         kvm_inject_x86_mce(first_cpu, 9, status,
1686                            MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr,
1687                            (MCM_ADDR_PHYS << 6) | 0xc, 1);
1688         for (cenv = first_cpu->next_cpu; cenv != NULL; cenv = cenv->next_cpu) {
1689             kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC,
1690                                MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, 1);
1691         }
1692     } else
1693 #endif
1694     {
1695         if (code == BUS_MCEERR_AO) {
1696             return 0;
1697         } else if (code == BUS_MCEERR_AR) {
1698             hardware_memory_error();
1699         } else {
1700             return 1;
1701         }
1702     }
1703     return 0;
1704 }