target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27 #include "hw/pc.h"
  28 #include "hw/apic.h"
  29 #include "ioport.h"
  30
  31 #ifdef CONFIG_KVM_PARA
  32 #include <linux/kvm_para.h>
  33 #endif
  34 //
  35 //#define DEBUG_KVM
  36
  37 #ifdef DEBUG_KVM
  38 #define DPRINTF(fmt, ...) \
  39     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  40 #else
  41 #define DPRINTF(fmt, ...) \
  42     do { } while (0)
  43 #endif
  44
  45 #define MSR_KVM_WALL_CLOCK  0x11
  46 #define MSR_KVM_SYSTEM_TIME 0x12
  47
  48 #ifdef KVM_CAP_EXT_CPUID
  49
  50 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  51 {
  52     struct kvm_cpuid2 *cpuid;
  53     int r, size;
  54
  55     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  56     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  57     cpuid->nent = max;
  58     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  59     if (r == 0 && cpuid->nent >= max) {
  60         r = -E2BIG;
  61     }
  62     if (r < 0) {
  63         if (r == -E2BIG) {
  64             qemu_free(cpuid);
  65             return NULL;
  66         } else {
  67             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  68                     strerror(-r));
  69             exit(1);
  70         }
  71     }
  72     return cpuid;
  73 }
  74
  75 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  76                                       uint32_t index, int reg)
  77 {
  78     struct kvm_cpuid2 *cpuid;
  79     int i, max;
  80     uint32_t ret = 0;
  81     uint32_t cpuid_1_edx;
  82
  83     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  84         return -1U;
  85     }
  86
  87     max = 1;
  88     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  89         max *= 2;
  90     }
  91
  92     for (i = 0; i < cpuid->nent; ++i) {
  93         if (cpuid->entries[i].function == function &&
  94             cpuid->entries[i].index == index) {
  95             switch (reg) {
  96             case R_EAX:
  97                 ret = cpuid->entries[i].eax;
  98                 break;
  99             case R_EBX:
 100                 ret = cpuid->entries[i].ebx;
 101                 break;
 102             case R_ECX:
 103                 ret = cpuid->entries[i].ecx;
 104                 break;
 105             case R_EDX:
 106                 ret = cpuid->entries[i].edx;
 107                 switch (function) {
 108                 case 1:
 109                     /* KVM before 2.6.30 misreports the following features */
 110                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 111                     break;
 112                 case 0x80000001:
 113                     /* On Intel, kvm returns cpuid according to the Intel spec,
 114                      * so add missing bits according to the AMD spec:
 115                      */
 116                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 117                     ret |= cpuid_1_edx & 0x183f7ff;
 118                     break;
 119                 }
 120                 break;
 121             }
 122         }
 123     }
 124
 125     qemu_free(cpuid);
 126
 127     return ret;
 128 }
 129
 130 #else
 131
 132 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
 133                                       uint32_t index, int reg)
 134 {
 135     return -1U;
 136 }
 137
 138 #endif
 139
 140 #ifdef CONFIG_KVM_PARA
 141 struct kvm_para_features {
 142         int cap;
 143         int feature;
 144 } para_features[] = {
 145 #ifdef KVM_CAP_CLOCKSOURCE
 146         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 147 #endif
 148 #ifdef KVM_CAP_NOP_IO_DELAY
 149         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 150 #endif
 151 #ifdef KVM_CAP_PV_MMU
 152         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 153 #endif
 154         { -1, -1 }
 155 };
 156
 157 static int get_para_features(CPUState *env)
 158 {
 159         int i, features = 0;
 160
 161         for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 162                 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
 163                         features |= (1 << para_features[i].feature);
 164         }
 165
 166         return features;
 167 }
 168 #endif
 169
 170 static int _kvm_arch_init_vcpu(CPUState *env);
 171
 172 int kvm_arch_init_vcpu(CPUState *env)
 173 {
 174     int r;
 175     struct {
 176         struct kvm_cpuid2 cpuid;
 177         struct kvm_cpuid_entry2 entries[100];
 178     } __attribute__((packed)) cpuid_data;
 179     uint32_t limit, i, j, cpuid_i;
 180     uint32_t unused;
 181     struct kvm_cpuid_entry2 *c;
 182 #ifdef KVM_CPUID_SIGNATURE
 183     uint32_t signature[3];
 184 #endif
 185
 186     r = _kvm_arch_init_vcpu(env);
 187     if (r < 0) {
 188         return r;
 189     }
 190
 191 #ifdef KVM_UPSTREAM
 192
 193     env->mp_state = KVM_MP_STATE_RUNNABLE;
 194
 195 #endif
 196
 197     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 198
 199     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 200     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 201     env->cpuid_ext_features |= i;
 202
 203     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 204                                                              0, R_EDX);
 205     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 206                                                              0, R_ECX);
 207
 208     cpuid_i = 0;
 209
 210 #ifdef CONFIG_KVM_PARA
 211     /* Paravirtualization CPUIDs */
 212     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 213     c = &cpuid_data.entries[cpuid_i++];
 214     memset(c, 0, sizeof(*c));
 215     c->function = KVM_CPUID_SIGNATURE;
 216     c->eax = 0;
 217     c->ebx = signature[0];
 218     c->ecx = signature[1];
 219     c->edx = signature[2];
 220
 221     c = &cpuid_data.entries[cpuid_i++];
 222     memset(c, 0, sizeof(*c));
 223     c->function = KVM_CPUID_FEATURES;
 224     c->eax = env->cpuid_kvm_features & get_para_features(env);
 225 #endif
 226
 227     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 228
 229     for (i = 0; i <= limit; i++) {
 230         c = &cpuid_data.entries[cpuid_i++];
 231
 232         switch (i) {
 233         case 2: {
 234             /* Keep reading function 2 till all the input is received */
 235             int times;
 236
 237             c->function = i;
 238             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 239                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 240             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 241             times = c->eax & 0xff;
 242
 243             for (j = 1; j < times; ++j) {
 244                 c = &cpuid_data.entries[cpuid_i++];
 245                 c->function = i;
 246                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 247                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 248             }
 249             break;
 250         }
 251         case 4:
 252         case 0xb:
 253         case 0xd:
 254             for (j = 0; ; j++) {
 255                 c->function = i;
 256                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 257                 c->index = j;
 258                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 259
 260                 if (i == 4 && c->eax == 0)
 261                     break;
 262                 if (i == 0xb && !(c->ecx & 0xff00))
 263                     break;
 264                 if (i == 0xd && c->eax == 0)
 265                     break;
 266
 267                 c = &cpuid_data.entries[cpuid_i++];
 268             }
 269             break;
 270         default:
 271             c->function = i;
 272             c->flags = 0;
 273             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 274             break;
 275         }
 276     }
 277     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 278
 279     for (i = 0x80000000; i <= limit; i++) {
 280         c = &cpuid_data.entries[cpuid_i++];
 281
 282         c->function = i;
 283         c->flags = 0;
 284         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 285     }
 286
 287     cpuid_data.cpuid.nent = cpuid_i;
 288
 289     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 290 }
 291
 292 void kvm_arch_reset_vcpu(CPUState *env)
 293 {
 294     env->exception_injected = -1;
 295     env->interrupt_injected = -1;
 296     env->nmi_injected = 0;
 297     env->nmi_pending = 0;
 298     /* Legal xcr0 for loading */
 299     env->xcr0 = 1;
 300     if (kvm_irqchip_in_kernel()) {
 301         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 302                                           KVM_MP_STATE_UNINITIALIZED;
 303     } else {
 304         env->mp_state = KVM_MP_STATE_RUNNABLE;
 305     }
 306 }
 307 #ifdef KVM_UPSTREAM
 308
 309 static int kvm_has_msr_star(CPUState *env)
 310 {
 311     static int has_msr_star;
 312     int ret;
 313
 314     /* first time */
 315     if (has_msr_star == 0) {
 316         struct kvm_msr_list msr_list, *kvm_msr_list;
 317
 318         has_msr_star = -1;
 319
 320         /* Obtain MSR list from KVM.  These are the MSRs that we must
 321          * save/restore */
 322         msr_list.nmsrs = 0;
 323         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 324         if (ret < 0 && ret != -E2BIG) {
 325             return 0;
 326         }
 327         /* Old kernel modules had a bug and could write beyond the provided
 328            memory. Allocate at least a safe amount of 1K. */
 329         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 330                                               msr_list.nmsrs *
 331                                               sizeof(msr_list.indices[0])));
 332
 333         kvm_msr_list->nmsrs = msr_list.nmsrs;
 334         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 335         if (ret >= 0) {
 336             int i;
 337
 338             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 339                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 340                     has_msr_star = 1;
 341                     break;
 342                 }
 343             }
 344         }
 345
 346         free(kvm_msr_list);
 347     }
 348
 349     if (has_msr_star == 1)
 350         return 1;
 351     return 0;
 352 }
 353
 354 static int kvm_init_identity_map_page(KVMState *s)
 355 {
 356 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 357     int ret;
 358     uint64_t addr = 0xfffbc000;
 359
 360     if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 361         return 0;
 362     }
 363
 364     ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
 365     if (ret < 0) {
 366         fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
 367         return ret;
 368     }
 369 #endif
 370     return 0;
 371 }
 372
 373 int kvm_arch_init(KVMState *s, int smp_cpus)
 374 {
 375     int ret;
 376
 377     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 378      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 379      * must be part of guest physical memory, we need to allocate it.  Older
 380      * versions of KVM just assumed that it would be at the end of physical
 381      * memory but that doesn't work with more than 4GB of memory.  We simply
 382      * refuse to work with those older versions of KVM. */
 383     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 384     if (ret <= 0) {
 385         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 386         return ret;
 387     }
 388
 389     /* this address is 3 pages before the bios, and the bios should present
 390      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 391      * this?
 392      */
 393     /*
 394      * Tell fw_cfg to notify the BIOS to reserve the range.
 395      */
 396     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 397         perror("e820_add_entry() table is full");
 398         exit(1);
 399     }
 400     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 401     if (ret < 0) {
 402         return ret;
 403     }
 404
 405     return kvm_init_identity_map_page(s);
 406 }
 407
 408 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 409 {
 410     lhs->selector = rhs->selector;
 411     lhs->base = rhs->base;
 412     lhs->limit = rhs->limit;
 413     lhs->type = 3;
 414     lhs->present = 1;
 415     lhs->dpl = 3;
 416     lhs->db = 0;
 417     lhs->s = 1;
 418     lhs->l = 0;
 419     lhs->g = 0;
 420     lhs->avl = 0;
 421     lhs->unusable = 0;
 422 }
 423
 424 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 425 {
 426     unsigned flags = rhs->flags;
 427     lhs->selector = rhs->selector;
 428     lhs->base = rhs->base;
 429     lhs->limit = rhs->limit;
 430     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 431     lhs->present = (flags & DESC_P_MASK) != 0;
 432     lhs->dpl = rhs->selector & 3;
 433     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 434     lhs->s = (flags & DESC_S_MASK) != 0;
 435     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 436     lhs->g = (flags & DESC_G_MASK) != 0;
 437     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 438     lhs->unusable = 0;
 439 }
 440
 441 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 442 {
 443     lhs->selector = rhs->selector;
 444     lhs->base = rhs->base;
 445     lhs->limit = rhs->limit;
 446     lhs->flags =
 447         (rhs->type << DESC_TYPE_SHIFT)
 448         | (rhs->present * DESC_P_MASK)
 449         | (rhs->dpl << DESC_DPL_SHIFT)
 450         | (rhs->db << DESC_B_SHIFT)
 451         | (rhs->s * DESC_S_MASK)
 452         | (rhs->l << DESC_L_SHIFT)
 453         | (rhs->g * DESC_G_MASK)
 454         | (rhs->avl * DESC_AVL_MASK);
 455 }
 456
 457 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 458 {
 459     if (set)
 460         *kvm_reg = *qemu_reg;
 461     else
 462         *qemu_reg = *kvm_reg;
 463 }
 464
 465 static int kvm_getput_regs(CPUState *env, int set)
 466 {
 467     struct kvm_regs regs;
 468     int ret = 0;
 469
 470     if (!set) {
 471         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 472         if (ret < 0)
 473             return ret;
 474     }
 475
 476     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 477     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 478     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 479     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 480     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 481     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 482     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 483     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 484 #ifdef TARGET_X86_64
 485     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 486     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 487     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 488     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 489     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 490     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 491     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 492     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 493 #endif
 494
 495     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 496     kvm_getput_reg(&regs.rip, &env->eip, set);
 497
 498     if (set)
 499         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 500
 501     return ret;
 502 }
 503
 504 static int kvm_put_fpu(CPUState *env)
 505 {
 506     struct kvm_fpu fpu;
 507     int i;
 508
 509     memset(&fpu, 0, sizeof fpu);
 510     fpu.fsw = env->fpus & ~(7 << 11);
 511     fpu.fsw |= (env->fpstt & 7) << 11;
 512     fpu.fcw = env->fpuc;
 513     for (i = 0; i < 8; ++i)
 514         fpu.ftwx |= (!env->fptags[i]) << i;
 515     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 516     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 517     fpu.mxcsr = env->mxcsr;
 518
 519     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 520 }
 521
 522 #ifdef KVM_CAP_XSAVE
 523 #define XSAVE_CWD_RIP     2
 524 #define XSAVE_CWD_RDP     4
 525 #define XSAVE_MXCSR       6
 526 #define XSAVE_ST_SPACE    8
 527 #define XSAVE_XMM_SPACE   40
 528 #define XSAVE_XSTATE_BV   128
 529 #define XSAVE_YMMH_SPACE  144
 530 #endif
 531
 532 static int kvm_put_xsave(CPUState *env)
 533 {
 534 #ifdef KVM_CAP_XSAVE
 535     int i;
 536     struct kvm_xsave* xsave;
 537     uint16_t cwd, swd, twd, fop;
 538
 539     if (!kvm_has_xsave())
 540         return kvm_put_fpu(env);
 541
 542     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 543     memset(xsave, 0, sizeof(struct kvm_xsave));
 544     cwd = swd = twd = fop = 0;
 545     swd = env->fpus & ~(7 << 11);
 546     swd |= (env->fpstt & 7) << 11;
 547     cwd = env->fpuc;
 548     for (i = 0; i < 8; ++i)
 549         twd |= (!env->fptags[i]) << i;
 550     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 551     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 552     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 553             sizeof env->fpregs);
 554     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 555             sizeof env->xmm_regs);
 556     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 557     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 558     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 559             sizeof env->ymmh_regs);
 560     return kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 561 #else
 562     return kvm_put_fpu(env);
 563 #endif
 564 }
 565
 566 static int kvm_put_xcrs(CPUState *env)
 567 {
 568 #ifdef KVM_CAP_XCRS
 569     struct kvm_xcrs xcrs;
 570
 571     if (!kvm_has_xcrs())
 572         return 0;
 573
 574     xcrs.nr_xcrs = 1;
 575     xcrs.flags = 0;
 576     xcrs.xcrs[0].xcr = 0;
 577     xcrs.xcrs[0].value = env->xcr0;
 578     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 579 #else
 580     return 0;
 581 #endif
 582 }
 583
 584 static int kvm_put_sregs(CPUState *env)
 585 {
 586     struct kvm_sregs sregs;
 587
 588     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 589     if (env->interrupt_injected >= 0) {
 590         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 591                 (uint64_t)1 << (env->interrupt_injected % 64);
 592     }
 593
 594     if ((env->eflags & VM_MASK)) {
 595             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 596             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 597             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 598             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 599             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 600             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 601     } else {
 602             set_seg(&sregs.cs, &env->segs[R_CS]);
 603             set_seg(&sregs.ds, &env->segs[R_DS]);
 604             set_seg(&sregs.es, &env->segs[R_ES]);
 605             set_seg(&sregs.fs, &env->segs[R_FS]);
 606             set_seg(&sregs.gs, &env->segs[R_GS]);
 607             set_seg(&sregs.ss, &env->segs[R_SS]);
 608
 609             if (env->cr[0] & CR0_PE_MASK) {
 610                 /* force ss cpl to cs cpl */
 611                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 612                         (sregs.cs.selector & 3);
 613                 sregs.ss.dpl = sregs.ss.selector & 3;
 614             }
 615     }
 616
 617     set_seg(&sregs.tr, &env->tr);
 618     set_seg(&sregs.ldt, &env->ldt);
 619
 620     sregs.idt.limit = env->idt.limit;
 621     sregs.idt.base = env->idt.base;
 622     sregs.gdt.limit = env->gdt.limit;
 623     sregs.gdt.base = env->gdt.base;
 624
 625     sregs.cr0 = env->cr[0];
 626     sregs.cr2 = env->cr[2];
 627     sregs.cr3 = env->cr[3];
 628     sregs.cr4 = env->cr[4];
 629
 630     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 631     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 632
 633     sregs.efer = env->efer;
 634
 635     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 636 }
 637
 638 #endif
 639
 640 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 641                               uint32_t index, uint64_t value)
 642 {
 643     entry->index = index;
 644     entry->data = value;
 645 }
 646
 647 #ifdef KVM_UPSTREAM
 648 static int kvm_put_msrs(CPUState *env, int level)
 649 {
 650     struct {
 651         struct kvm_msrs info;
 652         struct kvm_msr_entry entries[100];
 653     } msr_data;
 654     struct kvm_msr_entry *msrs = msr_data.entries;
 655     int n = 0;
 656
 657     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 658     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 659     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 660     if (kvm_has_msr_star(env))
 661         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 662     kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 663 #ifdef TARGET_X86_64
 664     /* FIXME if lm capable */
 665     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 666     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 667     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 668     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 669 #endif
 670     if (level == KVM_PUT_FULL_STATE) {
 671         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 672         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 673                           env->system_time_msr);
 674         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 675     }
 676
 677     msr_data.info.nmsrs = n;
 678
 679     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 680
 681 }
 682
 683
 684 static int kvm_get_fpu(CPUState *env)
 685 {
 686     struct kvm_fpu fpu;
 687     int i, ret;
 688
 689     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 690     if (ret < 0)
 691         return ret;
 692
 693     env->fpstt = (fpu.fsw >> 11) & 7;
 694     env->fpus = fpu.fsw;
 695     env->fpuc = fpu.fcw;
 696     for (i = 0; i < 8; ++i)
 697         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 698     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 699     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 700     env->mxcsr = fpu.mxcsr;
 701
 702     return 0;
 703 }
 704
 705 static int kvm_get_xsave(CPUState *env)
 706 {
 707 #ifdef KVM_CAP_XSAVE
 708     struct kvm_xsave* xsave;
 709     int ret, i;
 710     uint16_t cwd, swd, twd, fop;
 711
 712     if (!kvm_has_xsave())
 713         return kvm_get_fpu(env);
 714
 715     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 716     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 717     if (ret < 0)
 718         return ret;
 719
 720     cwd = (uint16_t)xsave->region[0];
 721     swd = (uint16_t)(xsave->region[0] >> 16);
 722     twd = (uint16_t)xsave->region[1];
 723     fop = (uint16_t)(xsave->region[1] >> 16);
 724     env->fpstt = (swd >> 11) & 7;
 725     env->fpus = swd;
 726     env->fpuc = cwd;
 727     for (i = 0; i < 8; ++i)
 728         env->fptags[i] = !((twd >> i) & 1);
 729     env->mxcsr = xsave->region[XSAVE_MXCSR];
 730     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 731             sizeof env->fpregs);
 732     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 733             sizeof env->xmm_regs);
 734     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 735     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 736             sizeof env->ymmh_regs);
 737     return 0;
 738 #else
 739     return kvm_get_fpu(env);
 740 #endif
 741 }
 742
 743 static int kvm_get_xcrs(CPUState *env)
 744 {
 745 #ifdef KVM_CAP_XCRS
 746     int i, ret;
 747     struct kvm_xcrs xcrs;
 748
 749     if (!kvm_has_xcrs())
 750         return 0;
 751
 752     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
 753     if (ret < 0)
 754         return ret;
 755
 756     for (i = 0; i < xcrs.nr_xcrs; i++)
 757         /* Only support xcr0 now */
 758         if (xcrs.xcrs[0].xcr == 0) {
 759             env->xcr0 = xcrs.xcrs[0].value;
 760             break;
 761         }
 762     return 0;
 763 #else
 764     return 0;
 765 #endif
 766 }
 767
 768 static int kvm_get_sregs(CPUState *env)
 769 {
 770     struct kvm_sregs sregs;
 771     uint32_t hflags;
 772     int bit, i, ret;
 773
 774     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 775     if (ret < 0)
 776         return ret;
 777
 778     /* There can only be one pending IRQ set in the bitmap at a time, so try
 779        to find it and save its number instead (-1 for none). */
 780     env->interrupt_injected = -1;
 781     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 782         if (sregs.interrupt_bitmap[i]) {
 783             bit = ctz64(sregs.interrupt_bitmap[i]);
 784             env->interrupt_injected = i * 64 + bit;
 785             break;
 786         }
 787     }
 788
 789     get_seg(&env->segs[R_CS], &sregs.cs);
 790     get_seg(&env->segs[R_DS], &sregs.ds);
 791     get_seg(&env->segs[R_ES], &sregs.es);
 792     get_seg(&env->segs[R_FS], &sregs.fs);
 793     get_seg(&env->segs[R_GS], &sregs.gs);
 794     get_seg(&env->segs[R_SS], &sregs.ss);
 795
 796     get_seg(&env->tr, &sregs.tr);
 797     get_seg(&env->ldt, &sregs.ldt);
 798
 799     env->idt.limit = sregs.idt.limit;
 800     env->idt.base = sregs.idt.base;
 801     env->gdt.limit = sregs.gdt.limit;
 802     env->gdt.base = sregs.gdt.base;
 803
 804     env->cr[0] = sregs.cr0;
 805     env->cr[2] = sregs.cr2;
 806     env->cr[3] = sregs.cr3;
 807     env->cr[4] = sregs.cr4;
 808
 809     cpu_set_apic_base(env->apic_state, sregs.apic_base);
 810
 811     env->efer = sregs.efer;
 812     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
 813
 814 #define HFLAG_COPY_MASK ~( \
 815                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 816                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 817                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 818                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 819
 820
 821
 822     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 823     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 824     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 825             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 826     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 827     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 828             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 829
 830     if (env->efer & MSR_EFER_LMA) {
 831         hflags |= HF_LMA_MASK;
 832     }
 833
 834     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 835         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 836     } else {
 837         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 838                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 839         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 840                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 841         if (!(env->cr[0] & CR0_PE_MASK) ||
 842                    (env->eflags & VM_MASK) ||
 843                    !(hflags & HF_CS32_MASK)) {
 844                 hflags |= HF_ADDSEG_MASK;
 845             } else {
 846                 hflags |= ((env->segs[R_DS].base |
 847                                 env->segs[R_ES].base |
 848                                 env->segs[R_SS].base) != 0) <<
 849                     HF_ADDSEG_SHIFT;
 850             }
 851     }
 852     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 853
 854     return 0;
 855 }
 856
 857 static int kvm_get_msrs(CPUState *env)
 858 {
 859     struct {
 860         struct kvm_msrs info;
 861         struct kvm_msr_entry entries[100];
 862     } msr_data;
 863     struct kvm_msr_entry *msrs = msr_data.entries;
 864     int ret, i, n;
 865
 866     n = 0;
 867     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 868     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 869     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 870     if (kvm_has_msr_star(env))
 871         msrs[n++].index = MSR_STAR;
 872     msrs[n++].index = MSR_IA32_TSC;
 873     msrs[n++].index = MSR_VM_HSAVE_PA;
 874 #ifdef TARGET_X86_64
 875     /* FIXME lm_capable_kernel */
 876     msrs[n++].index = MSR_CSTAR;
 877     msrs[n++].index = MSR_KERNELGSBASE;
 878     msrs[n++].index = MSR_FMASK;
 879     msrs[n++].index = MSR_LSTAR;
 880 #endif
 881     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
 882     msrs[n++].index = MSR_KVM_WALL_CLOCK;
 883
 884     msr_data.info.nmsrs = n;
 885     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 886     if (ret < 0)
 887         return ret;
 888
 889     for (i = 0; i < ret; i++) {
 890         switch (msrs[i].index) {
 891         case MSR_IA32_SYSENTER_CS:
 892             env->sysenter_cs = msrs[i].data;
 893             break;
 894         case MSR_IA32_SYSENTER_ESP:
 895             env->sysenter_esp = msrs[i].data;
 896             break;
 897         case MSR_IA32_SYSENTER_EIP:
 898             env->sysenter_eip = msrs[i].data;
 899             break;
 900         case MSR_STAR:
 901             env->star = msrs[i].data;
 902             break;
 903 #ifdef TARGET_X86_64
 904         case MSR_CSTAR:
 905             env->cstar = msrs[i].data;
 906             break;
 907         case MSR_KERNELGSBASE:
 908             env->kernelgsbase = msrs[i].data;
 909             break;
 910         case MSR_FMASK:
 911             env->fmask = msrs[i].data;
 912             break;
 913         case MSR_LSTAR:
 914             env->lstar = msrs[i].data;
 915             break;
 916 #endif
 917         case MSR_IA32_TSC:
 918             env->tsc = msrs[i].data;
 919             break;
 920         case MSR_KVM_SYSTEM_TIME:
 921             env->system_time_msr = msrs[i].data;
 922             break;
 923         case MSR_KVM_WALL_CLOCK:
 924             env->wall_clock_msr = msrs[i].data;
 925             break;
 926         case MSR_VM_HSAVE_PA:
 927             env->vm_hsave = msrs[i].data;
 928             break;
 929         }
 930     }
 931
 932     return 0;
 933 }
 934
 935 static int kvm_put_mp_state(CPUState *env)
 936 {
 937     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 938
 939     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
 940 }
 941
 942 static int kvm_get_mp_state(CPUState *env)
 943 {
 944     struct kvm_mp_state mp_state;
 945     int ret;
 946
 947     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
 948     if (ret < 0) {
 949         return ret;
 950     }
 951     env->mp_state = mp_state.mp_state;
 952     return 0;
 953 }
 954 #endif
 955
 956 static int kvm_put_vcpu_events(CPUState *env, int level)
 957 {
 958 #ifdef KVM_CAP_VCPU_EVENTS
 959     struct kvm_vcpu_events events;
 960
 961     if (!kvm_has_vcpu_events()) {
 962         return 0;
 963     }
 964
 965     events.exception.injected = (env->exception_injected >= 0);
 966     events.exception.nr = env->exception_injected;
 967     events.exception.has_error_code = env->has_error_code;
 968     events.exception.error_code = env->error_code;
 969
 970     events.interrupt.injected = (env->interrupt_injected >= 0);
 971     events.interrupt.nr = env->interrupt_injected;
 972     events.interrupt.soft = env->soft_interrupt;
 973
 974     events.nmi.injected = env->nmi_injected;
 975     events.nmi.pending = env->nmi_pending;
 976     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
 977
 978     events.sipi_vector = env->sipi_vector;
 979
 980     events.flags = 0;
 981     if (level >= KVM_PUT_RESET_STATE) {
 982         events.flags |=
 983             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
 984     }
 985
 986     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
 987 #else
 988     return 0;
 989 #endif
 990 }
 991
 992 static int kvm_get_vcpu_events(CPUState *env)
 993 {
 994 #ifdef KVM_CAP_VCPU_EVENTS
 995     struct kvm_vcpu_events events;
 996     int ret;
 997
 998     if (!kvm_has_vcpu_events()) {
 999         return 0;
1000     }
1001
1002     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1003     if (ret < 0) {
1004        return ret;
1005     }
1006     env->exception_injected =
1007        events.exception.injected ? events.exception.nr : -1;
1008     env->has_error_code = events.exception.has_error_code;
1009     env->error_code = events.exception.error_code;
1010
1011     env->interrupt_injected =
1012         events.interrupt.injected ? events.interrupt.nr : -1;
1013     env->soft_interrupt = events.interrupt.soft;
1014
1015     env->nmi_injected = events.nmi.injected;
1016     env->nmi_pending = events.nmi.pending;
1017     if (events.nmi.masked) {
1018         env->hflags2 |= HF2_NMI_MASK;
1019     } else {
1020         env->hflags2 &= ~HF2_NMI_MASK;
1021     }
1022
1023     env->sipi_vector = events.sipi_vector;
1024 #endif
1025
1026     return 0;
1027 }
1028
1029 static int kvm_guest_debug_workarounds(CPUState *env)
1030 {
1031     int ret = 0;
1032 #ifdef KVM_CAP_SET_GUEST_DEBUG
1033     unsigned long reinject_trap = 0;
1034
1035     if (!kvm_has_vcpu_events()) {
1036         if (env->exception_injected == 1) {
1037             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1038         } else if (env->exception_injected == 3) {
1039             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1040         }
1041         env->exception_injected = -1;
1042     }
1043
1044     /*
1045      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1046      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1047      * by updating the debug state once again if single-stepping is on.
1048      * Another reason to call kvm_update_guest_debug here is a pending debug
1049      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1050      * reinject them via SET_GUEST_DEBUG.
1051      */
1052     if (reinject_trap ||
1053         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1054         ret = kvm_update_guest_debug(env, reinject_trap);
1055     }
1056 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1057     return ret;
1058 }
1059
1060 static int kvm_put_debugregs(CPUState *env)
1061 {
1062 #ifdef KVM_CAP_DEBUGREGS
1063     struct kvm_debugregs dbgregs;
1064     int i;
1065
1066     if (!kvm_has_debugregs()) {
1067         return 0;
1068     }
1069
1070     for (i = 0; i < 4; i++) {
1071         dbgregs.db[i] = env->dr[i];
1072     }
1073     dbgregs.dr6 = env->dr[6];
1074     dbgregs.dr7 = env->dr[7];
1075     dbgregs.flags = 0;
1076
1077     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1078 #else
1079     return 0;
1080 #endif
1081 }
1082
1083 static int kvm_get_debugregs(CPUState *env)
1084 {
1085 #ifdef KVM_CAP_DEBUGREGS
1086     struct kvm_debugregs dbgregs;
1087     int i, ret;
1088
1089     if (!kvm_has_debugregs()) {
1090         return 0;
1091     }
1092
1093     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1094     if (ret < 0) {
1095        return ret;
1096     }
1097     for (i = 0; i < 4; i++) {
1098         env->dr[i] = dbgregs.db[i];
1099     }
1100     env->dr[4] = env->dr[6] = dbgregs.dr6;
1101     env->dr[5] = env->dr[7] = dbgregs.dr7;
1102 #endif
1103
1104     return 0;
1105 }
1106
1107 #ifdef KVM_UPSTREAM
1108 int kvm_arch_put_registers(CPUState *env, int level)
1109 {
1110     int ret;
1111
1112     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1113
1114     ret = kvm_getput_regs(env, 1);
1115     if (ret < 0)
1116         return ret;
1117
1118     ret = kvm_put_xsave(env);
1119     if (ret < 0)
1120         return ret;
1121
1122     ret = kvm_put_xcrs(env);
1123     if (ret < 0)
1124         return ret;
1125
1126     ret = kvm_put_sregs(env);
1127     if (ret < 0)
1128         return ret;
1129
1130     ret = kvm_put_msrs(env, level);
1131     if (ret < 0)
1132         return ret;
1133
1134     if (level >= KVM_PUT_RESET_STATE) {
1135         ret = kvm_put_mp_state(env);
1136         if (ret < 0)
1137             return ret;
1138     }
1139
1140     ret = kvm_put_vcpu_events(env, level);
1141     if (ret < 0)
1142         return ret;
1143
1144     /* must be last */
1145     ret = kvm_guest_debug_workarounds(env);
1146     if (ret < 0)
1147         return ret;
1148
1149     ret = kvm_put_debugregs(env);
1150     if (ret < 0)
1151         return ret;
1152
1153     return 0;
1154 }
1155
1156 int kvm_arch_get_registers(CPUState *env)
1157 {
1158     int ret;
1159
1160     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1161
1162     ret = kvm_getput_regs(env, 0);
1163     if (ret < 0)
1164         return ret;
1165
1166     ret = kvm_get_xsave(env);
1167     if (ret < 0)
1168         return ret;
1169
1170     ret = kvm_get_xcrs(env);
1171     if (ret < 0)
1172         return ret;
1173
1174     ret = kvm_get_sregs(env);
1175     if (ret < 0)
1176         return ret;
1177
1178     ret = kvm_get_msrs(env);
1179     if (ret < 0)
1180         return ret;
1181
1182     ret = kvm_get_mp_state(env);
1183     if (ret < 0)
1184         return ret;
1185
1186     ret = kvm_get_vcpu_events(env);
1187     if (ret < 0)
1188         return ret;
1189
1190     ret = kvm_get_debugregs(env);
1191     if (ret < 0)
1192         return ret;
1193
1194     return 0;
1195 }
1196
1197 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1198 {
1199     /* Try to inject an interrupt if the guest can accept it */
1200     if (run->ready_for_interrupt_injection &&
1201         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1202         (env->eflags & IF_MASK)) {
1203         int irq;
1204
1205         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1206         irq = cpu_get_pic_interrupt(env);
1207         if (irq >= 0) {
1208             struct kvm_interrupt intr;
1209             intr.irq = irq;
1210             /* FIXME: errors */
1211             DPRINTF("injected interrupt %d\n", irq);
1212             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1213         }
1214     }
1215
1216     /* If we have an interrupt but the guest is not ready to receive an
1217      * interrupt, request an interrupt window exit.  This will
1218      * cause a return to userspace as soon as the guest is ready to
1219      * receive interrupts. */
1220     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1221         run->request_interrupt_window = 1;
1222     else
1223         run->request_interrupt_window = 0;
1224
1225     DPRINTF("setting tpr\n");
1226     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1227
1228     return 0;
1229 }
1230 #endif
1231
1232 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1233 {
1234     if (run->if_flag)
1235         env->eflags |= IF_MASK;
1236     else
1237         env->eflags &= ~IF_MASK;
1238
1239     cpu_set_apic_tpr(env->apic_state, run->cr8);
1240     cpu_set_apic_base(env->apic_state, run->apic_base);
1241
1242     return 0;
1243 }
1244
1245 #ifdef KVM_UPSTREAM
1246
1247 int kvm_arch_process_irqchip_events(CPUState *env)
1248 {
1249     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1250         kvm_cpu_synchronize_state(env);
1251         do_cpu_init(env);
1252         env->exception_index = EXCP_HALTED;
1253     }
1254
1255     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1256         kvm_cpu_synchronize_state(env);
1257         do_cpu_sipi(env);
1258     }
1259
1260     return env->halted;
1261 }
1262
1263 static int kvm_handle_halt(CPUState *env)
1264 {
1265     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1266           (env->eflags & IF_MASK)) &&
1267         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1268         env->halted = 1;
1269         env->exception_index = EXCP_HLT;
1270         return 0;
1271     }
1272
1273     return 1;
1274 }
1275
1276 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1277 {
1278     int ret = 0;
1279
1280     switch (run->exit_reason) {
1281     case KVM_EXIT_HLT:
1282         DPRINTF("handle_hlt\n");
1283         ret = kvm_handle_halt(env);
1284         break;
1285     }
1286
1287     return ret;
1288 }
1289 #endif
1290
1291 #ifdef KVM_CAP_SET_GUEST_DEBUG
1292 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1293 {
1294     static const uint8_t int3 = 0xcc;
1295
1296     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1297         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
1298         return -EINVAL;
1299     return 0;
1300 }
1301
1302 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1303 {
1304     uint8_t int3;
1305
1306     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1307         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1308         return -EINVAL;
1309     return 0;
1310 }
1311
1312 static struct {
1313     target_ulong addr;
1314     int len;
1315     int type;
1316 } hw_breakpoint[4];
1317
1318 static int nb_hw_breakpoint;
1319
1320 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1321 {
1322     int n;
1323
1324     for (n = 0; n < nb_hw_breakpoint; n++)
1325         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1326             (hw_breakpoint[n].len == len || len == -1))
1327             return n;
1328     return -1;
1329 }
1330
1331 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1332                                   target_ulong len, int type)
1333 {
1334     switch (type) {
1335     case GDB_BREAKPOINT_HW:
1336         len = 1;
1337         break;
1338     case GDB_WATCHPOINT_WRITE:
1339     case GDB_WATCHPOINT_ACCESS:
1340         switch (len) {
1341         case 1:
1342             break;
1343         case 2:
1344         case 4:
1345         case 8:
1346             if (addr & (len - 1))
1347                 return -EINVAL;
1348             break;
1349         default:
1350             return -EINVAL;
1351         }
1352         break;
1353     default:
1354         return -ENOSYS;
1355     }
1356
1357     if (nb_hw_breakpoint == 4)
1358         return -ENOBUFS;
1359
1360     if (find_hw_breakpoint(addr, len, type) >= 0)
1361         return -EEXIST;
1362
1363     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1364     hw_breakpoint[nb_hw_breakpoint].len = len;
1365     hw_breakpoint[nb_hw_breakpoint].type = type;
1366     nb_hw_breakpoint++;
1367
1368     return 0;
1369 }
1370
1371 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1372                                   target_ulong len, int type)
1373 {
1374     int n;
1375
1376     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1377     if (n < 0)
1378         return -ENOENT;
1379
1380     nb_hw_breakpoint--;
1381     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1382
1383     return 0;
1384 }
1385
1386 void kvm_arch_remove_all_hw_breakpoints(void)
1387 {
1388     nb_hw_breakpoint = 0;
1389 }
1390
1391 static CPUWatchpoint hw_watchpoint;
1392
1393 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1394 {
1395     int handle = 0;
1396     int n;
1397
1398     if (arch_info->exception == 1) {
1399         if (arch_info->dr6 & (1 << 14)) {
1400             if (cpu_single_env->singlestep_enabled)
1401                 handle = 1;
1402         } else {
1403             for (n = 0; n < 4; n++)
1404                 if (arch_info->dr6 & (1 << n))
1405                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1406                     case 0x0:
1407                         handle = 1;
1408                         break;
1409                     case 0x1:
1410                         handle = 1;
1411                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1412                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1413                         hw_watchpoint.flags = BP_MEM_WRITE;
1414                         break;
1415                     case 0x3:
1416                         handle = 1;
1417                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1418                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1419                         hw_watchpoint.flags = BP_MEM_ACCESS;
1420                         break;
1421                     }
1422         }
1423     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1424         handle = 1;
1425
1426     if (!handle) {
1427         cpu_synchronize_state(cpu_single_env);
1428         assert(cpu_single_env->exception_injected == -1);
1429
1430         cpu_single_env->exception_injected = arch_info->exception;
1431         cpu_single_env->has_error_code = 0;
1432     }
1433
1434     return handle;
1435 }
1436
1437 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1438 {
1439     const uint8_t type_code[] = {
1440         [GDB_BREAKPOINT_HW] = 0x0,
1441         [GDB_WATCHPOINT_WRITE] = 0x1,
1442         [GDB_WATCHPOINT_ACCESS] = 0x3
1443     };
1444     const uint8_t len_code[] = {
1445         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1446     };
1447     int n;
1448
1449     if (kvm_sw_breakpoints_active(env))
1450         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1451
1452     if (nb_hw_breakpoint > 0) {
1453         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1454         dbg->arch.debugreg[7] = 0x0600;
1455         for (n = 0; n < nb_hw_breakpoint; n++) {
1456             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1457             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1458                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1459                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1460         }
1461     }
1462     /* Legal xcr0 for loading */
1463     env->xcr0 = 1;
1464 }
1465 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1466
1467 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1468 {
1469       return !(env->cr[0] & CR0_PE_MASK) ||
1470               ((env->segs[R_CS].selector  & 3) != 3);
1471 }
1472
1473 #include "qemu-kvm-x86.c"