hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "ide.h"
  29 #include "pci.h"
  30 #include "vmware_vga.h"
  31 #include "monitor.h"
  32 #include "fw_cfg.h"
  33 #include "hpet_emul.h"
  34 #include "smbios.h"
  35 #include "loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "mc146818rtc.h"
  39 #include "msix.h"
  40 #include "sysbus.h"
  41 #include "sysemu.h"
  42 #include "device-assignment.h"
  43 #include "kvm.h"
  44 #include "blockdev.h"
  45
  46 /* output Bochs bios info messages */
  47 //#define DEBUG_BIOS
  48
  49 /* debug PC/ISA interrupts */
  50 //#define DEBUG_IRQ
  51
  52 #ifdef DEBUG_IRQ
  53 #define DPRINTF(fmt, ...)                                       \
  54     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  55 #else
  56 #define DPRINTF(fmt, ...)
  57 #endif
  58
  59 #define BIOS_FILENAME "bios.bin"
  60 #define EXTBOOT_FILENAME "extboot.bin"
  61 #define VAPIC_FILENAME "vapic.bin"
  62
  63 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  64
  65 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  66 #define ACPI_DATA_SIZE       0x10000
  67 #define BIOS_CFG_IOPORT 0x510
  68 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  69 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  70 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  71 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  72 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  73
  74 #define MSI_ADDR_BASE 0xfee00000
  75
  76 #define E820_NR_ENTRIES         16
  77
  78 struct e820_entry {
  79     uint64_t address;
  80     uint64_t length;
  81     uint32_t type;
  82 } __attribute((__packed__, __aligned__(4)));
  83
  84 struct e820_table {
  85     uint32_t count;
  86     struct e820_entry entry[E820_NR_ENTRIES];
  87 } __attribute((__packed__, __aligned__(4)));
  88
  89 static struct e820_table e820_table;
  90
  91 void isa_irq_handler(void *opaque, int n, int level)
  92 {
  93     IsaIrqState *isa = (IsaIrqState *)opaque;
  94
  95     DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n);
  96     if (n < 16) {
  97         qemu_set_irq(isa->i8259[n], level);
  98     }
  99     if (isa->ioapic)
 100         qemu_set_irq(isa->ioapic[n], level);
 101 };
 102
 103 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 104 {
 105 }
 106
 107 /* MSDOS compatibility mode FPU exception support */
 108 static qemu_irq ferr_irq;
 109
 110 void pc_register_ferr_irq(qemu_irq irq)
 111 {
 112     ferr_irq = irq;
 113 }
 114
 115 /* XXX: add IGNNE support */
 116 void cpu_set_ferr(CPUX86State *s)
 117 {
 118     qemu_irq_raise(ferr_irq);
 119 }
 120
 121 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 122 {
 123     qemu_irq_lower(ferr_irq);
 124 }
 125
 126 /* TSC handling */
 127 uint64_t cpu_get_tsc(CPUX86State *env)
 128 {
 129     return cpu_get_ticks();
 130 }
 131
 132 /* SMM support */
 133
 134 static cpu_set_smm_t smm_set;
 135 static void *smm_arg;
 136
 137 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 138 {
 139     assert(smm_set == NULL);
 140     assert(smm_arg == NULL);
 141     smm_set = callback;
 142     smm_arg = arg;
 143 }
 144
 145 void cpu_smm_update(CPUState *env)
 146 {
 147     if (smm_set && smm_arg && env == first_cpu)
 148         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 149 }
 150
 151
 152 /* IRQ handling */
 153 int cpu_get_pic_interrupt(CPUState *env)
 154 {
 155     int intno;
 156
 157     intno = apic_get_interrupt(env->apic_state);
 158     if (intno >= 0) {
 159         /* set irq request if a PIC irq is still pending */
 160         /* XXX: improve that */
 161         pic_update_irq(isa_pic);
 162         return intno;
 163     }
 164     /* read the irq from the PIC */
 165     if (!apic_accept_pic_intr(env->apic_state)) {
 166         return -1;
 167     }
 168
 169     intno = pic_read_irq(isa_pic);
 170     return intno;
 171 }
 172
 173 static void pic_irq_request(void *opaque, int irq, int level)
 174 {
 175     CPUState *env = first_cpu;
 176
 177     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 178     if (env->apic_state) {
 179         while (env) {
 180             if (apic_accept_pic_intr(env->apic_state)) {
 181                 apic_deliver_pic_intr(env->apic_state, level);
 182             }
 183             env = env->next_cpu;
 184         }
 185     } else {
 186         if (level)
 187             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 188         else
 189             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 190     }
 191 }
 192
 193 /* PC cmos mappings */
 194
 195 #define REG_EQUIPMENT_BYTE          0x14
 196
 197 static int cmos_get_fd_drive_type(int fd0)
 198 {
 199     int val;
 200
 201     switch (fd0) {
 202     case 0:
 203         /* 1.44 Mb 3"5 drive */
 204         val = 4;
 205         break;
 206     case 1:
 207         /* 2.88 Mb 3"5 drive */
 208         val = 5;
 209         break;
 210     case 2:
 211         /* 1.2 Mb 5"5 drive */
 212         val = 2;
 213         break;
 214     default:
 215         val = 0;
 216         break;
 217     }
 218     return val;
 219 }
 220
 221 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 222                          ISADevice *s)
 223 {
 224     int cylinders, heads, sectors;
 225     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 226     rtc_set_memory(s, type_ofs, 47);
 227     rtc_set_memory(s, info_ofs, cylinders);
 228     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 229     rtc_set_memory(s, info_ofs + 2, heads);
 230     rtc_set_memory(s, info_ofs + 3, 0xff);
 231     rtc_set_memory(s, info_ofs + 4, 0xff);
 232     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 233     rtc_set_memory(s, info_ofs + 6, cylinders);
 234     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 235     rtc_set_memory(s, info_ofs + 8, sectors);
 236 }
 237
 238 /* convert boot_device letter to something recognizable by the bios */
 239 static int boot_device2nibble(char boot_device)
 240 {
 241     switch(boot_device) {
 242     case 'a':
 243     case 'b':
 244         return 0x01; /* floppy boot */
 245     case 'c':
 246         return 0x02; /* hard drive boot */
 247     case 'd':
 248         return 0x03; /* CD-ROM boot */
 249     case 'n':
 250         return 0x04; /* Network boot */
 251     }
 252     return 0;
 253 }
 254
 255 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 256 {
 257 #define PC_MAX_BOOT_DEVICES 3
 258     int nbds, bds[3] = { 0, };
 259     int i;
 260
 261     nbds = strlen(boot_device);
 262     if (nbds > PC_MAX_BOOT_DEVICES) {
 263         error_report("Too many boot devices for PC");
 264         return(1);
 265     }
 266     for (i = 0; i < nbds; i++) {
 267         bds[i] = boot_device2nibble(boot_device[i]);
 268         if (bds[i] == 0) {
 269             error_report("Invalid boot device for PC: '%c'",
 270                          boot_device[i]);
 271             return(1);
 272         }
 273     }
 274     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 275     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 276     return(0);
 277 }
 278
 279 static int pc_boot_set(void *opaque, const char *boot_device)
 280 {
 281     return set_boot_dev(opaque, boot_device, 0);
 282 }
 283
 284 typedef struct pc_cmos_init_late_arg {
 285     ISADevice *rtc_state;
 286     BusState *idebus0, *idebus1;
 287 } pc_cmos_init_late_arg;
 288
 289 static void pc_cmos_init_late(void *opaque)
 290 {
 291     pc_cmos_init_late_arg *arg = opaque;
 292     ISADevice *s = arg->rtc_state;
 293     int val;
 294     BlockDriverState *hd_table[4];
 295     int i;
 296
 297     ide_get_bs(hd_table, arg->idebus0);
 298     ide_get_bs(hd_table + 2, arg->idebus1);
 299
 300     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 301     if (hd_table[0])
 302         cmos_init_hd(0x19, 0x1b, hd_table[0], s);
 303     if (hd_table[1])
 304         cmos_init_hd(0x1a, 0x24, hd_table[1], s);
 305
 306     val = 0;
 307     for (i = 0; i < 4; i++) {
 308         if (hd_table[i]) {
 309             int cylinders, heads, sectors, translation;
 310             /* NOTE: bdrv_get_geometry_hint() returns the physical
 311                 geometry.  It is always such that: 1 <= sects <= 63, 1
 312                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 313                 geometry can be different if a translation is done. */
 314             translation = bdrv_get_translation_hint(hd_table[i]);
 315             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 316                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 317                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 318                     /* No translation. */
 319                     translation = 0;
 320                 } else {
 321                     /* LBA translation. */
 322                     translation = 1;
 323                 }
 324             } else {
 325                 translation--;
 326             }
 327             val |= translation << (i * 2);
 328         }
 329     }
 330     rtc_set_memory(s, 0x39, val);
 331
 332     qemu_unregister_reset(pc_cmos_init_late, opaque);
 333 }
 334
 335 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 336                   const char *boot_device,
 337                   BusState *idebus0, BusState *idebus1,
 338                   FDCtrl *floppy_controller, ISADevice *s)
 339 {
 340     int val;
 341     int fd0, fd1, nb;
 342     static pc_cmos_init_late_arg arg;
 343
 344     /* various important CMOS locations needed by PC/Bochs bios */
 345
 346     /* memory size */
 347     val = 640; /* base memory in K */
 348     rtc_set_memory(s, 0x15, val);
 349     rtc_set_memory(s, 0x16, val >> 8);
 350
 351     val = (ram_size / 1024) - 1024;
 352     if (val > 65535)
 353         val = 65535;
 354     rtc_set_memory(s, 0x17, val);
 355     rtc_set_memory(s, 0x18, val >> 8);
 356     rtc_set_memory(s, 0x30, val);
 357     rtc_set_memory(s, 0x31, val >> 8);
 358
 359     if (above_4g_mem_size) {
 360         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 361         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 362         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 363     }
 364
 365     if (ram_size > (16 * 1024 * 1024))
 366         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 367     else
 368         val = 0;
 369     if (val > 65535)
 370         val = 65535;
 371     rtc_set_memory(s, 0x34, val);
 372     rtc_set_memory(s, 0x35, val >> 8);
 373
 374     /* set the number of CPU */
 375     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 376
 377     /* set boot devices, and disable floppy signature check if requested */
 378     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 379         exit(1);
 380     }
 381
 382     /* floppy type */
 383
 384     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 385     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 386
 387     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 388     rtc_set_memory(s, 0x10, val);
 389
 390     val = 0;
 391     nb = 0;
 392     if (fd0 < 3)
 393         nb++;
 394     if (fd1 < 3)
 395         nb++;
 396     switch (nb) {
 397     case 0:
 398         break;
 399     case 1:
 400         val |= 0x01; /* 1 drive, ready for boot */
 401         break;
 402     case 2:
 403         val |= 0x41; /* 2 drives, ready for boot */
 404         break;
 405     }
 406     val |= 0x02; /* FPU is there */
 407     val |= 0x04; /* PS/2 mouse installed */
 408     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 409
 410     /* hard drives */
 411     arg.rtc_state = s;
 412     arg.idebus0 = idebus0;
 413     arg.idebus1 = idebus1;
 414     qemu_register_reset(pc_cmos_init_late, &arg);
 415 }
 416
 417 static void handle_a20_line_change(void *opaque, int irq, int level)
 418 {
 419     CPUState *cpu = opaque;
 420
 421     /* XXX: send to all CPUs ? */
 422     cpu_x86_set_a20(cpu, level);
 423 }
 424
 425 /***********************************************************/
 426 /* Bochs BIOS debug ports */
 427
 428 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 429 {
 430     static const char shutdown_str[8] = "Shutdown";
 431     static int shutdown_index = 0;
 432
 433     switch(addr) {
 434         /* Bochs BIOS messages */
 435     case 0x400:
 436     case 0x401:
 437         /* used to be panic, now unused */
 438         break;
 439     case 0x402:
 440     case 0x403:
 441 #ifdef DEBUG_BIOS
 442         fprintf(stderr, "%c", val);
 443 #endif
 444         break;
 445     case 0x8900:
 446         /* same as Bochs power off */
 447         if (val == shutdown_str[shutdown_index]) {
 448             shutdown_index++;
 449             if (shutdown_index == 8) {
 450                 shutdown_index = 0;
 451                 qemu_system_shutdown_request();
 452             }
 453         } else {
 454             shutdown_index = 0;
 455         }
 456         break;
 457
 458         /* LGPL'ed VGA BIOS messages */
 459     case 0x501:
 460     case 0x502:
 461         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 462         exit(1);
 463     case 0x500:
 464     case 0x503:
 465 #ifdef DEBUG_BIOS
 466         fprintf(stderr, "%c", val);
 467 #endif
 468         break;
 469     }
 470 }
 471
 472 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 473 {
 474     int index = le32_to_cpu(e820_table.count);
 475     struct e820_entry *entry;
 476
 477     if (index >= E820_NR_ENTRIES)
 478         return -EBUSY;
 479     entry = &e820_table.entry[index++];
 480
 481     entry->address = cpu_to_le64(address);
 482     entry->length = cpu_to_le64(length);
 483     entry->type = cpu_to_le32(type);
 484
 485     e820_table.count = cpu_to_le32(index);
 486     return index;
 487 }
 488
 489 static void *bochs_bios_init(void)
 490 {
 491     void *fw_cfg;
 492     uint8_t *smbios_table;
 493     size_t smbios_len;
 494     uint64_t *numa_fw_cfg;
 495     int i, j;
 496
 497     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 498     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 499     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 500     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 501     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 502
 503     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 504     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 505     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 506     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 507
 508     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 509
 510     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 511     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 512     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 513                      acpi_tables_len);
 514     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 515
 516     smbios_table = smbios_get_table(&smbios_len);
 517     if (smbios_table)
 518         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 519                          smbios_table, smbios_len);
 520     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 521                      sizeof(struct e820_table));
 522
 523     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 524                      sizeof(struct hpet_fw_config));
 525     /* allocate memory for the NUMA channel: one (64bit) word for the number
 526      * of nodes, one word for each VCPU->node and one word for each node to
 527      * hold the amount of memory.
 528      */
 529     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 530     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 531     for (i = 0; i < smp_cpus; i++) {
 532         for (j = 0; j < nb_numa_nodes; j++) {
 533             if (node_cpumask[j] & (1 << i)) {
 534                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 535                 break;
 536             }
 537         }
 538     }
 539     for (i = 0; i < nb_numa_nodes; i++) {
 540         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 541     }
 542     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 543                      (1 + smp_cpus + nb_numa_nodes) * 8);
 544
 545     return fw_cfg;
 546 }
 547
 548 static long get_file_size(FILE *f)
 549 {
 550     long where, size;
 551
 552     /* XXX: on Unix systems, using fstat() probably makes more sense */
 553
 554     where = ftell(f);
 555     fseek(f, 0, SEEK_END);
 556     size = ftell(f);
 557     fseek(f, where, SEEK_SET);
 558
 559     return size;
 560 }
 561
 562 static void load_linux(void *fw_cfg,
 563                        const char *kernel_filename,
 564                        const char *initrd_filename,
 565                        const char *kernel_cmdline,
 566                        target_phys_addr_t max_ram_size)
 567 {
 568     uint16_t protocol;
 569     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 570     uint32_t initrd_max;
 571     uint8_t header[8192], *setup, *kernel, *initrd_data;
 572     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 573     FILE *f;
 574     char *vmode;
 575
 576     /* Align to 16 bytes as a paranoia measure */
 577     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 578
 579     /* load the kernel header */
 580     f = fopen(kernel_filename, "rb");
 581     if (!f || !(kernel_size = get_file_size(f)) ||
 582         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 583         MIN(ARRAY_SIZE(header), kernel_size)) {
 584         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 585                 kernel_filename, strerror(errno));
 586         exit(1);
 587     }
 588
 589     /* kernel protocol version */
 590 #if 0
 591     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 592 #endif
 593     if (ldl_p(header+0x202) == 0x53726448)
 594         protocol = lduw_p(header+0x206);
 595     else {
 596         /* This looks like a multiboot kernel. If it is, let's stop
 597            treating it like a Linux kernel. */
 598         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 599                            kernel_cmdline, kernel_size, header))
 600             return;
 601         protocol = 0;
 602     }
 603
 604     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 605         /* Low kernel */
 606         real_addr    = 0x90000;
 607         cmdline_addr = 0x9a000 - cmdline_size;
 608         prot_addr    = 0x10000;
 609     } else if (protocol < 0x202) {
 610         /* High but ancient kernel */
 611         real_addr    = 0x90000;
 612         cmdline_addr = 0x9a000 - cmdline_size;
 613         prot_addr    = 0x100000;
 614     } else {
 615         /* High and recent kernel */
 616         real_addr    = 0x10000;
 617         cmdline_addr = 0x20000;
 618         prot_addr    = 0x100000;
 619     }
 620
 621 #if 0
 622     fprintf(stderr,
 623             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 624             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 625             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 626             real_addr,
 627             cmdline_addr,
 628             prot_addr);
 629 #endif
 630
 631     /* highest address for loading the initrd */
 632     if (protocol >= 0x203)
 633         initrd_max = ldl_p(header+0x22c);
 634     else
 635         initrd_max = 0x37ffffff;
 636
 637     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 638         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 639
 640     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 641     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 642     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 643                      (uint8_t*)strdup(kernel_cmdline),
 644                      strlen(kernel_cmdline)+1);
 645
 646     if (protocol >= 0x202) {
 647         stl_p(header+0x228, cmdline_addr);
 648     } else {
 649         stw_p(header+0x20, 0xA33F);
 650         stw_p(header+0x22, cmdline_addr-real_addr);
 651     }
 652
 653     /* handle vga= parameter */
 654     vmode = strstr(kernel_cmdline, "vga=");
 655     if (vmode) {
 656         unsigned int video_mode;
 657         /* skip "vga=" */
 658         vmode += 4;
 659         if (!strncmp(vmode, "normal", 6)) {
 660             video_mode = 0xffff;
 661         } else if (!strncmp(vmode, "ext", 3)) {
 662             video_mode = 0xfffe;
 663         } else if (!strncmp(vmode, "ask", 3)) {
 664             video_mode = 0xfffd;
 665         } else {
 666             video_mode = strtol(vmode, NULL, 0);
 667         }
 668         stw_p(header+0x1fa, video_mode);
 669     }
 670
 671     /* loader type */
 672     /* High nybble = B reserved for Qemu; low nybble is revision number.
 673        If this code is substantially changed, you may want to consider
 674        incrementing the revision. */
 675     if (protocol >= 0x200)
 676         header[0x210] = 0xB0;
 677
 678     /* heap */
 679     if (protocol >= 0x201) {
 680         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 681         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 682     }
 683
 684     /* load initrd */
 685     if (initrd_filename) {
 686         if (protocol < 0x200) {
 687             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 688             exit(1);
 689         }
 690
 691         initrd_size = get_image_size(initrd_filename);
 692         if (initrd_size < 0) {
 693             fprintf(stderr, "qemu: error reading initrd %s\n",
 694                     initrd_filename);
 695             exit(1);
 696         }
 697
 698         initrd_addr = (initrd_max-initrd_size) & ~4095;
 699
 700         initrd_data = qemu_malloc(initrd_size);
 701         load_image(initrd_filename, initrd_data);
 702
 703         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 704         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 705         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 706
 707         stl_p(header+0x218, initrd_addr);
 708         stl_p(header+0x21c, initrd_size);
 709     }
 710
 711     /* load kernel and setup */
 712     setup_size = header[0x1f1];
 713     if (setup_size == 0)
 714         setup_size = 4;
 715     setup_size = (setup_size+1)*512;
 716     kernel_size -= setup_size;
 717
 718     setup  = qemu_malloc(setup_size);
 719     kernel = qemu_malloc(kernel_size);
 720     fseek(f, 0, SEEK_SET);
 721     if (fread(setup, 1, setup_size, f) != setup_size) {
 722         fprintf(stderr, "fread() failed\n");
 723         exit(1);
 724     }
 725     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 726         fprintf(stderr, "fread() failed\n");
 727         exit(1);
 728     }
 729     fclose(f);
 730     memcpy(setup, header, MIN(sizeof(header), setup_size));
 731
 732     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 733     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 734     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 735
 736     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 737     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 738     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 739
 740     option_rom[nb_option_roms] = "linuxboot.bin";
 741     nb_option_roms++;
 742 }
 743
 744 #define NE2000_NB_MAX 6
 745
 746 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 747                                               0x280, 0x380 };
 748 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 749
 750 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 751 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 752
 753 void pc_audio_init (PCIBus *pci_bus, qemu_irq *pic)
 754 {
 755     struct soundhw *c;
 756
 757     for (c = soundhw; c->name; ++c) {
 758         if (c->enabled) {
 759             if (c->isa) {
 760                 c->init.init_isa(pic);
 761             } else {
 762                 if (pci_bus) {
 763                     c->init.init_pci(pci_bus);
 764                 }
 765             }
 766         }
 767     }
 768 }
 769
 770 void pc_init_ne2k_isa(NICInfo *nd)
 771 {
 772     static int nb_ne2k = 0;
 773
 774     if (nb_ne2k == NE2000_NB_MAX)
 775         return;
 776     isa_ne2000_init(ne2000_io[nb_ne2k],
 777                     ne2000_irq[nb_ne2k], nd);
 778     nb_ne2k++;
 779 }
 780
 781 int cpu_is_bsp(CPUState *env)
 782 {
 783     /* We hard-wire the BSP to the first CPU. */
 784     return env->cpu_index == 0;
 785 }
 786
 787 DeviceState *cpu_get_current_apic(void)
 788 {
 789     if (cpu_single_env) {
 790         return cpu_single_env->apic_state;
 791     } else {
 792         return NULL;
 793     }
 794 }
 795
 796 static DeviceState *apic_init(void *env, uint8_t apic_id)
 797 {
 798     DeviceState *dev;
 799     SysBusDevice *d;
 800     static int apic_mapped;
 801
 802     dev = qdev_create(NULL, "apic");
 803     qdev_prop_set_uint8(dev, "id", apic_id);
 804     qdev_prop_set_ptr(dev, "cpu_env", env);
 805     qdev_init_nofail(dev);
 806     d = sysbus_from_qdev(dev);
 807
 808     /* XXX: mapping more APICs at the same memory location */
 809     if (apic_mapped == 0) {
 810         /* NOTE: the APIC is directly connected to the CPU - it is not
 811            on the global memory bus. */
 812         /* XXX: what if the base changes? */
 813         sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
 814         apic_mapped = 1;
 815     }
 816
 817     msix_supported = 1;
 818
 819     return dev;
 820 }
 821
 822 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 823    BIOS will read it and start S3 resume at POST Entry */
 824 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
 825 {
 826     ISADevice *s = opaque;
 827
 828     if (level) {
 829         rtc_set_memory(s, 0xF, 0xFE);
 830     }
 831 }
 832
 833 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 834 {
 835     CPUState *s = opaque;
 836
 837     if (level) {
 838         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 839     }
 840 }
 841
 842 static void pc_cpu_reset(void *opaque)
 843 {
 844     CPUState *env = opaque;
 845
 846     cpu_reset(env);
 847     env->halted = !cpu_is_bsp(env);
 848 }
 849
 850 CPUState *pc_new_cpu(const char *cpu_model)
 851 {
 852     CPUState *env;
 853
 854     if (cpu_model == NULL) {
 855 #ifdef TARGET_X86_64
 856         cpu_model = "qemu64";
 857 #else
 858         cpu_model = "qemu32";
 859 #endif
 860     }
 861
 862     env = cpu_init(cpu_model);
 863     if (!env) {
 864         fprintf(stderr, "Unable to find x86 CPU definition\n");
 865         exit(1);
 866     }
 867     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 868         env->cpuid_apic_id = env->cpu_index;
 869         env->apic_state = apic_init(env, env->cpuid_apic_id);
 870     }
 871     qemu_register_reset(pc_cpu_reset, env);
 872     pc_cpu_reset(env);
 873     return env;
 874 }
 875
 876 void pc_cpus_init(const char *cpu_model)
 877 {
 878     int i;
 879
 880     /* init CPUs */
 881     for(i = 0; i < smp_cpus; i++) {
 882         pc_new_cpu(cpu_model);
 883     }
 884 }
 885
 886 void pc_memory_init(ram_addr_t ram_size,
 887                     const char *kernel_filename,
 888                     const char *kernel_cmdline,
 889                     const char *initrd_filename,
 890                     ram_addr_t *below_4g_mem_size_p,
 891                     ram_addr_t *above_4g_mem_size_p)
 892 {
 893     char *filename;
 894     int ret, linux_boot, i;
 895     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 896     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 897     int bios_size, isa_bios_size;
 898     void *fw_cfg;
 899
 900     if (ram_size >= 0xe0000000 ) {
 901         above_4g_mem_size = ram_size - 0xe0000000;
 902         below_4g_mem_size = 0xe0000000;
 903     } else {
 904         below_4g_mem_size = ram_size;
 905     }
 906     *above_4g_mem_size_p = above_4g_mem_size;
 907     *below_4g_mem_size_p = below_4g_mem_size;
 908
 909 #if TARGET_PHYS_ADDR_BITS == 32
 910     if (above_4g_mem_size > 0) {
 911         hw_error("To much RAM for 32-bit physical address");
 912     }
 913 #endif
 914     linux_boot = (kernel_filename != NULL);
 915
 916     /* allocate RAM */
 917     ram_addr = qemu_ram_alloc(NULL, "pc.ram",
 918                               below_4g_mem_size + above_4g_mem_size);
 919     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 920     cpu_register_physical_memory(0x100000,
 921                  below_4g_mem_size - 0x100000,
 922                  ram_addr + 0x100000);
 923 #if TARGET_PHYS_ADDR_BITS > 32
 924     if (above_4g_mem_size > 0) {
 925         cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size,
 926                                      ram_addr + below_4g_mem_size);
 927     }
 928 #endif
 929
 930     /* BIOS load */
 931     if (bios_name == NULL)
 932         bios_name = BIOS_FILENAME;
 933     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 934     if (filename) {
 935         bios_size = get_image_size(filename);
 936     } else {
 937         bios_size = -1;
 938     }
 939     if (bios_size <= 0 ||
 940         (bios_size % 65536) != 0) {
 941         goto bios_error;
 942     }
 943     bios_offset = qemu_ram_alloc(NULL, "pc.bios", bios_size);
 944     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
 945     if (ret != 0) {
 946     bios_error:
 947         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 948         exit(1);
 949     }
 950     if (filename) {
 951         qemu_free(filename);
 952     }
 953     /* map the last 128KB of the BIOS in ISA space */
 954     isa_bios_size = bios_size;
 955     if (isa_bios_size > (128 * 1024))
 956         isa_bios_size = 128 * 1024;
 957     cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size,
 958                                  IO_MEM_UNASSIGNED);
 959     cpu_register_physical_memory(0x100000 - isa_bios_size,
 960                                  isa_bios_size,
 961                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 962
 963     if (extboot_drive) {
 964         option_rom[nb_option_roms++] = qemu_strdup(EXTBOOT_FILENAME);
 965     }
 966     option_rom[nb_option_roms++] = qemu_strdup(VAPIC_FILENAME);
 967
 968     option_rom_offset = qemu_ram_alloc(NULL, "pc.rom", PC_ROM_SIZE);
 969     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 970
 971     /* map all the bios at the top of memory */
 972     cpu_register_physical_memory((uint32_t)(-bios_size),
 973                                  bios_size, bios_offset | IO_MEM_ROM);
 974
 975     fw_cfg = bochs_bios_init();
 976     rom_set_fw(fw_cfg);
 977
 978     if (linux_boot) {
 979         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 980     }
 981
 982     for (i = 0; i < nb_option_roms; i++) {
 983         rom_add_option(option_rom[i]);
 984     }
 985 }
 986
 987 qemu_irq *pc_allocate_cpu_irq(void)
 988 {
 989     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 990 }
 991
 992 void pc_vga_init(PCIBus *pci_bus)
 993 {
 994     if (cirrus_vga_enabled) {
 995         if (pci_bus) {
 996             pci_cirrus_vga_init(pci_bus);
 997         } else {
 998             isa_cirrus_vga_init();
 999         }
1000     } else if (vmsvga_enabled) {
1001         if (pci_bus)
1002             pci_vmsvga_init(pci_bus);
1003         else
1004             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1005     } else if (std_vga_enabled) {
1006         if (pci_bus) {
1007             pci_vga_init(pci_bus);
1008         } else {
1009             isa_vga_init();
1010         }
1011     }
1012 }
1013
1014 static void cpu_request_exit(void *opaque, int irq, int level)
1015 {
1016     CPUState *env = cpu_single_env;
1017
1018     if (env && level) {
1019         cpu_exit(env);
1020     }
1021 }
1022
1023 void pc_basic_device_init(qemu_irq *isa_irq,
1024                           FDCtrl **floppy_controller,
1025                           ISADevice **rtc_state)
1026 {
1027     int i;
1028     DriveInfo *fd[MAX_FD];
1029     PITState *pit;
1030     qemu_irq rtc_irq = NULL;
1031     qemu_irq *a20_line;
1032     ISADevice *i8042;
1033     qemu_irq *cpu_exit_irq;
1034
1035     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1036
1037     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1038
1039     if (!no_hpet) {
1040         DeviceState *hpet = sysbus_create_simple("hpet", HPET_BASE, NULL);
1041
1042         for (i = 0; i < 24; i++) {
1043             sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]);
1044         }
1045         rtc_irq = qdev_get_gpio_in(hpet, 0);
1046     }
1047     *rtc_state = rtc_init(2000, rtc_irq);
1048
1049     qemu_register_boot_set(pc_boot_set, *rtc_state);
1050
1051 #ifdef CONFIG_KVM_PIT
1052     if (kvm_enabled() && kvm_pit_in_kernel())
1053         pit = kvm_pit_init(0x40, isa_reserve_irq(0));
1054     else
1055 #endif
1056
1057     pit = pit_init(0x40, isa_reserve_irq(0));
1058
1059     pcspk_init(pit);
1060
1061     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1062         if (serial_hds[i]) {
1063             serial_isa_init(i, serial_hds[i]);
1064         }
1065     }
1066
1067     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1068         if (parallel_hds[i]) {
1069             parallel_init(i, parallel_hds[i]);
1070         }
1071     }
1072
1073     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
1074     i8042 = isa_create_simple("i8042");
1075     i8042_setup_a20_line(i8042, a20_line);
1076     vmmouse_init(i8042);
1077
1078     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1079     DMA_init(0, cpu_exit_irq);
1080
1081     for(i = 0; i < MAX_FD; i++) {
1082         fd[i] = drive_get(IF_FLOPPY, 0, i);
1083     }
1084     *floppy_controller = fdctrl_init_isa(fd);
1085 }
1086
1087 void pc_pci_device_init(PCIBus *pci_bus)
1088 {
1089     int max_bus;
1090     int bus;
1091
1092     max_bus = drive_get_max_bus(IF_SCSI);
1093     for (bus = 0; bus <= max_bus; bus++) {
1094         pci_create_simple(pci_bus, -1, "lsi53c895a");
1095     }
1096
1097     if (extboot_drive) {
1098         DriveInfo *info = extboot_drive;
1099         int cyls, heads, secs;
1100
1101         if (info->type != IF_IDE && info->type != IF_VIRTIO) {
1102             bdrv_guess_geometry(info->bdrv, &cyls, &heads, &secs);
1103             bdrv_set_geometry_hint(info->bdrv, cyls, heads, secs);
1104         }
1105
1106         extboot_init(info->bdrv);
1107     }
1108 }