hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "apic.h"
  21 #include "qemu-timer.h"
  22 #include "host-utils.h"
  23 #include "sysbus.h"
  24 #include "trace.h"
  25 #include "kvm.h"
  26
  27 /* APIC Local Vector Table */
  28 #define APIC_LVT_TIMER   0
  29 #define APIC_LVT_THERMAL 1
  30 #define APIC_LVT_PERFORM 2
  31 #define APIC_LVT_LINT0   3
  32 #define APIC_LVT_LINT1   4
  33 #define APIC_LVT_ERROR   5
  34 #define APIC_LVT_NB      6
  35
  36 /* APIC delivery modes */
  37 #define APIC_DM_FIXED   0
  38 #define APIC_DM_LOWPRI  1
  39 #define APIC_DM_SMI     2
  40 #define APIC_DM_NMI     4
  41 #define APIC_DM_INIT    5
  42 #define APIC_DM_SIPI    6
  43 #define APIC_DM_EXTINT  7
  44
  45 /* APIC destination mode */
  46 #define APIC_DESTMODE_FLAT      0xf
  47 #define APIC_DESTMODE_CLUSTER   1
  48
  49 #define APIC_TRIGGER_EDGE  0
  50 #define APIC_TRIGGER_LEVEL 1
  51
  52 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  53 #define APIC_LVT_MASKED                 (1<<16)
  54 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  55 #define APIC_LVT_REMOTE_IRR             (1<<14)
  56 #define APIC_INPUT_POLARITY             (1<<13)
  57 #define APIC_SEND_PENDING               (1<<12)
  58
  59 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  60
  61 #define APIC_SV_ENABLE (1 << 8)
  62
  63 #define MAX_APICS 255
  64 #define MAX_APIC_WORDS 8
  65
  66 /* Intel APIC constants: from include/asm/msidef.h */
  67 #define MSI_DATA_VECTOR_SHIFT           0
  68 #define MSI_DATA_VECTOR_MASK            0x000000ff
  69 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  70 #define MSI_DATA_TRIGGER_SHIFT          15
  71 #define MSI_DATA_LEVEL_SHIFT            14
  72 #define MSI_ADDR_DEST_MODE_SHIFT        2
  73 #define MSI_ADDR_DEST_ID_SHIFT          12
  74 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  75
  76 #define MSI_ADDR_SIZE                   0x100000
  77
  78 typedef struct APICState APICState;
  79
  80 struct APICState {
  81     SysBusDevice busdev;
  82     void *cpu_env;
  83     uint32_t apicbase;
  84     uint8_t id;
  85     uint8_t arb_id;
  86     uint8_t tpr;
  87     uint32_t spurious_vec;
  88     uint8_t log_dest;
  89     uint8_t dest_mode;
  90     uint32_t isr[8];  /* in service register */
  91     uint32_t tmr[8];  /* trigger mode register */
  92     uint32_t irr[8]; /* interrupt request register */
  93     uint32_t lvt[APIC_LVT_NB];
  94     uint32_t esr; /* error register */
  95     uint32_t icr[2];
  96
  97     uint32_t divide_conf;
  98     int count_shift;
  99     uint32_t initial_count;
 100     int64_t initial_count_load_time, next_time;
 101     uint32_t idx;
 102     QEMUTimer *timer;
 103     int sipi_vector;
 104     int wait_for_sipi;
 105 };
 106
 107 static APICState *local_apics[MAX_APICS + 1];
 108 static int apic_irq_delivered;
 109
 110 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 111 static void apic_update_irq(APICState *s);
 112 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 113                                       uint8_t dest, uint8_t dest_mode);
 114
 115 /* Find first bit starting from msb */
 116 static int fls_bit(uint32_t value)
 117 {
 118     return 31 - clz32(value);
 119 }
 120
 121 /* Find first bit starting from lsb */
 122 static int ffs_bit(uint32_t value)
 123 {
 124     return ctz32(value);
 125 }
 126
 127 static inline void set_bit(uint32_t *tab, int index)
 128 {
 129     int i, mask;
 130     i = index >> 5;
 131     mask = 1 << (index & 0x1f);
 132     tab[i] |= mask;
 133 }
 134
 135 static inline void reset_bit(uint32_t *tab, int index)
 136 {
 137     int i, mask;
 138     i = index >> 5;
 139     mask = 1 << (index & 0x1f);
 140     tab[i] &= ~mask;
 141 }
 142
 143 static inline int get_bit(uint32_t *tab, int index)
 144 {
 145     int i, mask;
 146     i = index >> 5;
 147     mask = 1 << (index & 0x1f);
 148     return !!(tab[i] & mask);
 149 }
 150
 151 static void apic_local_deliver(APICState *s, int vector)
 152 {
 153     uint32_t lvt = s->lvt[vector];
 154     int trigger_mode;
 155
 156     trace_apic_local_deliver(vector, (lvt >> 8) & 7);
 157
 158     if (lvt & APIC_LVT_MASKED)
 159         return;
 160
 161     switch ((lvt >> 8) & 7) {
 162     case APIC_DM_SMI:
 163         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
 164         break;
 165
 166     case APIC_DM_NMI:
 167         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
 168         break;
 169
 170     case APIC_DM_EXTINT:
 171         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 172         break;
 173
 174     case APIC_DM_FIXED:
 175         trigger_mode = APIC_TRIGGER_EDGE;
 176         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 177             (lvt & APIC_LVT_LEVEL_TRIGGER))
 178             trigger_mode = APIC_TRIGGER_LEVEL;
 179         apic_set_irq(s, lvt & 0xff, trigger_mode);
 180     }
 181 }
 182
 183 void apic_deliver_pic_intr(DeviceState *d, int level)
 184 {
 185     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 186
 187     if (level) {
 188         apic_local_deliver(s, APIC_LVT_LINT0);
 189     } else {
 190         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 191
 192         switch ((lvt >> 8) & 7) {
 193         case APIC_DM_FIXED:
 194             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 195                 break;
 196             reset_bit(s->irr, lvt & 0xff);
 197             /* fall through */
 198         case APIC_DM_EXTINT:
 199             cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 200             break;
 201         }
 202     }
 203 }
 204
 205 #define foreach_apic(apic, deliver_bitmask, code) \
 206 {\
 207     int __i, __j, __mask;\
 208     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 209         __mask = deliver_bitmask[__i];\
 210         if (__mask) {\
 211             for(__j = 0; __j < 32; __j++) {\
 212                 if (__mask & (1 << __j)) {\
 213                     apic = local_apics[__i * 32 + __j];\
 214                     if (apic) {\
 215                         code;\
 216                     }\
 217                 }\
 218             }\
 219         }\
 220     }\
 221 }
 222
 223 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 224                              uint8_t delivery_mode,
 225                              uint8_t vector_num, uint8_t polarity,
 226                              uint8_t trigger_mode)
 227 {
 228     APICState *apic_iter;
 229
 230     switch (delivery_mode) {
 231         case APIC_DM_LOWPRI:
 232             /* XXX: search for focus processor, arbitration */
 233             {
 234                 int i, d;
 235                 d = -1;
 236                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 237                     if (deliver_bitmask[i]) {
 238                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 239                         break;
 240                     }
 241                 }
 242                 if (d >= 0) {
 243                     apic_iter = local_apics[d];
 244                     if (apic_iter) {
 245                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 246                     }
 247                 }
 248             }
 249             return;
 250
 251         case APIC_DM_FIXED:
 252             break;
 253
 254         case APIC_DM_SMI:
 255             foreach_apic(apic_iter, deliver_bitmask,
 256                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 257             return;
 258
 259         case APIC_DM_NMI:
 260             foreach_apic(apic_iter, deliver_bitmask,
 261                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 262             return;
 263
 264         case APIC_DM_INIT:
 265             /* normal INIT IPI sent to processors */
 266             foreach_apic(apic_iter, deliver_bitmask,
 267                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 268             return;
 269
 270         case APIC_DM_EXTINT:
 271             /* handled in I/O APIC code */
 272             break;
 273
 274         default:
 275             return;
 276     }
 277
 278     foreach_apic(apic_iter, deliver_bitmask,
 279                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 280 }
 281
 282 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 283                       uint8_t delivery_mode, uint8_t vector_num,
 284                       uint8_t polarity, uint8_t trigger_mode)
 285 {
 286     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 287
 288     trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
 289                            polarity, trigger_mode);
 290
 291     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 292     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 293                      trigger_mode);
 294 }
 295
 296 void cpu_set_apic_base(DeviceState *d, uint64_t val)
 297 {
 298     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 299
 300     trace_cpu_set_apic_base(val);
 301
 302     if (!s)
 303         return;
 304     if (kvm_enabled() && kvm_irqchip_in_kernel())
 305         s->apicbase = val;
 306     else
 307         s->apicbase = (val & 0xfffff000) |
 308             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 309     /* if disabled, cannot be enabled again */
 310     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 311         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 312         cpu_clear_apic_feature(s->cpu_env);
 313         s->spurious_vec &= ~APIC_SV_ENABLE;
 314     }
 315 }
 316
 317 uint64_t cpu_get_apic_base(DeviceState *d)
 318 {
 319     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 320
 321     trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
 322
 323     return s ? s->apicbase : 0;
 324 }
 325
 326 void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
 327 {
 328     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 329
 330     if (!s)
 331         return;
 332     s->tpr = (val & 0x0f) << 4;
 333     apic_update_irq(s);
 334 }
 335
 336 uint8_t cpu_get_apic_tpr(DeviceState *d)
 337 {
 338     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 339
 340     return s ? s->tpr >> 4 : 0;
 341 }
 342
 343 /* return -1 if no bit is set */
 344 static int get_highest_priority_int(uint32_t *tab)
 345 {
 346     int i;
 347     for(i = 7; i >= 0; i--) {
 348         if (tab[i] != 0) {
 349             return i * 32 + fls_bit(tab[i]);
 350         }
 351     }
 352     return -1;
 353 }
 354
 355 static int apic_get_ppr(APICState *s)
 356 {
 357     int tpr, isrv, ppr;
 358
 359     tpr = (s->tpr >> 4);
 360     isrv = get_highest_priority_int(s->isr);
 361     if (isrv < 0)
 362         isrv = 0;
 363     isrv >>= 4;
 364     if (tpr >= isrv)
 365         ppr = s->tpr;
 366     else
 367         ppr = isrv << 4;
 368     return ppr;
 369 }
 370
 371 static int apic_get_arb_pri(APICState *s)
 372 {
 373     /* XXX: arbitration */
 374     return 0;
 375 }
 376
 377 /* signal the CPU if an irq is pending */
 378 static void apic_update_irq(APICState *s)
 379 {
 380     int irrv, ppr;
 381     if (!(s->spurious_vec & APIC_SV_ENABLE))
 382         return;
 383     irrv = get_highest_priority_int(s->irr);
 384     if (irrv < 0)
 385         return;
 386     ppr = apic_get_ppr(s);
 387     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 388         return;
 389     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 390 }
 391
 392 void apic_reset_irq_delivered(void)
 393 {
 394     trace_apic_reset_irq_delivered(apic_irq_delivered);
 395
 396     apic_irq_delivered = 0;
 397 }
 398
 399 int apic_get_irq_delivered(void)
 400 {
 401     trace_apic_get_irq_delivered(apic_irq_delivered);
 402
 403     return apic_irq_delivered;
 404 }
 405
 406 void apic_set_irq_delivered(void)
 407 {
 408     apic_irq_delivered = 1;
 409 }
 410
 411 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 412 {
 413     apic_irq_delivered += !get_bit(s->irr, vector_num);
 414
 415     trace_apic_set_irq(apic_irq_delivered);
 416
 417     set_bit(s->irr, vector_num);
 418     if (trigger_mode)
 419         set_bit(s->tmr, vector_num);
 420     else
 421         reset_bit(s->tmr, vector_num);
 422     apic_update_irq(s);
 423 }
 424
 425 static void apic_eoi(APICState *s)
 426 {
 427     int isrv;
 428     isrv = get_highest_priority_int(s->isr);
 429     if (isrv < 0)
 430         return;
 431     reset_bit(s->isr, isrv);
 432     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 433             set the remote IRR bit for level triggered interrupts. */
 434     apic_update_irq(s);
 435 }
 436
 437 static int apic_find_dest(uint8_t dest)
 438 {
 439     APICState *apic = local_apics[dest];
 440     int i;
 441
 442     if (apic && apic->id == dest)
 443         return dest;  /* shortcut in case apic->id == apic->idx */
 444
 445     for (i = 0; i < MAX_APICS; i++) {
 446         apic = local_apics[i];
 447         if (apic && apic->id == dest)
 448             return i;
 449         if (!apic)
 450             break;
 451     }
 452
 453     return -1;
 454 }
 455
 456 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 457                                       uint8_t dest, uint8_t dest_mode)
 458 {
 459     APICState *apic_iter;
 460     int i;
 461
 462     if (dest_mode == 0) {
 463         if (dest == 0xff) {
 464             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 465         } else {
 466             int idx = apic_find_dest(dest);
 467             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 468             if (idx >= 0)
 469                 set_bit(deliver_bitmask, idx);
 470         }
 471     } else {
 472         /* XXX: cluster mode */
 473         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 474         for(i = 0; i < MAX_APICS; i++) {
 475             apic_iter = local_apics[i];
 476             if (apic_iter) {
 477                 if (apic_iter->dest_mode == 0xf) {
 478                     if (dest & apic_iter->log_dest)
 479                         set_bit(deliver_bitmask, i);
 480                 } else if (apic_iter->dest_mode == 0x0) {
 481                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 482                         (dest & apic_iter->log_dest & 0x0f)) {
 483                         set_bit(deliver_bitmask, i);
 484                     }
 485                 }
 486             } else {
 487                 break;
 488             }
 489         }
 490     }
 491 }
 492
 493 void apic_init_reset(DeviceState *d)
 494 {
 495     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 496     int i;
 497
 498     if (!s)
 499         return;
 500
 501     s->tpr = 0;
 502     s->spurious_vec = 0xff;
 503     s->log_dest = 0;
 504     s->dest_mode = 0xf;
 505     memset(s->isr, 0, sizeof(s->isr));
 506     memset(s->tmr, 0, sizeof(s->tmr));
 507     memset(s->irr, 0, sizeof(s->irr));
 508     for(i = 0; i < APIC_LVT_NB; i++)
 509         s->lvt[i] = 1 << 16; /* mask LVT */
 510     s->esr = 0;
 511     memset(s->icr, 0, sizeof(s->icr));
 512     s->divide_conf = 0;
 513     s->count_shift = 0;
 514     s->initial_count = 0;
 515     s->initial_count_load_time = 0;
 516     s->next_time = 0;
 517     s->wait_for_sipi = 1;
 518 }
 519
 520 static void apic_startup(APICState *s, int vector_num)
 521 {
 522     s->sipi_vector = vector_num;
 523     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 524 }
 525
 526 void apic_sipi(DeviceState *d)
 527 {
 528     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 529
 530     cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 531
 532     if (!s->wait_for_sipi)
 533         return;
 534     cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
 535     s->wait_for_sipi = 0;
 536 }
 537
 538 static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
 539                          uint8_t delivery_mode, uint8_t vector_num,
 540                          uint8_t polarity, uint8_t trigger_mode)
 541 {
 542     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 543     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 544     int dest_shorthand = (s->icr[0] >> 18) & 3;
 545     APICState *apic_iter;
 546
 547     switch (dest_shorthand) {
 548     case 0:
 549         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 550         break;
 551     case 1:
 552         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 553         set_bit(deliver_bitmask, s->idx);
 554         break;
 555     case 2:
 556         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 557         break;
 558     case 3:
 559         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 560         reset_bit(deliver_bitmask, s->idx);
 561         break;
 562     }
 563
 564     switch (delivery_mode) {
 565         case APIC_DM_INIT:
 566             {
 567                 int trig_mode = (s->icr[0] >> 15) & 1;
 568                 int level = (s->icr[0] >> 14) & 1;
 569                 if (level == 0 && trig_mode == 1) {
 570                     foreach_apic(apic_iter, deliver_bitmask,
 571                                  apic_iter->arb_id = apic_iter->id );
 572                     return;
 573                 }
 574             }
 575             break;
 576
 577         case APIC_DM_SIPI:
 578             foreach_apic(apic_iter, deliver_bitmask,
 579                          apic_startup(apic_iter, vector_num) );
 580             return;
 581     }
 582
 583     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 584                      trigger_mode);
 585 }
 586
 587 int apic_get_interrupt(DeviceState *d)
 588 {
 589     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 590     int intno;
 591
 592     /* if the APIC is installed or enabled, we let the 8259 handle the
 593        IRQs */
 594     if (!s)
 595         return -1;
 596     if (!(s->spurious_vec & APIC_SV_ENABLE))
 597         return -1;
 598
 599     /* XXX: spurious IRQ handling */
 600     intno = get_highest_priority_int(s->irr);
 601     if (intno < 0)
 602         return -1;
 603     if (s->tpr && intno <= s->tpr)
 604         return s->spurious_vec & 0xff;
 605     reset_bit(s->irr, intno);
 606     set_bit(s->isr, intno);
 607     apic_update_irq(s);
 608     return intno;
 609 }
 610
 611 int apic_accept_pic_intr(DeviceState *d)
 612 {
 613     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 614     uint32_t lvt0;
 615
 616     if (!s)
 617         return -1;
 618
 619     lvt0 = s->lvt[APIC_LVT_LINT0];
 620
 621     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 622         (lvt0 & APIC_LVT_MASKED) == 0)
 623         return 1;
 624
 625     return 0;
 626 }
 627
 628 static uint32_t apic_get_current_count(APICState *s)
 629 {
 630     int64_t d;
 631     uint32_t val;
 632     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 633         s->count_shift;
 634     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 635         /* periodic */
 636         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 637     } else {
 638         if (d >= s->initial_count)
 639             val = 0;
 640         else
 641             val = s->initial_count - d;
 642     }
 643     return val;
 644 }
 645
 646 static void apic_timer_update(APICState *s, int64_t current_time)
 647 {
 648     int64_t next_time, d;
 649
 650     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 651         d = (current_time - s->initial_count_load_time) >>
 652             s->count_shift;
 653         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 654             if (!s->initial_count)
 655                 goto no_timer;
 656             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 657         } else {
 658             if (d >= s->initial_count)
 659                 goto no_timer;
 660             d = (uint64_t)s->initial_count + 1;
 661         }
 662         next_time = s->initial_count_load_time + (d << s->count_shift);
 663         qemu_mod_timer(s->timer, next_time);
 664         s->next_time = next_time;
 665     } else {
 666     no_timer:
 667         qemu_del_timer(s->timer);
 668     }
 669 }
 670
 671 static void apic_timer(void *opaque)
 672 {
 673     APICState *s = opaque;
 674
 675     apic_local_deliver(s, APIC_LVT_TIMER);
 676     apic_timer_update(s, s->next_time);
 677 }
 678
 679 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 680 {
 681     return 0;
 682 }
 683
 684 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 685 {
 686     return 0;
 687 }
 688
 689 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 690 {
 691 }
 692
 693 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 694 {
 695 }
 696
 697 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 698 {
 699     DeviceState *d;
 700     APICState *s;
 701     uint32_t val;
 702     int index;
 703
 704     d = cpu_get_current_apic();
 705     if (!d) {
 706         return 0;
 707     }
 708     s = DO_UPCAST(APICState, busdev.qdev, d);
 709
 710     index = (addr >> 4) & 0xff;
 711     switch(index) {
 712     case 0x02: /* id */
 713         val = s->id << 24;
 714         break;
 715     case 0x03: /* version */
 716         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 717         break;
 718     case 0x08:
 719         val = s->tpr;
 720         break;
 721     case 0x09:
 722         val = apic_get_arb_pri(s);
 723         break;
 724     case 0x0a:
 725         /* ppr */
 726         val = apic_get_ppr(s);
 727         break;
 728     case 0x0b:
 729         val = 0;
 730         break;
 731     case 0x0d:
 732         val = s->log_dest << 24;
 733         break;
 734     case 0x0e:
 735         val = s->dest_mode << 28;
 736         break;
 737     case 0x0f:
 738         val = s->spurious_vec;
 739         break;
 740     case 0x10 ... 0x17:
 741         val = s->isr[index & 7];
 742         break;
 743     case 0x18 ... 0x1f:
 744         val = s->tmr[index & 7];
 745         break;
 746     case 0x20 ... 0x27:
 747         val = s->irr[index & 7];
 748         break;
 749     case 0x28:
 750         val = s->esr;
 751         break;
 752     case 0x30:
 753     case 0x31:
 754         val = s->icr[index & 1];
 755         break;
 756     case 0x32 ... 0x37:
 757         val = s->lvt[index - 0x32];
 758         break;
 759     case 0x38:
 760         val = s->initial_count;
 761         break;
 762     case 0x39:
 763         val = apic_get_current_count(s);
 764         break;
 765     case 0x3e:
 766         val = s->divide_conf;
 767         break;
 768     default:
 769         s->esr |= ESR_ILLEGAL_ADDRESS;
 770         val = 0;
 771         break;
 772     }
 773     trace_apic_mem_readl(addr, val);
 774     return val;
 775 }
 776
 777 static void apic_send_msi(target_phys_addr_t addr, uint32 data)
 778 {
 779     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 780     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 781     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 782     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 783     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 784     /* XXX: Ignore redirection hint. */
 785     apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
 786 }
 787
 788 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 789 {
 790     DeviceState *d;
 791     APICState *s;
 792     int index = (addr >> 4) & 0xff;
 793     if (addr > 0xfff || !index) {
 794         /* MSI and MMIO APIC are at the same memory location,
 795          * but actually not on the global bus: MSI is on PCI bus
 796          * APIC is connected directly to the CPU.
 797          * Mapping them on the global bus happens to work because
 798          * MSI registers are reserved in APIC MMIO and vice versa. */
 799         apic_send_msi(addr, val);
 800         return;
 801     }
 802
 803     d = cpu_get_current_apic();
 804     if (!d) {
 805         return;
 806     }
 807     s = DO_UPCAST(APICState, busdev.qdev, d);
 808
 809     trace_apic_mem_writel(addr, val);
 810
 811     switch(index) {
 812     case 0x02:
 813         s->id = (val >> 24);
 814         break;
 815     case 0x03:
 816         break;
 817     case 0x08:
 818         s->tpr = val;
 819         apic_update_irq(s);
 820         break;
 821     case 0x09:
 822     case 0x0a:
 823         break;
 824     case 0x0b: /* EOI */
 825         apic_eoi(s);
 826         break;
 827     case 0x0d:
 828         s->log_dest = val >> 24;
 829         break;
 830     case 0x0e:
 831         s->dest_mode = val >> 28;
 832         break;
 833     case 0x0f:
 834         s->spurious_vec = val & 0x1ff;
 835         apic_update_irq(s);
 836         break;
 837     case 0x10 ... 0x17:
 838     case 0x18 ... 0x1f:
 839     case 0x20 ... 0x27:
 840     case 0x28:
 841         break;
 842     case 0x30:
 843         s->icr[0] = val;
 844         apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 845                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 846                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 847         break;
 848     case 0x31:
 849         s->icr[1] = val;
 850         break;
 851     case 0x32 ... 0x37:
 852         {
 853             int n = index - 0x32;
 854             s->lvt[n] = val;
 855             if (n == APIC_LVT_TIMER)
 856                 apic_timer_update(s, qemu_get_clock(vm_clock));
 857         }
 858         break;
 859     case 0x38:
 860         s->initial_count = val;
 861         s->initial_count_load_time = qemu_get_clock(vm_clock);
 862         apic_timer_update(s, s->initial_count_load_time);
 863         break;
 864     case 0x39:
 865         break;
 866     case 0x3e:
 867         {
 868             int v;
 869             s->divide_conf = val & 0xb;
 870             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 871             s->count_shift = (v + 1) & 7;
 872         }
 873         break;
 874     default:
 875         s->esr |= ESR_ILLEGAL_ADDRESS;
 876         break;
 877     }
 878 }
 879
 880 #ifdef KVM_CAP_IRQCHIP
 881
 882 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 883 {
 884     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 885 }
 886
 887 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 888                                  int reg_id, uint32_t val)
 889 {
 890     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 891 }
 892
 893 static void kvm_kernel_lapic_save_to_user(APICState *s)
 894 {
 895     struct kvm_lapic_state apic;
 896     struct kvm_lapic_state *kapic = &apic;
 897     int i, v;
 898
 899     kvm_get_lapic(s->cpu_env, kapic);
 900
 901     s->id = kapic_reg(kapic, 0x2) >> 24;
 902     s->tpr = kapic_reg(kapic, 0x8);
 903     s->arb_id = kapic_reg(kapic, 0x9);
 904     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 905     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 906     s->spurious_vec = kapic_reg(kapic, 0xf);
 907     for (i = 0; i < 8; i++) {
 908         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 909         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 910         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 911     }
 912     s->esr = kapic_reg(kapic, 0x28);
 913     s->icr[0] = kapic_reg(kapic, 0x30);
 914     s->icr[1] = kapic_reg(kapic, 0x31);
 915     for (i = 0; i < APIC_LVT_NB; i++)
 916         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 917     s->initial_count = kapic_reg(kapic, 0x38);
 918     s->divide_conf = kapic_reg(kapic, 0x3e);
 919
 920     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 921     s->count_shift = (v + 1) & 7;
 922
 923     s->initial_count_load_time = qemu_get_clock(vm_clock);
 924     apic_timer_update(s, s->initial_count_load_time);
 925 }
 926
 927 static void kvm_kernel_lapic_load_from_user(APICState *s)
 928 {
 929     struct kvm_lapic_state apic;
 930     struct kvm_lapic_state *klapic = &apic;
 931     int i;
 932
 933     memset(klapic, 0, sizeof apic);
 934     kapic_set_reg(klapic, 0x2, s->id << 24);
 935     kapic_set_reg(klapic, 0x8, s->tpr);
 936     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 937     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 938     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 939     for (i = 0; i < 8; i++) {
 940         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 941         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 942         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 943     }
 944     kapic_set_reg(klapic, 0x28, s->esr);
 945     kapic_set_reg(klapic, 0x30, s->icr[0]);
 946     kapic_set_reg(klapic, 0x31, s->icr[1]);
 947     for (i = 0; i < APIC_LVT_NB; i++)
 948         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 949     kapic_set_reg(klapic, 0x38, s->initial_count);
 950     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 951
 952     kvm_set_lapic(s->cpu_env, klapic);
 953 }
 954
 955 #endif
 956
 957 void kvm_load_lapic(CPUState *env)
 958 {
 959 #ifdef KVM_CAP_IRQCHIP
 960     APICState *s = DO_UPCAST(APICState, busdev.qdev, env->apic_state);
 961
 962     if (!s) {
 963         return;
 964     }
 965
 966     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 967         kvm_kernel_lapic_load_from_user(s);
 968     }
 969 #endif
 970 }
 971
 972 void kvm_save_lapic(CPUState *env)
 973 {
 974 #ifdef KVM_CAP_IRQCHIP
 975     APICState *s = DO_UPCAST(APICState, busdev.qdev, env->apic_state);
 976
 977     if (!s) {
 978         return;
 979     }
 980
 981     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 982         kvm_kernel_lapic_save_to_user(s);
 983     }
 984 #endif
 985 }
 986
 987 /* This function is only used for old state version 1 and 2 */
 988 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 989 {
 990     APICState *s = opaque;
 991     int i;
 992
 993     if (version_id > 2)
 994         return -EINVAL;
 995
 996     /* XXX: what if the base changes? (registered memory regions) */
 997     qemu_get_be32s(f, &s->apicbase);
 998     qemu_get_8s(f, &s->id);
 999     qemu_get_8s(f, &s->arb_id);
1000     qemu_get_8s(f, &s->tpr);
1001     qemu_get_be32s(f, &s->spurious_vec);
1002     qemu_get_8s(f, &s->log_dest);
1003     qemu_get_8s(f, &s->dest_mode);
1004     for (i = 0; i < 8; i++) {
1005         qemu_get_be32s(f, &s->isr[i]);
1006         qemu_get_be32s(f, &s->tmr[i]);
1007         qemu_get_be32s(f, &s->irr[i]);
1008     }
1009     for (i = 0; i < APIC_LVT_NB; i++) {
1010         qemu_get_be32s(f, &s->lvt[i]);
1011     }
1012     qemu_get_be32s(f, &s->esr);
1013     qemu_get_be32s(f, &s->icr[0]);
1014     qemu_get_be32s(f, &s->icr[1]);
1015     qemu_get_be32s(f, &s->divide_conf);
1016     s->count_shift=qemu_get_be32(f);
1017     qemu_get_be32s(f, &s->initial_count);
1018     s->initial_count_load_time=qemu_get_be64(f);
1019     s->next_time=qemu_get_be64(f);
1020
1021     if (version_id >= 2)
1022         qemu_get_timer(f, s->timer);
1023     return 0;
1024 }
1025
1026 static const VMStateDescription vmstate_apic = {
1027     .name = "apic",
1028     .version_id = 3,
1029     .minimum_version_id = 3,
1030     .minimum_version_id_old = 1,
1031     .load_state_old = apic_load_old,
1032     .fields      = (VMStateField []) {
1033         VMSTATE_UINT32(apicbase, APICState),
1034         VMSTATE_UINT8(id, APICState),
1035         VMSTATE_UINT8(arb_id, APICState),
1036         VMSTATE_UINT8(tpr, APICState),
1037         VMSTATE_UINT32(spurious_vec, APICState),
1038         VMSTATE_UINT8(log_dest, APICState),
1039         VMSTATE_UINT8(dest_mode, APICState),
1040         VMSTATE_UINT32_ARRAY(isr, APICState, 8),
1041         VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
1042         VMSTATE_UINT32_ARRAY(irr, APICState, 8),
1043         VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
1044         VMSTATE_UINT32(esr, APICState),
1045         VMSTATE_UINT32_ARRAY(icr, APICState, 2),
1046         VMSTATE_UINT32(divide_conf, APICState),
1047         VMSTATE_INT32(count_shift, APICState),
1048         VMSTATE_UINT32(initial_count, APICState),
1049         VMSTATE_INT64(initial_count_load_time, APICState),
1050         VMSTATE_INT64(next_time, APICState),
1051         VMSTATE_TIMER(timer, APICState),
1052         VMSTATE_END_OF_LIST()
1053     }
1054 };
1055
1056 static void apic_reset(DeviceState *d)
1057 {
1058     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
1059     int bsp;
1060
1061     bsp = cpu_is_bsp(s->cpu_env);
1062     s->apicbase = 0xfee00000 |
1063         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
1064
1065     apic_init_reset(d);
1066
1067     if (bsp) {
1068         /*
1069          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1070          * time typically by BIOS, so PIC interrupt can be delivered to the
1071          * processor when local APIC is enabled.
1072          */
1073         s->lvt[APIC_LVT_LINT0] = 0x700;
1074     }
1075 }
1076
1077 static CPUReadMemoryFunc * const apic_mem_read[3] = {
1078     apic_mem_readb,
1079     apic_mem_readw,
1080     apic_mem_readl,
1081 };
1082
1083 static CPUWriteMemoryFunc * const apic_mem_write[3] = {
1084     apic_mem_writeb,
1085     apic_mem_writew,
1086     apic_mem_writel,
1087 };
1088
1089 static int apic_init1(SysBusDevice *dev)
1090 {
1091     APICState *s = FROM_SYSBUS(APICState, dev);
1092     int apic_io_memory;
1093     static int last_apic_idx;
1094
1095     if (last_apic_idx >= MAX_APICS) {
1096         return -1;
1097     }
1098     apic_io_memory = cpu_register_io_memory(apic_mem_read,
1099                                             apic_mem_write, NULL);
1100     sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
1101
1102     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1103     s->idx = last_apic_idx++;
1104     local_apics[s->idx] = s;
1105     return 0;
1106 }
1107
1108 static SysBusDeviceInfo apic_info = {
1109     .init = apic_init1,
1110     .qdev.name = "apic",
1111     .qdev.size = sizeof(APICState),
1112     .qdev.vmsd = &vmstate_apic,
1113     .qdev.reset = apic_reset,
1114     .qdev.no_user = 1,
1115     .qdev.props = (Property[]) {
1116         DEFINE_PROP_UINT8("id", APICState, id, -1),
1117         DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
1118         DEFINE_PROP_END_OF_LIST(),
1119     }
1120 };
1121
1122 static void apic_register_devices(void)
1123 {
1124     sysbus_register_withprop(&apic_info);
1125 }
1126
1127 device_init(apic_register_devices)