hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "acpi.h"
  24 #include "sysemu.h"
  25 #include "range.h"
  26
  27 //#define DEBUG
  28
  29 #ifdef DEBUG
  30 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  31 #else
  32 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  33 #endif
  34
  35 #define ACPI_DBG_IO_ADDR  0xb044
  36
  37 #define GPE_BASE 0xafe0
  38 #define PROC_BASE 0xaf00
  39 #define PCI_BASE 0xae00
  40 #define PCI_EJ_BASE 0xae08
  41
  42 #define PIIX4_CPU_HOTPLUG_STATUS 4
  43 #define PIIX4_PCI_HOTPLUG_STATUS 2
  44
  45 struct gpe_regs {
  46     uint16_t sts; /* status */
  47     uint16_t en;  /* enabled */
  48     uint8_t cpus_sts[32];
  49 };
  50
  51 struct pci_status {
  52     uint32_t up;
  53     uint32_t down;
  54 };
  55
  56 typedef struct PIIX4PMState {
  57     PCIDevice dev;
  58     IORange ioport;
  59     uint16_t pmsts;
  60     uint16_t pmen;
  61     uint16_t pmcntrl;
  62
  63     APMState apm;
  64
  65     QEMUTimer *tmr_timer;
  66     int64_t tmr_overflow_time;
  67
  68     PMSMBus smb;
  69     uint32_t smb_io_base;
  70
  71     qemu_irq irq;
  72     qemu_irq cmos_s3;
  73     qemu_irq smi_irq;
  74     int kvm_enabled;
  75
  76     /* for pci hotplug */
  77     struct gpe_regs gpe;
  78     struct pci_status pci0_status;
  79 } PIIX4PMState;
  80
  81 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  82
  83 #define ACPI_ENABLE 0xf1
  84 #define ACPI_DISABLE 0xf0
  85
  86 static uint32_t get_pmtmr(PIIX4PMState *s)
  87 {
  88     uint32_t d;
  89     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
  90     return d & 0xffffff;
  91 }
  92
  93 static int get_pmsts(PIIX4PMState *s)
  94 {
  95     int64_t d;
  96
  97     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
  98                  get_ticks_per_sec());
  99     if (d >= s->tmr_overflow_time)
 100         s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
 101     return s->pmsts;
 102 }
 103
 104 static void pm_update_sci(PIIX4PMState *s)
 105 {
 106     int sci_level, pmsts;
 107     int64_t expire_time;
 108
 109     pmsts = get_pmsts(s);
 110     sci_level = (((pmsts & s->pmen) &
 111                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
 112                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
 113                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
 114                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
 115         (((s->gpe.sts & s->gpe.en) &
 116           (PIIX4_CPU_HOTPLUG_STATUS | PIIX4_PCI_HOTPLUG_STATUS)) != 0);
 117
 118     qemu_set_irq(s->irq, sci_level);
 119     /* schedule a timer interruption if needed */
 120     if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
 121         !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
 122         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
 123                                PM_TIMER_FREQUENCY);
 124         qemu_mod_timer(s->tmr_timer, expire_time);
 125     } else {
 126         qemu_del_timer(s->tmr_timer);
 127     }
 128 }
 129
 130 static void pm_tmr_timer(void *opaque)
 131 {
 132     PIIX4PMState *s = opaque;
 133     pm_update_sci(s);
 134 }
 135
 136 static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
 137                             uint64_t val)
 138 {
 139     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 140
 141     if (width != 2) {
 142         PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
 143                       (unsigned)addr, width, (unsigned)val);
 144     }
 145
 146     switch(addr) {
 147     case 0x00:
 148         {
 149             int64_t d;
 150             int pmsts;
 151             pmsts = get_pmsts(s);
 152             if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
 153                 /* if TMRSTS is reset, then compute the new overflow time */
 154                 d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
 155                              get_ticks_per_sec());
 156                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 157             }
 158             s->pmsts &= ~val;
 159             pm_update_sci(s);
 160         }
 161         break;
 162     case 0x02:
 163         s->pmen = val;
 164         pm_update_sci(s);
 165         break;
 166     case 0x04:
 167         {
 168             int sus_typ;
 169             s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
 170             if (val & ACPI_BITMASK_SLEEP_ENABLE) {
 171                 /* change suspend type */
 172                 sus_typ = (val >> 10) & 7;
 173                 switch(sus_typ) {
 174                 case 0: /* soft power off */
 175                     qemu_system_shutdown_request();
 176                     break;
 177                 case 1:
 178                     /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
 179                        Pretend that resume was caused by power button */
 180                     s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
 181                                  ACPI_BITMASK_POWER_BUTTON_STATUS);
 182                     qemu_system_reset_request();
 183                     if (s->cmos_s3) {
 184                         qemu_irq_raise(s->cmos_s3);
 185                     }
 186                 default:
 187                     break;
 188                 }
 189             }
 190         }
 191         break;
 192     default:
 193         break;
 194     }
 195     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
 196 }
 197
 198 static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
 199                             uint64_t *data)
 200 {
 201     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 202     uint32_t val;
 203
 204     switch(addr) {
 205     case 0x00:
 206         val = get_pmsts(s);
 207         break;
 208     case 0x02:
 209         val = s->pmen;
 210         break;
 211     case 0x04:
 212         val = s->pmcntrl;
 213         break;
 214     case 0x08:
 215         val = get_pmtmr(s);
 216         break;
 217     default:
 218         val = 0;
 219         break;
 220     }
 221     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
 222     *data = val;
 223 }
 224
 225 static const IORangeOps pm_iorange_ops = {
 226     .read = pm_ioport_read,
 227     .write = pm_ioport_write,
 228 };
 229
 230 static void apm_ctrl_changed(uint32_t val, void *arg)
 231 {
 232     PIIX4PMState *s = arg;
 233
 234     /* ACPI specs 3.0, 4.7.2.5 */
 235     if (val == ACPI_ENABLE) {
 236         s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
 237     } else if (val == ACPI_DISABLE) {
 238         s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
 239     }
 240
 241     if (s->dev.config[0x5b] & (1 << 1)) {
 242         if (s->smi_irq) {
 243             qemu_irq_raise(s->smi_irq);
 244         }
 245     }
 246 }
 247
 248 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 249 {
 250     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 251 }
 252
 253 static void pm_io_space_update(PIIX4PMState *s)
 254 {
 255     uint32_t pm_io_base;
 256
 257     if (s->dev.config[0x80] & 1) {
 258         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 259         pm_io_base &= 0xffc0;
 260
 261         /* XXX: need to improve memory and ioport allocation */
 262         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 263         iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
 264         ioport_register(&s->ioport);
 265     }
 266 }
 267
 268 static void pm_write_config(PCIDevice *d,
 269                             uint32_t address, uint32_t val, int len)
 270 {
 271     pci_default_write_config(d, address, val, len);
 272     if (range_covers_byte(address, len, 0x80))
 273         pm_io_space_update((PIIX4PMState *)d);
 274 }
 275
 276 static int vmstate_acpi_post_load(void *opaque, int version_id)
 277 {
 278     PIIX4PMState *s = opaque;
 279
 280     pm_io_space_update(s);
 281     return 0;
 282 }
 283
 284 static const VMStateDescription vmstate_gpe = {
 285     .name = "gpe",
 286     .version_id = 1,
 287     .minimum_version_id = 1,
 288     .minimum_version_id_old = 1,
 289     .fields      = (VMStateField []) {
 290         VMSTATE_UINT16(sts, struct gpe_regs),
 291         VMSTATE_UINT16(en, struct gpe_regs),
 292         VMSTATE_END_OF_LIST()
 293     }
 294 };
 295
 296 static const VMStateDescription vmstate_pci_status = {
 297     .name = "pci_status",
 298     .version_id = 1,
 299     .minimum_version_id = 1,
 300     .minimum_version_id_old = 1,
 301     .fields      = (VMStateField []) {
 302         VMSTATE_UINT32(up, struct pci_status),
 303         VMSTATE_UINT32(down, struct pci_status),
 304         VMSTATE_END_OF_LIST()
 305     }
 306 };
 307
 308 static const VMStateDescription vmstate_acpi = {
 309     .name = "piix4_pm",
 310     .version_id = 2,
 311     .minimum_version_id = 1,
 312     .minimum_version_id_old = 1,
 313     .post_load = vmstate_acpi_post_load,
 314     .fields      = (VMStateField []) {
 315         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 316         VMSTATE_UINT16(pmsts, PIIX4PMState),
 317         VMSTATE_UINT16(pmen, PIIX4PMState),
 318         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
 319         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 320         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
 321         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
 322         VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, struct gpe_regs),
 323         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 324                        struct pci_status),
 325         VMSTATE_END_OF_LIST()
 326     }
 327 };
 328
 329 static void piix4_reset(void *opaque)
 330 {
 331     PIIX4PMState *s = opaque;
 332     uint8_t *pci_conf = s->dev.config;
 333
 334     pci_conf[0x58] = 0;
 335     pci_conf[0x59] = 0;
 336     pci_conf[0x5a] = 0;
 337     pci_conf[0x5b] = 0;
 338
 339     if (s->kvm_enabled) {
 340         /* Mark SMM as already inited (until KVM supports SMM). */
 341         pci_conf[0x5B] = 0x02;
 342     }
 343 }
 344
 345 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 346 {
 347     PIIX4PMState *s = opaque;
 348
 349     if (!s) {
 350         qemu_system_shutdown_request();
 351     } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
 352         s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
 353         pm_update_sci(s);
 354     }
 355 }
 356
 357 static PIIX4PMState *global_piix4_pm_state; /* cpu hotadd */
 358
 359 static int piix4_pm_initfn(PCIDevice *dev)
 360 {
 361     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 362     uint8_t *pci_conf;
 363
 364     /* for cpu hotadd */
 365     global_piix4_pm_state = s;
 366
 367     pci_conf = s->dev.config;
 368     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 369     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 370     pci_conf[0x06] = 0x80;
 371     pci_conf[0x07] = 0x02;
 372     pci_conf[0x08] = 0x03; // revision number
 373     pci_conf[0x09] = 0x00;
 374     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 375     pci_conf[0x3d] = 0x01; // interrupt pin 1
 376
 377     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 378
 379 #if defined(TARGET_IA64)
 380     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 381     pci_conf[0x41] = 0x1f;
 382     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 383     s->pmcntrl = SCI_EN;
 384 #endif
 385
 386     /* APM */
 387     apm_init(&s->apm, apm_ctrl_changed, s);
 388
 389     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 390
 391     if (s->kvm_enabled) {
 392         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 393          * support SMM mode. */
 394         pci_conf[0x5B] = 0x02;
 395     }
 396
 397     /* XXX: which specification is used ? The i82731AB has different
 398        mappings */
 399     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 400     pci_conf[0x63] = 0x60;
 401     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 402         (serial_hds[1] != NULL ? 0x90 : 0);
 403
 404     pci_conf[0x90] = s->smb_io_base | 1;
 405     pci_conf[0x91] = s->smb_io_base >> 8;
 406     pci_conf[0xd2] = 0x09;
 407     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 408     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 409
 410     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 411
 412     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 413
 414     pm_smbus_init(&s->dev.qdev, &s->smb);
 415     qemu_register_reset(piix4_reset, s);
 416     piix4_acpi_system_hot_add_init(dev->bus, s);
 417
 418     return 0;
 419 }
 420
 421 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 422                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 423                        int kvm_enabled)
 424 {
 425     PCIDevice *dev;
 426     PIIX4PMState *s;
 427
 428     dev = pci_create(bus, devfn, "PIIX4_PM");
 429     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 430
 431     s = DO_UPCAST(PIIX4PMState, dev, dev);
 432     s->irq = sci_irq;
 433     s->cmos_s3 = cmos_s3;
 434     s->smi_irq = smi_irq;
 435     s->kvm_enabled = kvm_enabled;
 436
 437     qdev_init_nofail(&dev->qdev);
 438
 439     return s->smb.smbus;
 440 }
 441
 442 static PCIDeviceInfo piix4_pm_info = {
 443     .qdev.name          = "PIIX4_PM",
 444     .qdev.desc          = "PM",
 445     .qdev.size          = sizeof(PIIX4PMState),
 446     .qdev.vmsd          = &vmstate_acpi,
 447     .init               = piix4_pm_initfn,
 448     .config_write       = pm_write_config,
 449     .qdev.props         = (Property[]) {
 450         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 451         DEFINE_PROP_END_OF_LIST(),
 452     }
 453 };
 454
 455 static void piix4_pm_register(void)
 456 {
 457     pci_qdev_register(&piix4_pm_info);
 458 }
 459
 460 device_init(piix4_pm_register);
 461
 462 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 463 {
 464     if (addr & 1)
 465         return (val >> 8) & 0xff;
 466     return val & 0xff;
 467 }
 468
 469 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 470 {
 471     uint32_t val = 0;
 472     PIIX4PMState *s = opaque;
 473     struct gpe_regs *g = &s->gpe;
 474
 475     switch (addr) {
 476         case PROC_BASE ... PROC_BASE+31:
 477             val = g->cpus_sts[addr - PROC_BASE];
 478             break;
 479
 480         case GPE_BASE:
 481         case GPE_BASE + 1:
 482             val = gpe_read_val(g->sts, addr);
 483             break;
 484         case GPE_BASE + 2:
 485         case GPE_BASE + 3:
 486             val = gpe_read_val(g->en, addr);
 487             break;
 488         default:
 489             break;
 490     }
 491
 492     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 493     return val;
 494 }
 495
 496 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 497 {
 498     if (addr & 1)
 499         *cur = (*cur & 0xff) | (val << 8);
 500     else
 501         *cur = (*cur & 0xff00) | (val & 0xff);
 502 }
 503
 504 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 505 {
 506     uint16_t x1, x0 = val & 0xff;
 507     int shift = (addr & 1) ? 8 : 0;
 508
 509     x1 = (*cur >> shift) & 0xff;
 510
 511     x1 = x1 & ~x0;
 512
 513     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 514 }
 515
 516 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 517 {
 518     PIIX4PMState *s = opaque;
 519     struct gpe_regs *g = &s->gpe;
 520
 521     switch (addr) {
 522         case GPE_BASE:
 523         case GPE_BASE + 1:
 524             gpe_reset_val(&g->sts, addr, val);
 525             break;
 526         case GPE_BASE + 2:
 527         case GPE_BASE + 3:
 528             gpe_write_val(&g->en, addr, val);
 529             break;
 530         default:
 531             break;
 532     }
 533
 534     pm_update_sci(s);
 535
 536     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 537 }
 538
 539 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 540 {
 541     uint32_t val = 0;
 542     struct pci_status *g = opaque;
 543     switch (addr) {
 544         case PCI_BASE:
 545             val = g->up;
 546             break;
 547         case PCI_BASE + 4:
 548             val = g->down;
 549             break;
 550         default:
 551             break;
 552     }
 553
 554     PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
 555     return val;
 556 }
 557
 558 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 559 {
 560     struct pci_status *g = opaque;
 561     switch (addr) {
 562         case PCI_BASE:
 563             g->up = val;
 564             break;
 565         case PCI_BASE + 4:
 566             g->down = val;
 567             break;
 568    }
 569
 570     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
 571 }
 572
 573 static uint32_t pciej_read(void *opaque, uint32_t addr)
 574 {
 575     PIIX4_DPRINTF("pciej read %x\n", addr);
 576     return 0;
 577 }
 578
 579 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 580 {
 581     BusState *bus = opaque;
 582     DeviceState *qdev, *next;
 583     PCIDevice *dev;
 584     int slot = ffs(val) - 1;
 585
 586     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 587         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 588         if (PCI_SLOT(dev->devfn) == slot) {
 589             qdev_free(qdev);
 590         }
 591     }
 592
 593
 594     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 595 }
 596
 597 extern const char *global_cpu_model;
 598
 599 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 600                                 PCIHotplugState state);
 601
 602 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 603 {
 604     struct pci_status *pci0_status = &s->pci0_status;
 605     int i = 0, cpus = smp_cpus;
 606
 607     while (cpus > 0) {
 608         s->gpe.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
 609         cpus -= 8;
 610     }
 611
 612     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s);
 613     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, s);
 614
 615     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, s);
 616     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, s);
 617
 618     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
 619     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
 620
 621     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 622     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 623
 624     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 625 }
 626
 627 #if defined(TARGET_I386)
 628 static void enable_processor(struct gpe_regs *g, int cpu)
 629 {
 630     g->sts |= PIIX4_CPU_HOTPLUG_STATUS;
 631     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
 632 }
 633
 634 static void disable_processor(struct gpe_regs *g, int cpu)
 635 {
 636     g->sts |= PIIX4_CPU_HOTPLUG_STATUS;
 637     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
 638 }
 639
 640 void qemu_system_cpu_hot_add(int cpu, int state)
 641 {
 642     CPUState *env;
 643     PIIX4PMState *s = global_piix4_pm_state;
 644
 645     if (state && !qemu_get_cpu(cpu)) {
 646         env = pc_new_cpu(global_cpu_model);
 647         if (!env) {
 648             fprintf(stderr, "cpu %d creation failed\n", cpu);
 649             return;
 650         }
 651         env->cpuid_apic_id = cpu;
 652     }
 653
 654     if (state)
 655         enable_processor(&s->gpe, cpu);
 656     else
 657         disable_processor(&s->gpe, cpu);
 658
 659     pm_update_sci(s);
 660 }
 661 #endif
 662
 663 static void enable_device(PIIX4PMState *s, int slot)
 664 {
 665     s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
 666     s->pci0_status.up |= (1 << slot);
 667 }
 668
 669 static void disable_device(PIIX4PMState *s, int slot)
 670 {
 671     s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
 672     s->pci0_status.down |= (1 << slot);
 673 }
 674
 675 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 676                                 PCIHotplugState state)
 677 {
 678     int slot = PCI_SLOT(dev->devfn);
 679     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 680                                 DO_UPCAST(PCIDevice, qdev, qdev));
 681
 682     /* Don't send event when device is enabled during qemu machine creation:
 683      * it is present on boot, no hotplug event is necessary. We do send an
 684      * event when the device is disabled later. */
 685     if (state == PCI_COLDPLUG_ENABLED) {
 686         return 0;
 687     }
 688
 689     s->pci0_status.up = 0;
 690     s->pci0_status.down = 0;
 691     if (state == PCI_HOTPLUG_ENABLED) {
 692         enable_device(s, slot);
 693     } else {
 694         disable_device(s, slot);
 695     }
 696
 697     pm_update_sci(s);
 698
 699     return 0;
 700 }