hw/testdev.c

   1 #include "hw.h"
   2 #include "qdev.h"
   3 #include "isa.h"
   4
   5 struct testdev {
   6     ISADevice dev;
   7     CharDriverState *chr;
   8 };
   9
  10 static void test_device_serial_write(void *opaque, uint32_t addr, uint32_t data)
  11 {
  12     struct testdev *dev = opaque;
  13     uint8_t buf[1] = { data };
  14
  15     if (dev->chr) {
  16         qemu_chr_write(dev->chr, buf, 1);
  17     }
  18 }
  19
  20 static void test_device_exit(void *opaque, uint32_t addr, uint32_t data)
  21 {
  22     exit(data);
  23 }
  24
  25 static uint32_t test_device_memsize_read(void *opaque, uint32_t addr)
  26 {
  27     return ram_size;
  28 }
  29
  30 extern qemu_irq *ioapic_irq_hack;
  31
  32 static void test_device_irq_line(void *opaque, uint32_t addr, uint32_t data)
  33 {
  34     qemu_set_irq(ioapic_irq_hack[addr - 0x2000], !!data);
  35 }
  36
  37 static uint32 test_device_ioport_data;
  38
  39 static void test_device_ioport_write(void *opaque, uint32_t addr, uint32_t data)
  40 {
  41     test_device_ioport_data = data;
  42 }
  43
  44 static uint32_t test_device_ioport_read(void *opaque, uint32_t addr)
  45 {
  46     return test_device_ioport_data;
  47 }
  48
  49 static char *iomem_buf;
  50
  51 static uint32_t test_iomem_readb(void *opaque, target_phys_addr_t addr)
  52 {
  53     return iomem_buf[addr];
  54 }
  55
  56 static uint32_t test_iomem_readw(void *opaque, target_phys_addr_t addr)
  57 {
  58     return *(uint16_t*)(iomem_buf + addr);
  59 }
  60
  61 static uint32_t test_iomem_readl(void *opaque, target_phys_addr_t addr)
  62 {
  63     return *(uint32_t*)(iomem_buf + addr);
  64 }
  65
  66 static void test_iomem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  67 {
  68     iomem_buf[addr] = val;
  69 }
  70
  71 static void test_iomem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
  72 {
  73     *(uint16_t*)(iomem_buf + addr) = val;
  74 }
  75
  76 static void test_iomem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  77 {
  78     *(uint32_t*)(iomem_buf + addr) = val;
  79 }
  80
  81 static CPUReadMemoryFunc * const test_iomem_read[3] = {
  82     test_iomem_readb,
  83     test_iomem_readw,
  84     test_iomem_readl,
  85 };
  86
  87 static CPUWriteMemoryFunc * const test_iomem_write[3] = {
  88     test_iomem_writeb,
  89     test_iomem_writew,
  90     test_iomem_writel,
  91 };
  92
  93 static int init_test_device(ISADevice *isa)
  94 {
  95     struct testdev *dev = DO_UPCAST(struct testdev, dev, isa);
  96     int iomem;
  97
  98     register_ioport_write(0xf1, 1, 1, test_device_serial_write, dev);
  99     register_ioport_write(0xf4, 1, 4, test_device_exit, dev);
 100     register_ioport_read(0xd1, 1, 4, test_device_memsize_read, dev);
 101     register_ioport_read(0xe0, 1, 1, test_device_ioport_read, dev);
 102     register_ioport_write(0xe0, 1, 1, test_device_ioport_write, dev);
 103     register_ioport_read(0xe0, 1, 2, test_device_ioport_read, dev);
 104     register_ioport_write(0xe0, 1, 2, test_device_ioport_write, dev);
 105     register_ioport_read(0xe0, 1, 4, test_device_ioport_read, dev);
 106     register_ioport_write(0xe0, 1, 4, test_device_ioport_write, dev);
 107     register_ioport_write(0x2000, 24, 1, test_device_irq_line, NULL);
 108     iomem_buf = qemu_mallocz(0x10000);
 109     iomem = cpu_register_io_memory(test_iomem_read, test_iomem_write, NULL);
 110     cpu_register_physical_memory(0xff000000, 0x10000, iomem);
 111     return 0;
 112 }
 113
 114 static ISADeviceInfo testdev_info = {
 115     .qdev.name  = "testdev",
 116     .qdev.size  = sizeof(struct testdev),
 117     .init       = init_test_device,
 118     .qdev.props = (Property[]) {
 119         DEFINE_PROP_CHR("chardev", struct testdev, chr),
 120         DEFINE_PROP_END_OF_LIST(),
 121     },
 122 };
 123
 124 static void testdev_register_devices(void)
 125 {
 126     isa_qdev_register(&testdev_info);
 127 }
 128
 129 device_init(testdev_register_devices)