hw/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "hw.h"
  24 #include "pc.h"
  25 #include "apic.h"
  26 #include "sysemu.h"
  27 #include "apic.h"
  28 #include "qemu-timer.h"
  29 #include "host-utils.h"
  30 #include "sysbus.h"
  31
  32 #include "kvm.h"
  33
  34 //#define DEBUG_IOAPIC
  35
  36 #ifdef DEBUG_IOAPIC
  37 #define DPRINTF(fmt, ...)                                       \
  38     do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
  39 #else
  40 #define DPRINTF(fmt, ...)
  41 #endif
  42
  43 #define IOAPIC_DEFAULT_BASE_ADDRESS  0xfec00000
  44 #define IOAPIC_LVT_MASKED               (1<<16)
  45
  46 #define IOAPIC_TRIGGER_EDGE             0
  47 #define IOAPIC_TRIGGER_LEVEL            1
  48
  49 /*io{apic,sapic} delivery mode*/
  50 #define IOAPIC_DM_FIXED                 0x0
  51 #define IOAPIC_DM_LOWEST_PRIORITY       0x1
  52 #define IOAPIC_DM_PMI                   0x2
  53 #define IOAPIC_DM_NMI                   0x4
  54 #define IOAPIC_DM_INIT                  0x5
  55 #define IOAPIC_DM_SIPI                  0x5
  56 #define IOAPIC_DM_EXTINT                0x7
  57
  58 typedef struct IOAPICState IOAPICState;
  59
  60 struct IOAPICState {
  61     SysBusDevice busdev;
  62     uint8_t id;
  63     uint8_t ioregsel;
  64     uint64_t base_address;
  65
  66     uint32_t irr;
  67     uint64_t ioredtbl[IOAPIC_NUM_PINS];
  68 };
  69
  70 static void ioapic_service(IOAPICState *s)
  71 {
  72     uint8_t i;
  73     uint8_t trig_mode;
  74     uint8_t vector;
  75     uint8_t delivery_mode;
  76     uint32_t mask;
  77     uint64_t entry;
  78     uint8_t dest;
  79     uint8_t dest_mode;
  80     uint8_t polarity;
  81
  82     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  83         mask = 1 << i;
  84         if (s->irr & mask) {
  85             entry = s->ioredtbl[i];
  86             if (!(entry & IOAPIC_LVT_MASKED)) {
  87                 trig_mode = ((entry >> 15) & 1);
  88                 dest = entry >> 56;
  89                 dest_mode = (entry >> 11) & 1;
  90                 delivery_mode = (entry >> 8) & 7;
  91                 polarity = (entry >> 13) & 1;
  92                 if (trig_mode == IOAPIC_TRIGGER_EDGE)
  93                     s->irr &= ~mask;
  94                 if (delivery_mode == IOAPIC_DM_EXTINT)
  95                     vector = pic_read_irq(isa_pic);
  96                 else
  97                     vector = entry & 0xff;
  98
  99                 apic_deliver_irq(dest, dest_mode, delivery_mode,
 100                                  vector, polarity, trig_mode);
 101             }
 102         }
 103     }
 104 }
 105
 106 static void ioapic_set_irq(void *opaque, int vector, int level)
 107 {
 108     IOAPICState *s = opaque;
 109
 110     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 111      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 112      * the cleanest way of doing it but it should work. */
 113
 114     DPRINTF("%s: %s vec %x\n", __func__, level? "raise" : "lower", vector);
 115     if (vector == 0 && irq0override) {
 116         vector = 2;
 117     }
 118
 119     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 120         uint32_t mask = 1 << vector;
 121         uint64_t entry = s->ioredtbl[vector];
 122
 123         if ((entry >> 15) & 1) {
 124             /* level triggered */
 125             if (level) {
 126                 s->irr |= mask;
 127                 ioapic_service(s);
 128             } else {
 129                 s->irr &= ~mask;
 130             }
 131         } else {
 132             /* edge triggered */
 133             if (level) {
 134                 s->irr |= mask;
 135                 ioapic_service(s);
 136             }
 137         }
 138     }
 139 }
 140
 141 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
 142 {
 143     IOAPICState *s = opaque;
 144     int index;
 145     uint32_t val = 0;
 146
 147     addr &= 0xff;
 148     if (addr == 0x00) {
 149         val = s->ioregsel;
 150     } else if (addr == 0x10) {
 151         switch (s->ioregsel) {
 152             case 0x00:
 153                 val = s->id << 24;
 154                 break;
 155             case 0x01:
 156                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
 157                 break;
 158             case 0x02:
 159                 val = 0;
 160                 break;
 161             default:
 162                 index = (s->ioregsel - 0x10) >> 1;
 163                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 164                     if (s->ioregsel & 1)
 165                         val = s->ioredtbl[index] >> 32;
 166                     else
 167                         val = s->ioredtbl[index] & 0xffffffff;
 168                 }
 169         }
 170         DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
 171     }
 172     return val;
 173 }
 174
 175 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 176 {
 177     IOAPICState *s = opaque;
 178     int index;
 179
 180     addr &= 0xff;
 181     if (addr == 0x00)  {
 182         s->ioregsel = val;
 183         return;
 184     } else if (addr == 0x10) {
 185         DPRINTF("write: %08x = %08x\n", s->ioregsel, val);
 186         switch (s->ioregsel) {
 187             case 0x00:
 188                 s->id = (val >> 24) & 0xff;
 189                 return;
 190             case 0x01:
 191             case 0x02:
 192                 return;
 193             default:
 194                 index = (s->ioregsel - 0x10) >> 1;
 195                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 196                     if (s->ioregsel & 1) {
 197                         s->ioredtbl[index] &= 0xffffffff;
 198                         s->ioredtbl[index] |= (uint64_t)val << 32;
 199                     } else {
 200                         s->ioredtbl[index] &= ~0xffffffffULL;
 201                         s->ioredtbl[index] |= val;
 202                     }
 203                     ioapic_service(s);
 204                 }
 205         }
 206     }
 207 }
 208
 209 static void kvm_kernel_ioapic_save_to_user(IOAPICState *s)
 210 {
 211 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 212     struct kvm_irqchip chip;
 213     struct kvm_ioapic_state *kioapic;
 214     int i;
 215
 216     chip.chip_id = KVM_IRQCHIP_IOAPIC;
 217     kvm_get_irqchip(kvm_context, &chip);
 218     kioapic = &chip.chip.ioapic;
 219
 220     s->id = kioapic->id;
 221     s->ioregsel = kioapic->ioregsel;
 222     s->base_address = kioapic->base_address;
 223     s->irr = kioapic->irr;
 224     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 225         s->ioredtbl[i] = kioapic->redirtbl[i].bits;
 226     }
 227 #endif
 228 }
 229
 230 static void kvm_kernel_ioapic_load_from_user(IOAPICState *s)
 231 {
 232 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 233     struct kvm_irqchip chip;
 234     struct kvm_ioapic_state *kioapic;
 235     int i;
 236
 237     chip.chip_id = KVM_IRQCHIP_IOAPIC;
 238     kioapic = &chip.chip.ioapic;
 239
 240     kioapic->id = s->id;
 241     kioapic->ioregsel = s->ioregsel;
 242     kioapic->base_address = s->base_address;
 243     kioapic->irr = s->irr;
 244     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 245         kioapic->redirtbl[i].bits = s->ioredtbl[i];
 246     }
 247
 248     kvm_set_irqchip(kvm_context, &chip);
 249 #endif
 250 }
 251
 252 static void ioapic_pre_save(void *opaque)
 253 {
 254     IOAPICState *s = (void *)opaque;
 255
 256     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 257         kvm_kernel_ioapic_save_to_user(s);
 258     }
 259 }
 260
 261 static int ioapic_pre_load(void *opaque)
 262 {
 263     IOAPICState *s = opaque;
 264
 265     /* in case we are doing version 1, we just set these to sane values */
 266     s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 267     s->irr = 0;
 268     return 0;
 269 }
 270
 271 static int ioapic_post_load(void *opaque, int version_id)
 272 {
 273     IOAPICState *s = opaque;
 274
 275     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 276         kvm_kernel_ioapic_load_from_user(s);
 277     }
 278     return 0;
 279 }
 280
 281 static const VMStateDescription vmstate_ioapic = {
 282     .name = "ioapic",
 283     .version_id = 2,
 284     .minimum_version_id = 1,
 285     .minimum_version_id_old = 1,
 286     .pre_load = ioapic_pre_load,
 287     .post_load = ioapic_post_load,
 288     .pre_save = ioapic_pre_save,
 289     .fields      = (VMStateField []) {
 290         VMSTATE_UINT8(id, IOAPICState),
 291         VMSTATE_UINT8(ioregsel, IOAPICState),
 292         VMSTATE_UINT64_V(base_address, IOAPICState, 2),
 293         VMSTATE_UINT32_V(irr, IOAPICState, 2),
 294         VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
 295         VMSTATE_END_OF_LIST()
 296     }
 297 };
 298
 299 static void ioapic_reset(DeviceState *d)
 300 {
 301     IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d);
 302     int i;
 303
 304     s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 305     s->id = 0;
 306     s->ioregsel = 0;
 307     s->irr = 0;
 308     for(i = 0; i < IOAPIC_NUM_PINS; i++)
 309         s->ioredtbl[i] = 1 << 16; /* mask LVT */
 310 #ifdef KVM_CAP_IRQCHIP
 311     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 312         kvm_kernel_ioapic_load_from_user(s);
 313     }
 314 #endif
 315 }
 316
 317 static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
 318     ioapic_mem_readl,
 319     ioapic_mem_readl,
 320     ioapic_mem_readl,
 321 };
 322
 323 static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
 324     ioapic_mem_writel,
 325     ioapic_mem_writel,
 326     ioapic_mem_writel,
 327 };
 328
 329 static int ioapic_init1(SysBusDevice *dev)
 330 {
 331     IOAPICState *s = FROM_SYSBUS(IOAPICState, dev);
 332     int io_memory;
 333
 334     io_memory = cpu_register_io_memory(ioapic_mem_read,
 335                                        ioapic_mem_write, s);
 336     sysbus_init_mmio(dev, 0x1000, io_memory);
 337
 338     qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
 339
 340     return 0;
 341 }
 342
 343 static SysBusDeviceInfo ioapic_info = {
 344     .init = ioapic_init1,
 345     .qdev.name = "ioapic",
 346     .qdev.size = sizeof(IOAPICState),
 347     .qdev.vmsd = &vmstate_ioapic,
 348     .qdev.reset = ioapic_reset,
 349     .qdev.no_user = 1,
 350 };
 351
 352 static void ioapic_register_devices(void)
 353 {
 354     sysbus_register_withprop(&ioapic_info);
 355 }
 356
 357 device_init(ioapic_register_devices)