hw/realview.c

   1 /*
   2  * ARM RealView Baseboard System emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "arm-misc.h"
  12 #include "primecell.h"
  13 #include "devices.h"
  14 #include "pci.h"
  15 #include "usb-ohci.h"
  16 #include "net.h"
  17 #include "sysemu.h"
  18 #include "boards.h"
  19 #include "bitbang_i2c.h"
  20 #include "sysbus.h"
  21 #include "blockdev.h"
  22
  23 #define SMP_BOOT_ADDR 0xe0000000
  24
  25 typedef struct {
  26     SysBusDevice busdev;
  27     bitbang_i2c_interface *bitbang;
  28     int out;
  29     int in;
  30 } RealViewI2CState;
  31
  32 static uint32_t realview_i2c_read(void *opaque, target_phys_addr_t offset)
  33 {
  34     RealViewI2CState *s = (RealViewI2CState *)opaque;
  35
  36     if (offset == 0) {
  37         return (s->out & 1) | (s->in << 1);
  38     } else {
  39         hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset);
  40         return -1;
  41     }
  42 }
  43
  44 static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
  45                                uint32_t value)
  46 {
  47     RealViewI2CState *s = (RealViewI2CState *)opaque;
  48
  49     switch (offset) {
  50     case 0:
  51         s->out |= value & 3;
  52         break;
  53     case 4:
  54         s->out &= ~value;
  55         break;
  56     default:
  57         hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset);
  58     }
  59     bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
  60     s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
  61 }
  62
  63 static CPUReadMemoryFunc * const realview_i2c_readfn[] = {
  64    realview_i2c_read,
  65    realview_i2c_read,
  66    realview_i2c_read
  67 };
  68
  69 static CPUWriteMemoryFunc * const realview_i2c_writefn[] = {
  70    realview_i2c_write,
  71    realview_i2c_write,
  72    realview_i2c_write
  73 };
  74
  75 static int realview_i2c_init(SysBusDevice *dev)
  76 {
  77     RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);
  78     i2c_bus *bus;
  79     int iomemtype;
  80
  81     bus = i2c_init_bus(&dev->qdev, "i2c");
  82     s->bitbang = bitbang_i2c_init(bus);
  83     iomemtype = cpu_register_io_memory(realview_i2c_readfn,
  84                                        realview_i2c_writefn, s);
  85     sysbus_init_mmio(dev, 0x1000, iomemtype);
  86     return 0;
  87 }
  88
  89 static SysBusDeviceInfo realview_i2c_info = {
  90     .init = realview_i2c_init,
  91     .qdev.name  = "realview_i2c",
  92     .qdev.size  = sizeof(RealViewI2CState),
  93 };
  94
  95 static void realview_register_devices(void)
  96 {
  97     sysbus_register_withprop(&realview_i2c_info);
  98 }
  99
 100 /* Board init.  */
 101
 102 static struct arm_boot_info realview_binfo = {
 103     .smp_loader_start = SMP_BOOT_ADDR,
 104 };
 105
 106 static void secondary_cpu_reset(void *opaque)
 107 {
 108   CPUState *env = opaque;
 109
 110   cpu_reset(env);
 111   /* Set entry point for secondary CPUs.  This assumes we're using
 112      the init code from arm_boot.c.  Real hardware resets all CPUs
 113      the same.  */
 114   env->regs[15] = SMP_BOOT_ADDR;
 115 }
 116
 117 /* The following two lists must be consistent.  */
 118 enum realview_board_type {
 119     BOARD_EB,
 120     BOARD_EB_MPCORE,
 121     BOARD_PB_A8,
 122     BOARD_PBX_A9,
 123 };
 124
 125 static const int realview_board_id[] = {
 126     0x33b,
 127     0x33b,
 128     0x769,
 129     0x76d
 130 };
 131
 132 static void realview_init(ram_addr_t ram_size,
 133                      const char *boot_device,
 134                      const char *kernel_filename, const char *kernel_cmdline,
 135                      const char *initrd_filename, const char *cpu_model,
 136                      enum realview_board_type board_type)
 137 {
 138     CPUState *env = NULL;
 139     ram_addr_t ram_offset;
 140     DeviceState *dev;
 141     SysBusDevice *busdev;
 142     qemu_irq *irqp;
 143     qemu_irq pic[64];
 144     PCIBus *pci_bus;
 145     NICInfo *nd;
 146     i2c_bus *i2c;
 147     int n;
 148     int done_nic = 0;
 149     qemu_irq cpu_irq[4];
 150     int is_mpcore = 0;
 151     int is_pb = 0;
 152     uint32_t proc_id = 0;
 153     uint32_t sys_id;
 154     ram_addr_t low_ram_size;
 155
 156     switch (board_type) {
 157     case BOARD_EB:
 158         break;
 159     case BOARD_EB_MPCORE:
 160         is_mpcore = 1;
 161         break;
 162     case BOARD_PB_A8:
 163         is_pb = 1;
 164         break;
 165     case BOARD_PBX_A9:
 166         is_mpcore = 1;
 167         is_pb = 1;
 168         break;
 169     }
 170     for (n = 0; n < smp_cpus; n++) {
 171         env = cpu_init(cpu_model);
 172         if (!env) {
 173             fprintf(stderr, "Unable to find CPU definition\n");
 174             exit(1);
 175         }
 176         irqp = arm_pic_init_cpu(env);
 177         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 178         if (n > 0) {
 179             qemu_register_reset(secondary_cpu_reset, env);
 180         }
 181     }
 182     if (arm_feature(env, ARM_FEATURE_V7)) {
 183         if (is_mpcore) {
 184             proc_id = 0x0c000000;
 185         } else {
 186             proc_id = 0x0e000000;
 187         }
 188     } else if (arm_feature(env, ARM_FEATURE_V6K)) {
 189         proc_id = 0x06000000;
 190     } else if (arm_feature(env, ARM_FEATURE_V6)) {
 191         proc_id = 0x04000000;
 192     } else {
 193         proc_id = 0x02000000;
 194     }
 195
 196     if (is_pb && ram_size > 0x20000000) {
 197         /* Core tile RAM.  */
 198         low_ram_size = ram_size - 0x20000000;
 199         ram_size = 0x20000000;
 200         ram_offset = qemu_ram_alloc(NULL, "realview.lowmem", low_ram_size);
 201         cpu_register_physical_memory(0x20000000, low_ram_size,
 202                                      ram_offset | IO_MEM_RAM);
 203     }
 204
 205     ram_offset = qemu_ram_alloc(NULL, "realview.highmem", ram_size);
 206     low_ram_size = ram_size;
 207     if (low_ram_size > 0x10000000)
 208       low_ram_size = 0x10000000;
 209     /* SDRAM at address zero.  */
 210     cpu_register_physical_memory(0, low_ram_size, ram_offset | IO_MEM_RAM);
 211     if (is_pb) {
 212         /* And again at a high address.  */
 213         cpu_register_physical_memory(0x70000000, ram_size,
 214                                      ram_offset | IO_MEM_RAM);
 215     } else {
 216         ram_size = low_ram_size;
 217     }
 218
 219     sys_id = is_pb ? 0x01780500 : 0xc1400400;
 220     arm_sysctl_init(0x10000000, sys_id, proc_id);
 221
 222     if (is_mpcore) {
 223         dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
 224         qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 225         qdev_init_nofail(dev);
 226         busdev = sysbus_from_qdev(dev);
 227         if (is_pb) {
 228             realview_binfo.smp_priv_base = 0x1f000000;
 229         } else {
 230             realview_binfo.smp_priv_base = 0x10100000;
 231         }
 232         sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base);
 233         for (n = 0; n < smp_cpus; n++) {
 234             sysbus_connect_irq(busdev, n, cpu_irq[n]);
 235         }
 236     } else {
 237         uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
 238         /* For now just create the nIRQ GIC, and ignore the others.  */
 239         dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
 240     }
 241     for (n = 0; n < 64; n++) {
 242         pic[n] = qdev_get_gpio_in(dev, n);
 243     }
 244
 245     sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
 246     sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
 247
 248     sysbus_create_simple("pl011", 0x10009000, pic[12]);
 249     sysbus_create_simple("pl011", 0x1000a000, pic[13]);
 250     sysbus_create_simple("pl011", 0x1000b000, pic[14]);
 251     sysbus_create_simple("pl011", 0x1000c000, pic[15]);
 252
 253     /* DMA controller is optional, apparently.  */
 254     sysbus_create_simple("pl081", 0x10030000, pic[24]);
 255
 256     sysbus_create_simple("sp804", 0x10011000, pic[4]);
 257     sysbus_create_simple("sp804", 0x10012000, pic[5]);
 258
 259     sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);
 260
 261     sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
 262
 263     sysbus_create_simple("pl031", 0x10017000, pic[10]);
 264
 265     if (!is_pb) {
 266         dev = sysbus_create_varargs("realview_pci", 0x60000000,
 267                                     pic[48], pic[49], pic[50], pic[51], NULL);
 268         pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 269         if (usb_enabled) {
 270             usb_ohci_init_pci(pci_bus, -1);
 271         }
 272         n = drive_get_max_bus(IF_SCSI);
 273         while (n >= 0) {
 274             pci_create_simple(pci_bus, -1, "lsi53c895a");
 275             n--;
 276         }
 277     }
 278     for(n = 0; n < nb_nics; n++) {
 279         nd = &nd_table[n];
 280
 281         if ((!nd->model && !done_nic)
 282             || strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0) {
 283             if (is_pb) {
 284                 lan9118_init(nd, 0x4e000000, pic[28]);
 285             } else {
 286                 smc91c111_init(nd, 0x4e000000, pic[28]);
 287             }
 288             done_nic = 1;
 289         } else {
 290             pci_nic_init_nofail(nd, "rtl8139", NULL);
 291         }
 292     }
 293
 294     dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL);
 295     i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
 296     i2c_create_slave(i2c, "ds1338", 0x68);
 297
 298     /* Memory map for RealView Emulation Baseboard:  */
 299     /* 0x10000000 System registers.  */
 300     /*  0x10001000 System controller.  */
 301     /* 0x10002000 Two-Wire Serial Bus.  */
 302     /* 0x10003000 Reserved.  */
 303     /*  0x10004000 AACI.  */
 304     /*  0x10005000 MCI.  */
 305     /* 0x10006000 KMI0.  */
 306     /* 0x10007000 KMI1.  */
 307     /*  0x10008000 Character LCD. (EB) */
 308     /* 0x10009000 UART0.  */
 309     /* 0x1000a000 UART1.  */
 310     /* 0x1000b000 UART2.  */
 311     /* 0x1000c000 UART3.  */
 312     /*  0x1000d000 SSPI.  */
 313     /*  0x1000e000 SCI.  */
 314     /* 0x1000f000 Reserved.  */
 315     /*  0x10010000 Watchdog.  */
 316     /* 0x10011000 Timer 0+1.  */
 317     /* 0x10012000 Timer 2+3.  */
 318     /*  0x10013000 GPIO 0.  */
 319     /*  0x10014000 GPIO 1.  */
 320     /*  0x10015000 GPIO 2.  */
 321     /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
 322     /* 0x10017000 RTC.  */
 323     /*  0x10018000 DMC.  */
 324     /*  0x10019000 PCI controller config.  */
 325     /*  0x10020000 CLCD.  */
 326     /* 0x10030000 DMA Controller.  */
 327     /* 0x10040000 GIC1. (EB) */
 328     /*  0x10050000 GIC2. (EB) */
 329     /*  0x10060000 GIC3. (EB) */
 330     /*  0x10070000 GIC4. (EB) */
 331     /*  0x10080000 SMC.  */
 332     /* 0x1e000000 GIC1. (PB) */
 333     /*  0x1e001000 GIC2. (PB) */
 334     /*  0x1e002000 GIC3. (PB) */
 335     /*  0x1e003000 GIC4. (PB) */
 336     /*  0x40000000 NOR flash.  */
 337     /*  0x44000000 DoC flash.  */
 338     /*  0x48000000 SRAM.  */
 339     /*  0x4c000000 Configuration flash.  */
 340     /* 0x4e000000 Ethernet.  */
 341     /*  0x4f000000 USB.  */
 342     /*  0x50000000 PISMO.  */
 343     /*  0x54000000 PISMO.  */
 344     /*  0x58000000 PISMO.  */
 345     /*  0x5c000000 PISMO.  */
 346     /* 0x60000000 PCI.  */
 347     /* 0x61000000 PCI Self Config.  */
 348     /* 0x62000000 PCI Config.  */
 349     /* 0x63000000 PCI IO.  */
 350     /* 0x64000000 PCI mem 0.  */
 351     /* 0x68000000 PCI mem 1.  */
 352     /* 0x6c000000 PCI mem 2.  */
 353
 354     /* ??? Hack to map an additional page of ram for the secondary CPU
 355        startup code.  I guess this works on real hardware because the
 356        BootROM happens to be in ROM/flash or in memory that isn't clobbered
 357        until after Linux boots the secondary CPUs.  */
 358     ram_offset = qemu_ram_alloc(NULL, "realview.hack", 0x1000);
 359     cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
 360                                  ram_offset | IO_MEM_RAM);
 361
 362     realview_binfo.ram_size = ram_size;
 363     realview_binfo.kernel_filename = kernel_filename;
 364     realview_binfo.kernel_cmdline = kernel_cmdline;
 365     realview_binfo.initrd_filename = initrd_filename;
 366     realview_binfo.nb_cpus = smp_cpus;
 367     realview_binfo.board_id = realview_board_id[board_type];
 368     realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
 369     arm_load_kernel(first_cpu, &realview_binfo);
 370 }
 371
 372 static void realview_eb_init(ram_addr_t ram_size,
 373                      const char *boot_device,
 374                      const char *kernel_filename, const char *kernel_cmdline,
 375                      const char *initrd_filename, const char *cpu_model)
 376 {
 377     if (!cpu_model) {
 378         cpu_model = "arm926";
 379     }
 380     realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
 381                   initrd_filename, cpu_model, BOARD_EB);
 382 }
 383
 384 static void realview_eb_mpcore_init(ram_addr_t ram_size,
 385                      const char *boot_device,
 386                      const char *kernel_filename, const char *kernel_cmdline,
 387                      const char *initrd_filename, const char *cpu_model)
 388 {
 389     if (!cpu_model) {
 390         cpu_model = "arm11mpcore";
 391     }
 392     realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
 393                   initrd_filename, cpu_model, BOARD_EB_MPCORE);
 394 }
 395
 396 static void realview_pb_a8_init(ram_addr_t ram_size,
 397                      const char *boot_device,
 398                      const char *kernel_filename, const char *kernel_cmdline,
 399                      const char *initrd_filename, const char *cpu_model)
 400 {
 401     if (!cpu_model) {
 402         cpu_model = "cortex-a8";
 403     }
 404     realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
 405                   initrd_filename, cpu_model, BOARD_PB_A8);
 406 }
 407
 408 static void realview_pbx_a9_init(ram_addr_t ram_size,
 409                      const char *boot_device,
 410                      const char *kernel_filename, const char *kernel_cmdline,
 411                      const char *initrd_filename, const char *cpu_model)
 412 {
 413     if (!cpu_model) {
 414         cpu_model = "cortex-a9";
 415     }
 416     realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
 417                   initrd_filename, cpu_model, BOARD_PBX_A9);
 418 }
 419
 420 static QEMUMachine realview_eb_machine = {
 421     .name = "realview-eb",
 422     .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
 423     .init = realview_eb_init,
 424     .use_scsi = 1,
 425 };
 426
 427 static QEMUMachine realview_eb_mpcore_machine = {
 428     .name = "realview-eb-mpcore",
 429     .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
 430     .init = realview_eb_mpcore_init,
 431     .use_scsi = 1,
 432     .max_cpus = 4,
 433 };
 434
 435 static QEMUMachine realview_pb_a8_machine = {
 436     .name = "realview-pb-a8",
 437     .desc = "ARM RealView Platform Baseboard for Cortex-A8",
 438     .init = realview_pb_a8_init,
 439 };
 440
 441 static QEMUMachine realview_pbx_a9_machine = {
 442     .name = "realview-pbx-a9",
 443     .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
 444     .init = realview_pbx_a9_init,
 445     .use_scsi = 1,
 446     .max_cpus = 4,
 447 };
 448
 449 static void realview_machine_init(void)
 450 {
 451     qemu_register_machine(&realview_eb_machine);
 452     qemu_register_machine(&realview_eb_mpcore_machine);
 453     qemu_register_machine(&realview_pb_a8_machine);
 454     qemu_register_machine(&realview_pbx_a9_machine);
 455 }
 456
 457 machine_init(realview_machine_init);
 458 device_init(realview_register_devices)