hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32 #include "sysbus.h"
  33 #include "mc146818rtc.h"
  34
  35 //#define HPET_DEBUG
  36 #ifdef HPET_DEBUG
  37 #define DPRINTF printf
  38 #else
  39 #define DPRINTF(...)
  40 #endif
  41
  42 #define HPET_MSI_SUPPORT        0
  43
  44 struct HPETState;
  45 typedef struct HPETTimer {  /* timers */
  46     uint8_t tn;             /*timer number*/
  47     QEMUTimer *qemu_timer;
  48     struct HPETState *state;
  49     /* Memory-mapped, software visible timer registers */
  50     uint64_t config;        /* configuration/cap */
  51     uint64_t cmp;           /* comparator */
  52     uint64_t fsb;           /* FSB route */
  53     /* Hidden register state */
  54     uint64_t period;        /* Last value written to comparator */
  55     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  56                              * mode. Next pop will be actual timer expiration.
  57                              */
  58 } HPETTimer;
  59
  60 typedef struct HPETState {
  61     SysBusDevice busdev;
  62     uint64_t hpet_offset;
  63     qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
  64     uint32_t flags;
  65     uint8_t rtc_irq_level;
  66     uint8_t num_timers;
  67     HPETTimer timer[HPET_MAX_TIMERS];
  68
  69     /* Memory-mapped, software visible registers */
  70     uint64_t capability;        /* capabilities */
  71     uint64_t config;            /* configuration */
  72     uint64_t isr;               /* interrupt status reg */
  73     uint64_t hpet_counter;      /* main counter */
  74     uint8_t  hpet_id;           /* instance id */
  75 } HPETState;
  76
  77 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  78
  79 static uint32_t hpet_in_legacy_mode(HPETState *s)
  80 {
  81     return s->config & HPET_CFG_LEGACY;
  82 }
  83
  84 static uint32_t timer_int_route(struct HPETTimer *timer)
  85 {
  86     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  87 }
  88
  89 static uint32_t timer_fsb_route(HPETTimer *t)
  90 {
  91     return t->config & HPET_TN_FSB_ENABLE;
  92 }
  93
  94 static uint32_t hpet_enabled(HPETState *s)
  95 {
  96     return s->config & HPET_CFG_ENABLE;
  97 }
  98
  99 static uint32_t timer_is_periodic(HPETTimer *t)
 100 {
 101     return t->config & HPET_TN_PERIODIC;
 102 }
 103
 104 static uint32_t timer_enabled(HPETTimer *t)
 105 {
 106     return t->config & HPET_TN_ENABLE;
 107 }
 108
 109 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
 110 {
 111     return ((int32_t)(b) - (int32_t)(a) < 0);
 112 }
 113
 114 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 115 {
 116     return ((int64_t)(b) - (int64_t)(a) < 0);
 117 }
 118
 119 static uint64_t ticks_to_ns(uint64_t value)
 120 {
 121     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 122 }
 123
 124 static uint64_t ns_to_ticks(uint64_t value)
 125 {
 126     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 127 }
 128
 129 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 130 {
 131     new &= mask;
 132     new |= old & ~mask;
 133     return new;
 134 }
 135
 136 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 137 {
 138     return (!(old & mask) && (new & mask));
 139 }
 140
 141 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 142 {
 143     return ((old & mask) && !(new & mask));
 144 }
 145
 146 static uint64_t hpet_get_ticks(HPETState *s)
 147 {
 148     return ns_to_ticks(qemu_get_clock(vm_clock) + s->hpet_offset);
 149 }
 150
 151 /*
 152  * calculate diff between comparator value and current ticks
 153  */
 154 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 155 {
 156
 157     if (t->config & HPET_TN_32BIT) {
 158         uint32_t diff, cmp;
 159
 160         cmp = (uint32_t)t->cmp;
 161         diff = cmp - (uint32_t)current;
 162         diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
 163         return (uint64_t)diff;
 164     } else {
 165         uint64_t diff, cmp;
 166
 167         cmp = t->cmp;
 168         diff = cmp - current;
 169         diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
 170         return diff;
 171     }
 172 }
 173
 174 static void update_irq(struct HPETTimer *timer, int set)
 175 {
 176     uint64_t mask;
 177     HPETState *s;
 178     int route;
 179
 180     if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
 181         /* if LegacyReplacementRoute bit is set, HPET specification requires
 182          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 183          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 184          */
 185         route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
 186     } else {
 187         route = timer_int_route(timer);
 188     }
 189     s = timer->state;
 190     mask = 1 << timer->tn;
 191     if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
 192         s->isr &= ~mask;
 193         if (!timer_fsb_route(timer)) {
 194             qemu_irq_lower(s->irqs[route]);
 195         }
 196     } else if (timer_fsb_route(timer)) {
 197         stl_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
 198     } else if (timer->config & HPET_TN_TYPE_LEVEL) {
 199         s->isr |= mask;
 200         qemu_irq_raise(s->irqs[route]);
 201     } else {
 202         s->isr &= ~mask;
 203         qemu_irq_pulse(s->irqs[route]);
 204     }
 205 }
 206
 207 static void hpet_pre_save(void *opaque)
 208 {
 209     HPETState *s = opaque;
 210
 211     /* save current counter value */
 212     s->hpet_counter = hpet_get_ticks(s);
 213 }
 214
 215 static int hpet_pre_load(void *opaque)
 216 {
 217     HPETState *s = opaque;
 218
 219     /* version 1 only supports 3, later versions will load the actual value */
 220     s->num_timers = HPET_MIN_TIMERS;
 221     return 0;
 222 }
 223
 224 static int hpet_post_load(void *opaque, int version_id)
 225 {
 226     HPETState *s = opaque;
 227
 228     /* Recalculate the offset between the main counter and guest time */
 229     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 230
 231     /* Push number of timers into capability returned via HPET_ID */
 232     s->capability &= ~HPET_ID_NUM_TIM_MASK;
 233     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 234     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 235
 236     /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
 237     s->flags &= ~(1 << HPET_MSI_SUPPORT);
 238     if (s->timer[0].config & HPET_TN_FSB_CAP) {
 239         s->flags |= 1 << HPET_MSI_SUPPORT;
 240     }
 241
 242     if (hpet_in_legacy_mode(s)) {
 243         hpet_pit_disable();
 244     }
 245
 246     return 0;
 247 }
 248
 249 static const VMStateDescription vmstate_hpet_timer = {
 250     .name = "hpet_timer",
 251     .version_id = 1,
 252     .minimum_version_id = 1,
 253     .minimum_version_id_old = 1,
 254     .fields      = (VMStateField []) {
 255         VMSTATE_UINT8(tn, HPETTimer),
 256         VMSTATE_UINT64(config, HPETTimer),
 257         VMSTATE_UINT64(cmp, HPETTimer),
 258         VMSTATE_UINT64(fsb, HPETTimer),
 259         VMSTATE_UINT64(period, HPETTimer),
 260         VMSTATE_UINT8(wrap_flag, HPETTimer),
 261         VMSTATE_TIMER(qemu_timer, HPETTimer),
 262         VMSTATE_END_OF_LIST()
 263     }
 264 };
 265
 266 static const VMStateDescription vmstate_hpet = {
 267     .name = "hpet",
 268     .version_id = 2,
 269     .minimum_version_id = 1,
 270     .minimum_version_id_old = 1,
 271     .pre_save = hpet_pre_save,
 272     .pre_load = hpet_pre_load,
 273     .post_load = hpet_post_load,
 274     .fields      = (VMStateField []) {
 275         VMSTATE_UINT64(config, HPETState),
 276         VMSTATE_UINT64(isr, HPETState),
 277         VMSTATE_UINT64(hpet_counter, HPETState),
 278         VMSTATE_UINT8_V(num_timers, HPETState, 2),
 279         VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
 280                                     vmstate_hpet_timer, HPETTimer),
 281         VMSTATE_END_OF_LIST()
 282     }
 283 };
 284
 285 /*
 286  * timer expiration callback
 287  */
 288 static void hpet_timer(void *opaque)
 289 {
 290     HPETTimer *t = opaque;
 291     uint64_t diff;
 292
 293     uint64_t period = t->period;
 294     uint64_t cur_tick = hpet_get_ticks(t->state);
 295
 296     if (timer_is_periodic(t) && period != 0) {
 297         if (t->config & HPET_TN_32BIT) {
 298             while (hpet_time_after(cur_tick, t->cmp)) {
 299                 t->cmp = (uint32_t)(t->cmp + t->period);
 300             }
 301         } else {
 302             while (hpet_time_after64(cur_tick, t->cmp)) {
 303                 t->cmp += period;
 304             }
 305         }
 306         diff = hpet_calculate_diff(t, cur_tick);
 307         qemu_mod_timer(t->qemu_timer,
 308                        qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 309     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 310         if (t->wrap_flag) {
 311             diff = hpet_calculate_diff(t, cur_tick);
 312             qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) +
 313                            (int64_t)ticks_to_ns(diff));
 314             t->wrap_flag = 0;
 315         }
 316     }
 317     update_irq(t, 1);
 318 }
 319
 320 static void hpet_set_timer(HPETTimer *t)
 321 {
 322     uint64_t diff;
 323     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 324     uint64_t cur_tick = hpet_get_ticks(t->state);
 325
 326     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 327     t->wrap_flag = 0;
 328     diff = hpet_calculate_diff(t, cur_tick);
 329
 330     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 331      * counter wraps in addition to an interrupt with comparator match.
 332      */
 333     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 334         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 335         if (wrap_diff < (uint32_t)diff) {
 336             diff = wrap_diff;
 337             t->wrap_flag = 1;
 338         }
 339     }
 340     qemu_mod_timer(t->qemu_timer,
 341                    qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 342 }
 343
 344 static void hpet_del_timer(HPETTimer *t)
 345 {
 346     qemu_del_timer(t->qemu_timer);
 347     update_irq(t, 0);
 348 }
 349
 350 #ifdef HPET_DEBUG
 351 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 352 {
 353     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 354     return 0;
 355 }
 356
 357 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 358 {
 359     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 360     return 0;
 361 }
 362 #endif
 363
 364 static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
 365 {
 366     HPETState *s = opaque;
 367     uint64_t cur_tick, index;
 368
 369     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 370     index = addr;
 371     /*address range of all TN regs*/
 372     if (index >= 0x100 && index <= 0x3ff) {
 373         uint8_t timer_id = (addr - 0x100) / 0x20;
 374         HPETTimer *timer = &s->timer[timer_id];
 375
 376         if (timer_id > s->num_timers) {
 377             DPRINTF("qemu: timer id out of range\n");
 378             return 0;
 379         }
 380
 381         switch ((addr - 0x100) % 0x20) {
 382         case HPET_TN_CFG:
 383             return timer->config;
 384         case HPET_TN_CFG + 4: // Interrupt capabilities
 385             return timer->config >> 32;
 386         case HPET_TN_CMP: // comparator register
 387             return timer->cmp;
 388         case HPET_TN_CMP + 4:
 389             return timer->cmp >> 32;
 390         case HPET_TN_ROUTE:
 391             return timer->fsb;
 392         case HPET_TN_ROUTE + 4:
 393             return timer->fsb >> 32;
 394         default:
 395             DPRINTF("qemu: invalid hpet_ram_readl\n");
 396             break;
 397         }
 398     } else {
 399         switch (index) {
 400         case HPET_ID:
 401             return s->capability;
 402         case HPET_PERIOD:
 403             return s->capability >> 32;
 404         case HPET_CFG:
 405             return s->config;
 406         case HPET_CFG + 4:
 407             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
 408             return 0;
 409         case HPET_COUNTER:
 410             if (hpet_enabled(s)) {
 411                 cur_tick = hpet_get_ticks(s);
 412             } else {
 413                 cur_tick = s->hpet_counter;
 414             }
 415             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 416             return cur_tick;
 417         case HPET_COUNTER + 4:
 418             if (hpet_enabled(s)) {
 419                 cur_tick = hpet_get_ticks(s);
 420             } else {
 421                 cur_tick = s->hpet_counter;
 422             }
 423             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 424             return cur_tick >> 32;
 425         case HPET_STATUS:
 426             return s->isr;
 427         default:
 428             DPRINTF("qemu: invalid hpet_ram_readl\n");
 429             break;
 430         }
 431     }
 432     return 0;
 433 }
 434
 435 #ifdef HPET_DEBUG
 436 static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
 437                             uint32_t value)
 438 {
 439     printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
 440            addr, value);
 441 }
 442
 443 static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
 444                             uint32_t value)
 445 {
 446     printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
 447            addr, value);
 448 }
 449 #endif
 450
 451 static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
 452                             uint32_t value)
 453 {
 454     int i;
 455     HPETState *s = opaque;
 456     uint64_t old_val, new_val, val, index;
 457
 458     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 459     index = addr;
 460     old_val = hpet_ram_readl(opaque, addr);
 461     new_val = value;
 462
 463     /*address range of all TN regs*/
 464     if (index >= 0x100 && index <= 0x3ff) {
 465         uint8_t timer_id = (addr - 0x100) / 0x20;
 466         HPETTimer *timer = &s->timer[timer_id];
 467
 468         DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
 469         if (timer_id > s->num_timers) {
 470             DPRINTF("qemu: timer id out of range\n");
 471             return;
 472         }
 473         switch ((addr - 0x100) % 0x20) {
 474         case HPET_TN_CFG:
 475             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 476             if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
 477                 update_irq(timer, 0);
 478             }
 479             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 480             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 481             if (new_val & HPET_TN_32BIT) {
 482                 timer->cmp = (uint32_t)timer->cmp;
 483                 timer->period = (uint32_t)timer->period;
 484             }
 485             if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 486                 hpet_set_timer(timer);
 487             } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 488                 hpet_del_timer(timer);
 489             }
 490             break;
 491         case HPET_TN_CFG + 4: // Interrupt capabilities
 492             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 493             break;
 494         case HPET_TN_CMP: // comparator register
 495             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
 496             if (timer->config & HPET_TN_32BIT) {
 497                 new_val = (uint32_t)new_val;
 498             }
 499             if (!timer_is_periodic(timer)
 500                 || (timer->config & HPET_TN_SETVAL)) {
 501                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 502             }
 503             if (timer_is_periodic(timer)) {
 504                 /*
 505                  * FIXME: Clamp period to reasonable min value?
 506                  * Clamp period to reasonable max value
 507                  */
 508                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 509                 timer->period =
 510                     (timer->period & 0xffffffff00000000ULL) | new_val;
 511             }
 512             timer->config &= ~HPET_TN_SETVAL;
 513             if (hpet_enabled(s)) {
 514                 hpet_set_timer(timer);
 515             }
 516             break;
 517         case HPET_TN_CMP + 4: // comparator register high order
 518             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 519             if (!timer_is_periodic(timer)
 520                 || (timer->config & HPET_TN_SETVAL)) {
 521                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 522             } else {
 523                 /*
 524                  * FIXME: Clamp period to reasonable min value?
 525                  * Clamp period to reasonable max value
 526                  */
 527                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 528                 timer->period =
 529                     (timer->period & 0xffffffffULL) | new_val << 32;
 530                 }
 531                 timer->config &= ~HPET_TN_SETVAL;
 532                 if (hpet_enabled(s)) {
 533                     hpet_set_timer(timer);
 534                 }
 535                 break;
 536         case HPET_TN_ROUTE:
 537             timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
 538             break;
 539         case HPET_TN_ROUTE + 4:
 540             timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
 541             break;
 542         default:
 543             DPRINTF("qemu: invalid hpet_ram_writel\n");
 544             break;
 545         }
 546         return;
 547     } else {
 548         switch (index) {
 549         case HPET_ID:
 550             return;
 551         case HPET_CFG:
 552             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 553             s->config = (s->config & 0xffffffff00000000ULL) | val;
 554             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 555                 /* Enable main counter and interrupt generation. */
 556                 s->hpet_offset =
 557                     ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 558                 for (i = 0; i < s->num_timers; i++) {
 559                     if ((&s->timer[i])->cmp != ~0ULL) {
 560                         hpet_set_timer(&s->timer[i]);
 561                     }
 562                 }
 563             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 564                 /* Halt main counter and disable interrupt generation. */
 565                 s->hpet_counter = hpet_get_ticks(s);
 566                 for (i = 0; i < s->num_timers; i++) {
 567                     hpet_del_timer(&s->timer[i]);
 568                 }
 569             }
 570             /* i8254 and RTC are disabled when HPET is in legacy mode */
 571             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 572                 hpet_pit_disable();
 573                 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
 574             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 575                 hpet_pit_enable();
 576                 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
 577             }
 578             break;
 579         case HPET_CFG + 4:
 580             DPRINTF("qemu: invalid HPET_CFG+4 write \n");
 581             break;
 582         case HPET_STATUS:
 583             val = new_val & s->isr;
 584             for (i = 0; i < s->num_timers; i++) {
 585                 if (val & (1 << i)) {
 586                     update_irq(&s->timer[i], 0);
 587                 }
 588             }
 589             break;
 590         case HPET_COUNTER:
 591             if (hpet_enabled(s)) {
 592                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 593             }
 594             s->hpet_counter =
 595                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 596             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 597                     value, s->hpet_counter);
 598             break;
 599         case HPET_COUNTER + 4:
 600             if (hpet_enabled(s)) {
 601                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 602             }
 603             s->hpet_counter =
 604                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 605             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 606                     value, s->hpet_counter);
 607             break;
 608         default:
 609             DPRINTF("qemu: invalid hpet_ram_writel\n");
 610             break;
 611         }
 612     }
 613 }
 614
 615 static CPUReadMemoryFunc * const hpet_ram_read[] = {
 616 #ifdef HPET_DEBUG
 617     hpet_ram_readb,
 618     hpet_ram_readw,
 619 #else
 620     NULL,
 621     NULL,
 622 #endif
 623     hpet_ram_readl,
 624 };
 625
 626 static CPUWriteMemoryFunc * const hpet_ram_write[] = {
 627 #ifdef HPET_DEBUG
 628     hpet_ram_writeb,
 629     hpet_ram_writew,
 630 #else
 631     NULL,
 632     NULL,
 633 #endif
 634     hpet_ram_writel,
 635 };
 636
 637 static void hpet_reset(DeviceState *d)
 638 {
 639     HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d));
 640     int i;
 641     static int count = 0;
 642
 643     for (i = 0; i < s->num_timers; i++) {
 644         HPETTimer *timer = &s->timer[i];
 645
 646         hpet_del_timer(timer);
 647         timer->cmp = ~0ULL;
 648         timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 649         if (s->flags & (1 << HPET_MSI_SUPPORT)) {
 650             timer->config |= HPET_TN_FSB_CAP;
 651         }
 652         /* advertise availability of ioapic inti2 */
 653         timer->config |=  0x00000004ULL << 32;
 654         timer->period = 0ULL;
 655         timer->wrap_flag = 0;
 656     }
 657
 658     s->hpet_counter = 0ULL;
 659     s->hpet_offset = 0ULL;
 660     s->config = 0ULL;
 661     if (count > 0) {
 662         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 663          * because hpet is taking over for pit here. On subsequent invocations,
 664          * hpet_reset is called due to system reset. At this point control must
 665          * be returned to pit until SW reenables hpet.
 666          */
 667         hpet_pit_enable();
 668     }
 669     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 670     hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr;
 671     count = 1;
 672 }
 673
 674 static void hpet_handle_rtc_irq(void *opaque, int n, int level)
 675 {
 676     HPETState *s = FROM_SYSBUS(HPETState, opaque);
 677
 678     s->rtc_irq_level = level;
 679     if (!hpet_in_legacy_mode(s)) {
 680         qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
 681     }
 682 }
 683
 684 static int hpet_init(SysBusDevice *dev)
 685 {
 686     HPETState *s = FROM_SYSBUS(HPETState, dev);
 687     int i, iomemtype;
 688     HPETTimer *timer;
 689
 690     if (hpet_cfg.count == UINT8_MAX) {
 691         /* first instance */
 692         hpet_cfg.count = 0;
 693     }
 694
 695     if (hpet_cfg.count == 8) {
 696         fprintf(stderr, "Only 8 instances of HPET is allowed\n");
 697         return -1;
 698     }
 699
 700     s->hpet_id = hpet_cfg.count++;
 701
 702     for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
 703         sysbus_init_irq(dev, &s->irqs[i]);
 704     }
 705
 706     if (s->num_timers < HPET_MIN_TIMERS) {
 707         s->num_timers = HPET_MIN_TIMERS;
 708     } else if (s->num_timers > HPET_MAX_TIMERS) {
 709         s->num_timers = HPET_MAX_TIMERS;
 710     }
 711     for (i = 0; i < HPET_MAX_TIMERS; i++) {
 712         timer = &s->timer[i];
 713         timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
 714         timer->tn = i;
 715         timer->state = s;
 716     }
 717
 718     /* 64-bit main counter; LegacyReplacementRoute. */
 719     s->capability = 0x8086a001ULL;
 720     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 721     s->capability |= ((HPET_CLK_PERIOD) << 32);
 722
 723     isa_reserve_irq(RTC_ISA_IRQ);
 724     qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
 725
 726     /* HPET Area */
 727     iomemtype = cpu_register_io_memory(hpet_ram_read,
 728                                        hpet_ram_write, s);
 729     sysbus_init_mmio(dev, 0x400, iomemtype);
 730     return 0;
 731 }
 732
 733 static SysBusDeviceInfo hpet_device_info = {
 734     .qdev.name    = "hpet",
 735     .qdev.size    = sizeof(HPETState),
 736     .qdev.no_user = 1,
 737     .qdev.vmsd    = &vmstate_hpet,
 738     .qdev.reset   = hpet_reset,
 739     .init         = hpet_init,
 740     .qdev.props = (Property[]) {
 741         DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
 742         DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
 743         DEFINE_PROP_END_OF_LIST(),
 744     },
 745 };
 746
 747 static void hpet_register_device(void)
 748 {
 749     sysbus_register_withprop(&hpet_device_info);
 750 }
 751
 752 device_init(hpet_register_device)