hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "apic.h"
  21 #include "qemu-timer.h"
  22 #include "host-utils.h"
  23 #include "sysbus.h"
  24 #include "trace.h"
  25 #include "kvm.h"
  26
  27 /* APIC Local Vector Table */
  28 #define APIC_LVT_TIMER   0
  29 #define APIC_LVT_THERMAL 1
  30 #define APIC_LVT_PERFORM 2
  31 #define APIC_LVT_LINT0   3
  32 #define APIC_LVT_LINT1   4
  33 #define APIC_LVT_ERROR   5
  34 #define APIC_LVT_NB      6
  35
  36 /* APIC delivery modes */
  37 #define APIC_DM_FIXED   0
  38 #define APIC_DM_LOWPRI  1
  39 #define APIC_DM_SMI     2
  40 #define APIC_DM_NMI     4
  41 #define APIC_DM_INIT    5
  42 #define APIC_DM_SIPI    6
  43 #define APIC_DM_EXTINT  7
  44
  45 /* APIC destination mode */
  46 #define APIC_DESTMODE_FLAT      0xf
  47 #define APIC_DESTMODE_CLUSTER   1
  48
  49 #define APIC_TRIGGER_EDGE  0
  50 #define APIC_TRIGGER_LEVEL 1
  51
  52 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  53 #define APIC_LVT_MASKED                 (1<<16)
  54 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  55 #define APIC_LVT_REMOTE_IRR             (1<<14)
  56 #define APIC_INPUT_POLARITY             (1<<13)
  57 #define APIC_SEND_PENDING               (1<<12)
  58
  59 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  60
  61 #define APIC_SV_ENABLE (1 << 8)
  62
  63 #define MAX_APICS 255
  64 #define MAX_APIC_WORDS 8
  65
  66 /* Intel APIC constants: from include/asm/msidef.h */
  67 #define MSI_DATA_VECTOR_SHIFT           0
  68 #define MSI_DATA_VECTOR_MASK            0x000000ff
  69 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  70 #define MSI_DATA_TRIGGER_SHIFT          15
  71 #define MSI_DATA_LEVEL_SHIFT            14
  72 #define MSI_ADDR_DEST_MODE_SHIFT        2
  73 #define MSI_ADDR_DEST_ID_SHIFT          12
  74 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  75
  76 #define MSI_ADDR_SIZE                   0x100000
  77
  78 typedef struct APICState APICState;
  79
  80 struct APICState {
  81     SysBusDevice busdev;
  82     void *cpu_env;
  83     uint32_t apicbase;
  84     uint8_t id;
  85     uint8_t arb_id;
  86     uint8_t tpr;
  87     uint32_t spurious_vec;
  88     uint8_t log_dest;
  89     uint8_t dest_mode;
  90     uint32_t isr[8];  /* in service register */
  91     uint32_t tmr[8];  /* trigger mode register */
  92     uint32_t irr[8]; /* interrupt request register */
  93     uint32_t lvt[APIC_LVT_NB];
  94     uint32_t esr; /* error register */
  95     uint32_t icr[2];
  96
  97     uint32_t divide_conf;
  98     int count_shift;
  99     uint32_t initial_count;
 100     int64_t initial_count_load_time, next_time;
 101     uint32_t idx;
 102     QEMUTimer *timer;
 103     int sipi_vector;
 104     int wait_for_sipi;
 105 };
 106
 107 static APICState *local_apics[MAX_APICS + 1];
 108 static int apic_irq_delivered;
 109
 110 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 111 static void apic_update_irq(APICState *s);
 112 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 113                                       uint8_t dest, uint8_t dest_mode);
 114
 115 /* Find first bit starting from msb */
 116 static int fls_bit(uint32_t value)
 117 {
 118     return 31 - clz32(value);
 119 }
 120
 121 /* Find first bit starting from lsb */
 122 static int ffs_bit(uint32_t value)
 123 {
 124     return ctz32(value);
 125 }
 126
 127 static inline void set_bit(uint32_t *tab, int index)
 128 {
 129     int i, mask;
 130     i = index >> 5;
 131     mask = 1 << (index & 0x1f);
 132     tab[i] |= mask;
 133 }
 134
 135 static inline void reset_bit(uint32_t *tab, int index)
 136 {
 137     int i, mask;
 138     i = index >> 5;
 139     mask = 1 << (index & 0x1f);
 140     tab[i] &= ~mask;
 141 }
 142
 143 static inline int get_bit(uint32_t *tab, int index)
 144 {
 145     int i, mask;
 146     i = index >> 5;
 147     mask = 1 << (index & 0x1f);
 148     return !!(tab[i] & mask);
 149 }
 150
 151 static void apic_local_deliver(APICState *s, int vector)
 152 {
 153     uint32_t lvt = s->lvt[vector];
 154     int trigger_mode;
 155
 156     trace_apic_local_deliver(vector, (lvt >> 8) & 7);
 157
 158     if (lvt & APIC_LVT_MASKED)
 159         return;
 160
 161     switch ((lvt >> 8) & 7) {
 162     case APIC_DM_SMI:
 163         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
 164         break;
 165
 166     case APIC_DM_NMI:
 167         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
 168         break;
 169
 170     case APIC_DM_EXTINT:
 171         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 172         break;
 173
 174     case APIC_DM_FIXED:
 175         trigger_mode = APIC_TRIGGER_EDGE;
 176         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 177             (lvt & APIC_LVT_LEVEL_TRIGGER))
 178             trigger_mode = APIC_TRIGGER_LEVEL;
 179         apic_set_irq(s, lvt & 0xff, trigger_mode);
 180     }
 181 }
 182
 183 void apic_deliver_pic_intr(DeviceState *d, int level)
 184 {
 185     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 186
 187     if (level) {
 188         apic_local_deliver(s, APIC_LVT_LINT0);
 189     } else {
 190         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 191
 192         switch ((lvt >> 8) & 7) {
 193         case APIC_DM_FIXED:
 194             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 195                 break;
 196             reset_bit(s->irr, lvt & 0xff);
 197             /* fall through */
 198         case APIC_DM_EXTINT:
 199             cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 200             break;
 201         }
 202     }
 203 }
 204
 205 #define foreach_apic(apic, deliver_bitmask, code) \
 206 {\
 207     int __i, __j, __mask;\
 208     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 209         __mask = deliver_bitmask[__i];\
 210         if (__mask) {\
 211             for(__j = 0; __j < 32; __j++) {\
 212                 if (__mask & (1 << __j)) {\
 213                     apic = local_apics[__i * 32 + __j];\
 214                     if (apic) {\
 215                         code;\
 216                     }\
 217                 }\
 218             }\
 219         }\
 220     }\
 221 }
 222
 223 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 224                              uint8_t delivery_mode,
 225                              uint8_t vector_num, uint8_t polarity,
 226                              uint8_t trigger_mode)
 227 {
 228     APICState *apic_iter;
 229
 230     switch (delivery_mode) {
 231         case APIC_DM_LOWPRI:
 232             /* XXX: search for focus processor, arbitration */
 233             {
 234                 int i, d;
 235                 d = -1;
 236                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 237                     if (deliver_bitmask[i]) {
 238                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 239                         break;
 240                     }
 241                 }
 242                 if (d >= 0) {
 243                     apic_iter = local_apics[d];
 244                     if (apic_iter) {
 245                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 246                     }
 247                 }
 248             }
 249             return;
 250
 251         case APIC_DM_FIXED:
 252             break;
 253
 254         case APIC_DM_SMI:
 255             foreach_apic(apic_iter, deliver_bitmask,
 256                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 257             return;
 258
 259         case APIC_DM_NMI:
 260             foreach_apic(apic_iter, deliver_bitmask,
 261                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 262             return;
 263
 264         case APIC_DM_INIT:
 265             /* normal INIT IPI sent to processors */
 266             foreach_apic(apic_iter, deliver_bitmask,
 267                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 268             return;
 269
 270         case APIC_DM_EXTINT:
 271             /* handled in I/O APIC code */
 272             break;
 273
 274         default:
 275             return;
 276     }
 277
 278     foreach_apic(apic_iter, deliver_bitmask,
 279                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 280 }
 281
 282 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 283                       uint8_t delivery_mode, uint8_t vector_num,
 284                       uint8_t polarity, uint8_t trigger_mode)
 285 {
 286     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 287
 288     trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
 289                            polarity, trigger_mode);
 290
 291     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 292     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 293                      trigger_mode);
 294 }
 295
 296 void cpu_set_apic_base(DeviceState *d, uint64_t val)
 297 {
 298     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 299
 300     trace_cpu_set_apic_base(val);
 301
 302     if (!s)
 303         return;
 304     if (kvm_enabled() && kvm_irqchip_in_kernel())
 305         s->apicbase = val;
 306     else
 307         s->apicbase = (val & 0xfffff000) |
 308             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 309     /* if disabled, cannot be enabled again */
 310     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 311         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 312         cpu_clear_apic_feature(s->cpu_env);
 313         s->spurious_vec &= ~APIC_SV_ENABLE;
 314     }
 315 }
 316
 317 uint64_t cpu_get_apic_base(DeviceState *d)
 318 {
 319     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 320
 321     trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
 322
 323     return s ? s->apicbase : 0;
 324 }
 325
 326 void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
 327 {
 328     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 329
 330     if (!s)
 331         return;
 332     s->tpr = (val & 0x0f) << 4;
 333     apic_update_irq(s);
 334 }
 335
 336 uint8_t cpu_get_apic_tpr(DeviceState *d)
 337 {
 338     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 339
 340     return s ? s->tpr >> 4 : 0;
 341 }
 342
 343 /* return -1 if no bit is set */
 344 static int get_highest_priority_int(uint32_t *tab)
 345 {
 346     int i;
 347     for(i = 7; i >= 0; i--) {
 348         if (tab[i] != 0) {
 349             return i * 32 + fls_bit(tab[i]);
 350         }
 351     }
 352     return -1;
 353 }
 354
 355 static int apic_get_ppr(APICState *s)
 356 {
 357     int tpr, isrv, ppr;
 358
 359     tpr = (s->tpr >> 4);
 360     isrv = get_highest_priority_int(s->isr);
 361     if (isrv < 0)
 362         isrv = 0;
 363     isrv >>= 4;
 364     if (tpr >= isrv)
 365         ppr = s->tpr;
 366     else
 367         ppr = isrv << 4;
 368     return ppr;
 369 }
 370
 371 static int apic_get_arb_pri(APICState *s)
 372 {
 373     /* XXX: arbitration */
 374     return 0;
 375 }
 376
 377 /* signal the CPU if an irq is pending */
 378 static void apic_update_irq(APICState *s)
 379 {
 380     int irrv, ppr;
 381     if (!(s->spurious_vec & APIC_SV_ENABLE))
 382         return;
 383     irrv = get_highest_priority_int(s->irr);
 384     if (irrv < 0)
 385         return;
 386     ppr = apic_get_ppr(s);
 387     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 388         return;
 389     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 390 }
 391
 392 void apic_reset_irq_delivered(void)
 393 {
 394     trace_apic_reset_irq_delivered(apic_irq_delivered);
 395
 396     apic_irq_delivered = 0;
 397 }
 398
 399 int apic_get_irq_delivered(void)
 400 {
 401     trace_apic_get_irq_delivered(apic_irq_delivered);
 402
 403     return apic_irq_delivered;
 404 }
 405
 406 void apic_set_irq_delivered(void)
 407 {
 408     apic_irq_delivered = 1;
 409 }
 410
 411 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 412 {
 413     apic_irq_delivered += !get_bit(s->irr, vector_num);
 414
 415     trace_apic_set_irq(apic_irq_delivered);
 416
 417     set_bit(s->irr, vector_num);
 418     if (trigger_mode)
 419         set_bit(s->tmr, vector_num);
 420     else
 421         reset_bit(s->tmr, vector_num);
 422     apic_update_irq(s);
 423 }
 424
 425 static void apic_eoi(APICState *s)
 426 {
 427     int isrv;
 428     isrv = get_highest_priority_int(s->isr);
 429     if (isrv < 0)
 430         return;
 431     reset_bit(s->isr, isrv);
 432     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 433             set the remote IRR bit for level triggered interrupts. */
 434     apic_update_irq(s);
 435 }
 436
 437 static int apic_find_dest(uint8_t dest)
 438 {
 439     APICState *apic = local_apics[dest];
 440     int i;
 441
 442     if (apic && apic->id == dest)
 443         return dest;  /* shortcut in case apic->id == apic->idx */
 444
 445     for (i = 0; i < MAX_APICS; i++) {
 446         apic = local_apics[i];
 447         if (apic && apic->id == dest)
 448             return i;
 449     }
 450
 451     return -1;
 452 }
 453
 454 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 455                                       uint8_t dest, uint8_t dest_mode)
 456 {
 457     APICState *apic_iter;
 458     int i;
 459
 460     if (dest_mode == 0) {
 461         if (dest == 0xff) {
 462             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 463         } else {
 464             int idx = apic_find_dest(dest);
 465             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 466             if (idx >= 0)
 467                 set_bit(deliver_bitmask, idx);
 468         }
 469     } else {
 470         /* XXX: cluster mode */
 471         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 472         for(i = 0; i < MAX_APICS; i++) {
 473             apic_iter = local_apics[i];
 474             if (apic_iter) {
 475                 if (apic_iter->dest_mode == 0xf) {
 476                     if (dest & apic_iter->log_dest)
 477                         set_bit(deliver_bitmask, i);
 478                 } else if (apic_iter->dest_mode == 0x0) {
 479                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 480                         (dest & apic_iter->log_dest & 0x0f)) {
 481                         set_bit(deliver_bitmask, i);
 482                     }
 483                 }
 484             }
 485         }
 486     }
 487 }
 488
 489 void apic_init_reset(DeviceState *d)
 490 {
 491     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 492     int i;
 493
 494     if (!s)
 495         return;
 496
 497     s->tpr = 0;
 498     s->spurious_vec = 0xff;
 499     s->log_dest = 0;
 500     s->dest_mode = 0xf;
 501     memset(s->isr, 0, sizeof(s->isr));
 502     memset(s->tmr, 0, sizeof(s->tmr));
 503     memset(s->irr, 0, sizeof(s->irr));
 504     for(i = 0; i < APIC_LVT_NB; i++)
 505         s->lvt[i] = 1 << 16; /* mask LVT */
 506     s->esr = 0;
 507     memset(s->icr, 0, sizeof(s->icr));
 508     s->divide_conf = 0;
 509     s->count_shift = 0;
 510     s->initial_count = 0;
 511     s->initial_count_load_time = 0;
 512     s->next_time = 0;
 513     s->wait_for_sipi = 1;
 514 }
 515
 516 static void apic_startup(APICState *s, int vector_num)
 517 {
 518     s->sipi_vector = vector_num;
 519     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 520 }
 521
 522 void apic_sipi(DeviceState *d)
 523 {
 524     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 525
 526     cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 527
 528     if (!s->wait_for_sipi)
 529         return;
 530     cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
 531     s->wait_for_sipi = 0;
 532 }
 533
 534 static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
 535                          uint8_t delivery_mode, uint8_t vector_num,
 536                          uint8_t polarity, uint8_t trigger_mode)
 537 {
 538     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 539     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 540     int dest_shorthand = (s->icr[0] >> 18) & 3;
 541     APICState *apic_iter;
 542
 543     switch (dest_shorthand) {
 544     case 0:
 545         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 546         break;
 547     case 1:
 548         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 549         set_bit(deliver_bitmask, s->idx);
 550         break;
 551     case 2:
 552         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 553         break;
 554     case 3:
 555         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 556         reset_bit(deliver_bitmask, s->idx);
 557         break;
 558     }
 559
 560     switch (delivery_mode) {
 561         case APIC_DM_INIT:
 562             {
 563                 int trig_mode = (s->icr[0] >> 15) & 1;
 564                 int level = (s->icr[0] >> 14) & 1;
 565                 if (level == 0 && trig_mode == 1) {
 566                     foreach_apic(apic_iter, deliver_bitmask,
 567                                  apic_iter->arb_id = apic_iter->id );
 568                     return;
 569                 }
 570             }
 571             break;
 572
 573         case APIC_DM_SIPI:
 574             foreach_apic(apic_iter, deliver_bitmask,
 575                          apic_startup(apic_iter, vector_num) );
 576             return;
 577     }
 578
 579     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 580                      trigger_mode);
 581 }
 582
 583 int apic_get_interrupt(DeviceState *d)
 584 {
 585     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 586     int intno;
 587
 588     /* if the APIC is installed or enabled, we let the 8259 handle the
 589        IRQs */
 590     if (!s)
 591         return -1;
 592     if (!(s->spurious_vec & APIC_SV_ENABLE))
 593         return -1;
 594
 595     /* XXX: spurious IRQ handling */
 596     intno = get_highest_priority_int(s->irr);
 597     if (intno < 0)
 598         return -1;
 599     if (s->tpr && intno <= s->tpr)
 600         return s->spurious_vec & 0xff;
 601     reset_bit(s->irr, intno);
 602     set_bit(s->isr, intno);
 603     apic_update_irq(s);
 604     return intno;
 605 }
 606
 607 int apic_accept_pic_intr(DeviceState *d)
 608 {
 609     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 610     uint32_t lvt0;
 611
 612     if (!s)
 613         return -1;
 614
 615     lvt0 = s->lvt[APIC_LVT_LINT0];
 616
 617     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 618         (lvt0 & APIC_LVT_MASKED) == 0)
 619         return 1;
 620
 621     return 0;
 622 }
 623
 624 static uint32_t apic_get_current_count(APICState *s)
 625 {
 626     int64_t d;
 627     uint32_t val;
 628     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 629         s->count_shift;
 630     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 631         /* periodic */
 632         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 633     } else {
 634         if (d >= s->initial_count)
 635             val = 0;
 636         else
 637             val = s->initial_count - d;
 638     }
 639     return val;
 640 }
 641
 642 static void apic_timer_update(APICState *s, int64_t current_time)
 643 {
 644     int64_t next_time, d;
 645
 646     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 647         d = (current_time - s->initial_count_load_time) >>
 648             s->count_shift;
 649         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 650             if (!s->initial_count)
 651                 goto no_timer;
 652             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 653         } else {
 654             if (d >= s->initial_count)
 655                 goto no_timer;
 656             d = (uint64_t)s->initial_count + 1;
 657         }
 658         next_time = s->initial_count_load_time + (d << s->count_shift);
 659         qemu_mod_timer(s->timer, next_time);
 660         s->next_time = next_time;
 661     } else {
 662     no_timer:
 663         qemu_del_timer(s->timer);
 664     }
 665 }
 666
 667 static void apic_timer(void *opaque)
 668 {
 669     APICState *s = opaque;
 670
 671     apic_local_deliver(s, APIC_LVT_TIMER);
 672     apic_timer_update(s, s->next_time);
 673 }
 674
 675 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 676 {
 677     return 0;
 678 }
 679
 680 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 681 {
 682     return 0;
 683 }
 684
 685 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 686 {
 687 }
 688
 689 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 690 {
 691 }
 692
 693 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 694 {
 695     DeviceState *d;
 696     APICState *s;
 697     uint32_t val;
 698     int index;
 699
 700     d = cpu_get_current_apic();
 701     if (!d) {
 702         return 0;
 703     }
 704     s = DO_UPCAST(APICState, busdev.qdev, d);
 705
 706     index = (addr >> 4) & 0xff;
 707     switch(index) {
 708     case 0x02: /* id */
 709         val = s->id << 24;
 710         break;
 711     case 0x03: /* version */
 712         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 713         break;
 714     case 0x08:
 715         val = s->tpr;
 716         break;
 717     case 0x09:
 718         val = apic_get_arb_pri(s);
 719         break;
 720     case 0x0a:
 721         /* ppr */
 722         val = apic_get_ppr(s);
 723         break;
 724     case 0x0b:
 725         val = 0;
 726         break;
 727     case 0x0d:
 728         val = s->log_dest << 24;
 729         break;
 730     case 0x0e:
 731         val = s->dest_mode << 28;
 732         break;
 733     case 0x0f:
 734         val = s->spurious_vec;
 735         break;
 736     case 0x10 ... 0x17:
 737         val = s->isr[index & 7];
 738         break;
 739     case 0x18 ... 0x1f:
 740         val = s->tmr[index & 7];
 741         break;
 742     case 0x20 ... 0x27:
 743         val = s->irr[index & 7];
 744         break;
 745     case 0x28:
 746         val = s->esr;
 747         break;
 748     case 0x30:
 749     case 0x31:
 750         val = s->icr[index & 1];
 751         break;
 752     case 0x32 ... 0x37:
 753         val = s->lvt[index - 0x32];
 754         break;
 755     case 0x38:
 756         val = s->initial_count;
 757         break;
 758     case 0x39:
 759         val = apic_get_current_count(s);
 760         break;
 761     case 0x3e:
 762         val = s->divide_conf;
 763         break;
 764     default:
 765         s->esr |= ESR_ILLEGAL_ADDRESS;
 766         val = 0;
 767         break;
 768     }
 769     trace_apic_mem_readl(addr, val);
 770     return val;
 771 }
 772
 773 static void apic_send_msi(target_phys_addr_t addr, uint32 data)
 774 {
 775     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 776     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 777     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 778     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 779     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 780     /* XXX: Ignore redirection hint. */
 781     apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
 782 }
 783
 784 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 785 {
 786     DeviceState *d;
 787     APICState *s;
 788     int index = (addr >> 4) & 0xff;
 789     if (addr > 0xfff || !index) {
 790         /* MSI and MMIO APIC are at the same memory location,
 791          * but actually not on the global bus: MSI is on PCI bus
 792          * APIC is connected directly to the CPU.
 793          * Mapping them on the global bus happens to work because
 794          * MSI registers are reserved in APIC MMIO and vice versa. */
 795         apic_send_msi(addr, val);
 796         return;
 797     }
 798
 799     d = cpu_get_current_apic();
 800     if (!d) {
 801         return;
 802     }
 803     s = DO_UPCAST(APICState, busdev.qdev, d);
 804
 805     trace_apic_mem_writel(addr, val);
 806
 807     switch(index) {
 808     case 0x02:
 809         s->id = (val >> 24);
 810         break;
 811     case 0x03:
 812         break;
 813     case 0x08:
 814         s->tpr = val;
 815         apic_update_irq(s);
 816         break;
 817     case 0x09:
 818     case 0x0a:
 819         break;
 820     case 0x0b: /* EOI */
 821         apic_eoi(s);
 822         break;
 823     case 0x0d:
 824         s->log_dest = val >> 24;
 825         break;
 826     case 0x0e:
 827         s->dest_mode = val >> 28;
 828         break;
 829     case 0x0f:
 830         s->spurious_vec = val & 0x1ff;
 831         apic_update_irq(s);
 832         break;
 833     case 0x10 ... 0x17:
 834     case 0x18 ... 0x1f:
 835     case 0x20 ... 0x27:
 836     case 0x28:
 837         break;
 838     case 0x30:
 839         s->icr[0] = val;
 840         apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 841                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 842                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 843         break;
 844     case 0x31:
 845         s->icr[1] = val;
 846         break;
 847     case 0x32 ... 0x37:
 848         {
 849             int n = index - 0x32;
 850             s->lvt[n] = val;
 851             if (n == APIC_LVT_TIMER)
 852                 apic_timer_update(s, qemu_get_clock(vm_clock));
 853         }
 854         break;
 855     case 0x38:
 856         s->initial_count = val;
 857         s->initial_count_load_time = qemu_get_clock(vm_clock);
 858         apic_timer_update(s, s->initial_count_load_time);
 859         break;
 860     case 0x39:
 861         break;
 862     case 0x3e:
 863         {
 864             int v;
 865             s->divide_conf = val & 0xb;
 866             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 867             s->count_shift = (v + 1) & 7;
 868         }
 869         break;
 870     default:
 871         s->esr |= ESR_ILLEGAL_ADDRESS;
 872         break;
 873     }
 874 }
 875
 876 #ifdef KVM_CAP_IRQCHIP
 877
 878 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 879 {
 880     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 881 }
 882
 883 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 884                                  int reg_id, uint32_t val)
 885 {
 886     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 887 }
 888
 889 static void kvm_kernel_lapic_save_to_user(APICState *s)
 890 {
 891     struct kvm_lapic_state apic;
 892     struct kvm_lapic_state *kapic = &apic;
 893     int i, v;
 894
 895     kvm_get_lapic(s->cpu_env, kapic);
 896
 897     s->id = kapic_reg(kapic, 0x2) >> 24;
 898     s->tpr = kapic_reg(kapic, 0x8);
 899     s->arb_id = kapic_reg(kapic, 0x9);
 900     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 901     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 902     s->spurious_vec = kapic_reg(kapic, 0xf);
 903     for (i = 0; i < 8; i++) {
 904         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 905         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 906         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 907     }
 908     s->esr = kapic_reg(kapic, 0x28);
 909     s->icr[0] = kapic_reg(kapic, 0x30);
 910     s->icr[1] = kapic_reg(kapic, 0x31);
 911     for (i = 0; i < APIC_LVT_NB; i++)
 912         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 913     s->initial_count = kapic_reg(kapic, 0x38);
 914     s->divide_conf = kapic_reg(kapic, 0x3e);
 915
 916     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 917     s->count_shift = (v + 1) & 7;
 918
 919     s->initial_count_load_time = qemu_get_clock(vm_clock);
 920     apic_timer_update(s, s->initial_count_load_time);
 921 }
 922
 923 static void kvm_kernel_lapic_load_from_user(APICState *s)
 924 {
 925     struct kvm_lapic_state apic;
 926     struct kvm_lapic_state *klapic = &apic;
 927     int i;
 928
 929     memset(klapic, 0, sizeof apic);
 930     kapic_set_reg(klapic, 0x2, s->id << 24);
 931     kapic_set_reg(klapic, 0x8, s->tpr);
 932     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 933     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 934     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 935     for (i = 0; i < 8; i++) {
 936         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 937         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 938         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 939     }
 940     kapic_set_reg(klapic, 0x28, s->esr);
 941     kapic_set_reg(klapic, 0x30, s->icr[0]);
 942     kapic_set_reg(klapic, 0x31, s->icr[1]);
 943     for (i = 0; i < APIC_LVT_NB; i++)
 944         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 945     kapic_set_reg(klapic, 0x38, s->initial_count);
 946     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 947
 948     kvm_set_lapic(s->cpu_env, klapic);
 949 }
 950
 951 #endif
 952
 953 void kvm_load_lapic(CPUState *env)
 954 {
 955 #ifdef KVM_CAP_IRQCHIP
 956     APICState *s = DO_UPCAST(APICState, busdev.qdev, env->apic_state);
 957
 958     if (!s) {
 959         return;
 960     }
 961
 962     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 963         kvm_kernel_lapic_load_from_user(s);
 964     }
 965 #endif
 966 }
 967
 968 void kvm_save_lapic(CPUState *env)
 969 {
 970 #ifdef KVM_CAP_IRQCHIP
 971     APICState *s = DO_UPCAST(APICState, busdev.qdev, env->apic_state);
 972
 973     if (!s) {
 974         return;
 975     }
 976
 977     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 978         kvm_kernel_lapic_save_to_user(s);
 979     }
 980 #endif
 981 }
 982
 983 /* This function is only used for old state version 1 and 2 */
 984 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 985 {
 986     APICState *s = opaque;
 987     int i;
 988
 989     if (version_id > 2)
 990         return -EINVAL;
 991
 992     /* XXX: what if the base changes? (registered memory regions) */
 993     qemu_get_be32s(f, &s->apicbase);
 994     qemu_get_8s(f, &s->id);
 995     qemu_get_8s(f, &s->arb_id);
 996     qemu_get_8s(f, &s->tpr);
 997     qemu_get_be32s(f, &s->spurious_vec);
 998     qemu_get_8s(f, &s->log_dest);
 999     qemu_get_8s(f, &s->dest_mode);
1000     for (i = 0; i < 8; i++) {
1001         qemu_get_be32s(f, &s->isr[i]);
1002         qemu_get_be32s(f, &s->tmr[i]);
1003         qemu_get_be32s(f, &s->irr[i]);
1004     }
1005     for (i = 0; i < APIC_LVT_NB; i++) {
1006         qemu_get_be32s(f, &s->lvt[i]);
1007     }
1008     qemu_get_be32s(f, &s->esr);
1009     qemu_get_be32s(f, &s->icr[0]);
1010     qemu_get_be32s(f, &s->icr[1]);
1011     qemu_get_be32s(f, &s->divide_conf);
1012     s->count_shift=qemu_get_be32(f);
1013     qemu_get_be32s(f, &s->initial_count);
1014     s->initial_count_load_time=qemu_get_be64(f);
1015     s->next_time=qemu_get_be64(f);
1016
1017     if (version_id >= 2)
1018         qemu_get_timer(f, s->timer);
1019     return 0;
1020 }
1021
1022 static const VMStateDescription vmstate_apic = {
1023     .name = "apic",
1024     .version_id = 3,
1025     .minimum_version_id = 3,
1026     .minimum_version_id_old = 1,
1027     .load_state_old = apic_load_old,
1028     .fields      = (VMStateField []) {
1029         VMSTATE_UINT32(apicbase, APICState),
1030         VMSTATE_UINT8(id, APICState),
1031         VMSTATE_UINT8(arb_id, APICState),
1032         VMSTATE_UINT8(tpr, APICState),
1033         VMSTATE_UINT32(spurious_vec, APICState),
1034         VMSTATE_UINT8(log_dest, APICState),
1035         VMSTATE_UINT8(dest_mode, APICState),
1036         VMSTATE_UINT32_ARRAY(isr, APICState, 8),
1037         VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
1038         VMSTATE_UINT32_ARRAY(irr, APICState, 8),
1039         VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
1040         VMSTATE_UINT32(esr, APICState),
1041         VMSTATE_UINT32_ARRAY(icr, APICState, 2),
1042         VMSTATE_UINT32(divide_conf, APICState),
1043         VMSTATE_INT32(count_shift, APICState),
1044         VMSTATE_UINT32(initial_count, APICState),
1045         VMSTATE_INT64(initial_count_load_time, APICState),
1046         VMSTATE_INT64(next_time, APICState),
1047         VMSTATE_TIMER(timer, APICState),
1048         VMSTATE_END_OF_LIST()
1049     }
1050 };
1051
1052 static void apic_reset(DeviceState *d)
1053 {
1054     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
1055     int bsp;
1056
1057     bsp = cpu_is_bsp(s->cpu_env);
1058     s->apicbase = 0xfee00000 |
1059         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
1060
1061     apic_init_reset(d);
1062
1063     if (bsp) {
1064         /*
1065          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1066          * time typically by BIOS, so PIC interrupt can be delivered to the
1067          * processor when local APIC is enabled.
1068          */
1069         s->lvt[APIC_LVT_LINT0] = 0x700;
1070     }
1071 }
1072
1073 static CPUReadMemoryFunc * const apic_mem_read[3] = {
1074     apic_mem_readb,
1075     apic_mem_readw,
1076     apic_mem_readl,
1077 };
1078
1079 static CPUWriteMemoryFunc * const apic_mem_write[3] = {
1080     apic_mem_writeb,
1081     apic_mem_writew,
1082     apic_mem_writel,
1083 };
1084
1085 static int apic_init1(SysBusDevice *dev)
1086 {
1087     APICState *s = FROM_SYSBUS(APICState, dev);
1088     int apic_io_memory;
1089     static int last_apic_idx;
1090
1091     if (last_apic_idx >= MAX_APICS) {
1092         return -1;
1093     }
1094     apic_io_memory = cpu_register_io_memory(apic_mem_read,
1095                                             apic_mem_write, NULL);
1096     sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
1097
1098     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1099     s->idx = last_apic_idx++;
1100     local_apics[s->idx] = s;
1101     return 0;
1102 }
1103
1104 static SysBusDeviceInfo apic_info = {
1105     .init = apic_init1,
1106     .qdev.name = "apic",
1107     .qdev.size = sizeof(APICState),
1108     .qdev.vmsd = &vmstate_apic,
1109     .qdev.reset = apic_reset,
1110     .qdev.no_user = 1,
1111     .qdev.props = (Property[]) {
1112         DEFINE_PROP_UINT8("id", APICState, id, -1),
1113         DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
1114         DEFINE_PROP_END_OF_LIST(),
1115     }
1116 };
1117
1118 static void apic_register_devices(void)
1119 {
1120     sysbus_register_withprop(&apic_info);
1121 }
1122
1123 device_init(apic_register_devices)