hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "acpi.h"
  24 #include "sysemu.h"
  25 #include "range.h"
  26
  27 //#define DEBUG
  28
  29 #ifdef DEBUG
  30 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  31 #else
  32 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  33 #endif
  34
  35 #define ACPI_DBG_IO_ADDR  0xb044
  36
  37 #define GPE_BASE 0xafe0
  38 #define PROC_BASE 0xaf00
  39 #define PCI_BASE 0xae00
  40 #define PCI_EJ_BASE 0xae08
  41
  42 #define PIIX4_CPU_HOTPLUG_STATUS 4
  43 #define PIIX4_PCI_HOTPLUG_STATUS 2
  44
  45 struct gpe_regs {
  46     uint16_t sts; /* status */
  47     uint16_t en;  /* enabled */
  48     uint8_t cpus_sts[32];
  49 };
  50
  51 struct pci_status {
  52     uint32_t up;
  53     uint32_t down;
  54 };
  55
  56 typedef struct PIIX4PMState {
  57     PCIDevice dev;
  58     uint16_t pmsts;
  59     uint16_t pmen;
  60     uint16_t pmcntrl;
  61
  62     APMState apm;
  63
  64     QEMUTimer *tmr_timer;
  65     int64_t tmr_overflow_time;
  66
  67     PMSMBus smb;
  68     uint32_t smb_io_base;
  69
  70     qemu_irq irq;
  71     qemu_irq cmos_s3;
  72     qemu_irq smi_irq;
  73     int kvm_enabled;
  74
  75     /* for pci hotplug */
  76     struct gpe_regs gpe;
  77     struct pci_status pci0_status;
  78 } PIIX4PMState;
  79
  80 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  81
  82 #define ACPI_ENABLE 0xf1
  83 #define ACPI_DISABLE 0xf0
  84
  85 static uint32_t get_pmtmr(PIIX4PMState *s)
  86 {
  87     uint32_t d;
  88     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
  89     return d & 0xffffff;
  90 }
  91
  92 static int get_pmsts(PIIX4PMState *s)
  93 {
  94     int64_t d;
  95
  96     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
  97                  get_ticks_per_sec());
  98     if (d >= s->tmr_overflow_time)
  99         s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
 100     return s->pmsts;
 101 }
 102
 103 static void pm_update_sci(PIIX4PMState *s)
 104 {
 105     int sci_level, pmsts;
 106     int64_t expire_time;
 107
 108     pmsts = get_pmsts(s);
 109     sci_level = (((pmsts & s->pmen) &
 110                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
 111                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
 112                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
 113                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
 114         (((s->gpe.sts & s->gpe.en) &
 115           (PIIX4_CPU_HOTPLUG_STATUS | PIIX4_PCI_HOTPLUG_STATUS)) != 0);
 116
 117     qemu_set_irq(s->irq, sci_level);
 118     /* schedule a timer interruption if needed */
 119     if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
 120         !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
 121         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
 122                                PM_TIMER_FREQUENCY);
 123         qemu_mod_timer(s->tmr_timer, expire_time);
 124     } else {
 125         qemu_del_timer(s->tmr_timer);
 126     }
 127 }
 128
 129 static void pm_tmr_timer(void *opaque)
 130 {
 131     PIIX4PMState *s = opaque;
 132     pm_update_sci(s);
 133 }
 134
 135 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 136 {
 137     PIIX4PMState *s = opaque;
 138     addr &= 0x3f;
 139     switch(addr) {
 140     case 0x00:
 141         {
 142             int64_t d;
 143             int pmsts;
 144             pmsts = get_pmsts(s);
 145             if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
 146                 /* if TMRSTS is reset, then compute the new overflow time */
 147                 d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
 148                              get_ticks_per_sec());
 149                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 150             }
 151             s->pmsts &= ~val;
 152             pm_update_sci(s);
 153         }
 154         break;
 155     case 0x02:
 156         s->pmen = val;
 157         pm_update_sci(s);
 158         break;
 159     case 0x04:
 160         {
 161             int sus_typ;
 162             s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
 163             if (val & ACPI_BITMASK_SLEEP_ENABLE) {
 164                 /* change suspend type */
 165                 sus_typ = (val >> 10) & 7;
 166                 switch(sus_typ) {
 167                 case 0: /* soft power off */
 168                     qemu_system_shutdown_request();
 169                     break;
 170                 case 1:
 171                     /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
 172                        Pretend that resume was caused by power button */
 173                     s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
 174                                  ACPI_BITMASK_POWER_BUTTON_STATUS);
 175                     qemu_system_reset_request();
 176                     if (s->cmos_s3) {
 177                         qemu_irq_raise(s->cmos_s3);
 178                     }
 179                 default:
 180                     break;
 181                 }
 182             }
 183         }
 184         break;
 185     default:
 186         break;
 187     }
 188     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
 189 }
 190
 191 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 192 {
 193     PIIX4PMState *s = opaque;
 194     uint32_t val;
 195
 196     addr &= 0x3f;
 197     switch(addr) {
 198     case 0x00:
 199         val = get_pmsts(s);
 200         break;
 201     case 0x02:
 202         val = s->pmen;
 203         break;
 204     case 0x04:
 205         val = s->pmcntrl;
 206         break;
 207     default:
 208         val = 0;
 209         break;
 210     }
 211     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
 212     return val;
 213 }
 214
 215 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 216 {
 217     //    PIIX4PMState *s = opaque;
 218     PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr & 0x3f, val);
 219 }
 220
 221 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 222 {
 223     PIIX4PMState *s = opaque;
 224     uint32_t val;
 225
 226     addr &= 0x3f;
 227     switch(addr) {
 228     case 0x08:
 229         val = get_pmtmr(s);
 230         break;
 231     default:
 232         val = 0;
 233         break;
 234     }
 235     PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
 236     return val;
 237 }
 238
 239 static void apm_ctrl_changed(uint32_t val, void *arg)
 240 {
 241     PIIX4PMState *s = arg;
 242
 243     /* ACPI specs 3.0, 4.7.2.5 */
 244     if (val == ACPI_ENABLE) {
 245         s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
 246     } else if (val == ACPI_DISABLE) {
 247         s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
 248     }
 249
 250     if (s->dev.config[0x5b] & (1 << 1)) {
 251         if (s->smi_irq) {
 252             qemu_irq_raise(s->smi_irq);
 253         }
 254     }
 255 }
 256
 257 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 258 {
 259     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 260 }
 261
 262 static void pm_io_space_update(PIIX4PMState *s)
 263 {
 264     uint32_t pm_io_base;
 265
 266     if (s->dev.config[0x80] & 1) {
 267         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 268         pm_io_base &= 0xffc0;
 269
 270         /* XXX: need to improve memory and ioport allocation */
 271         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 272         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 273         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 274         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 275         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 276     }
 277 }
 278
 279 static void pm_write_config(PCIDevice *d,
 280                             uint32_t address, uint32_t val, int len)
 281 {
 282     pci_default_write_config(d, address, val, len);
 283     if (range_covers_byte(address, len, 0x80))
 284         pm_io_space_update((PIIX4PMState *)d);
 285 }
 286
 287 static int vmstate_acpi_post_load(void *opaque, int version_id)
 288 {
 289     PIIX4PMState *s = opaque;
 290
 291     pm_io_space_update(s);
 292     return 0;
 293 }
 294
 295 static const VMStateDescription vmstate_gpe = {
 296     .name = "gpe",
 297     .version_id = 1,
 298     .minimum_version_id = 1,
 299     .minimum_version_id_old = 1,
 300     .fields      = (VMStateField []) {
 301         VMSTATE_UINT16(sts, struct gpe_regs),
 302         VMSTATE_UINT16(en, struct gpe_regs),
 303         VMSTATE_END_OF_LIST()
 304     }
 305 };
 306
 307 static const VMStateDescription vmstate_pci_status = {
 308     .name = "pci_status",
 309     .version_id = 1,
 310     .minimum_version_id = 1,
 311     .minimum_version_id_old = 1,
 312     .fields      = (VMStateField []) {
 313         VMSTATE_UINT32(up, struct pci_status),
 314         VMSTATE_UINT32(down, struct pci_status),
 315         VMSTATE_END_OF_LIST()
 316     }
 317 };
 318
 319 static const VMStateDescription vmstate_acpi = {
 320     .name = "piix4_pm",
 321     .version_id = 2,
 322     .minimum_version_id = 1,
 323     .minimum_version_id_old = 1,
 324     .post_load = vmstate_acpi_post_load,
 325     .fields      = (VMStateField []) {
 326         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 327         VMSTATE_UINT16(pmsts, PIIX4PMState),
 328         VMSTATE_UINT16(pmen, PIIX4PMState),
 329         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
 330         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 331         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
 332         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
 333         VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, struct gpe_regs),
 334         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 335                        struct pci_status),
 336         VMSTATE_END_OF_LIST()
 337     }
 338 };
 339
 340 static void piix4_reset(void *opaque)
 341 {
 342     PIIX4PMState *s = opaque;
 343     uint8_t *pci_conf = s->dev.config;
 344
 345     pci_conf[0x58] = 0;
 346     pci_conf[0x59] = 0;
 347     pci_conf[0x5a] = 0;
 348     pci_conf[0x5b] = 0;
 349
 350     if (s->kvm_enabled) {
 351         /* Mark SMM as already inited (until KVM supports SMM). */
 352         pci_conf[0x5B] = 0x02;
 353     }
 354 }
 355
 356 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 357 {
 358     PIIX4PMState *s = opaque;
 359
 360     if (!s) {
 361         qemu_system_shutdown_request();
 362     } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
 363         s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
 364         pm_update_sci(s);
 365     }
 366 }
 367
 368 static PIIX4PMState *global_piix4_pm_state; /* cpu hotadd */
 369
 370 static int piix4_pm_initfn(PCIDevice *dev)
 371 {
 372     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 373     uint8_t *pci_conf;
 374
 375     /* for cpu hotadd */
 376     global_piix4_pm_state = s;
 377
 378     pci_conf = s->dev.config;
 379     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 380     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 381     pci_conf[0x06] = 0x80;
 382     pci_conf[0x07] = 0x02;
 383     pci_conf[0x08] = 0x03; // revision number
 384     pci_conf[0x09] = 0x00;
 385     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 386     pci_conf[0x3d] = 0x01; // interrupt pin 1
 387
 388     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 389
 390 #if defined(TARGET_IA64)
 391     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 392     pci_conf[0x41] = 0x1f;
 393     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 394     s->pmcntrl = SCI_EN;
 395 #endif
 396
 397     /* APM */
 398     apm_init(&s->apm, apm_ctrl_changed, s);
 399
 400     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 401
 402     if (s->kvm_enabled) {
 403         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 404          * support SMM mode. */
 405         pci_conf[0x5B] = 0x02;
 406     }
 407
 408     /* XXX: which specification is used ? The i82731AB has different
 409        mappings */
 410     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 411     pci_conf[0x63] = 0x60;
 412     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 413         (serial_hds[1] != NULL ? 0x90 : 0);
 414
 415     pci_conf[0x90] = s->smb_io_base | 1;
 416     pci_conf[0x91] = s->smb_io_base >> 8;
 417     pci_conf[0xd2] = 0x09;
 418     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 419     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 420
 421     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 422
 423     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 424
 425     pm_smbus_init(&s->dev.qdev, &s->smb);
 426     qemu_register_reset(piix4_reset, s);
 427     piix4_acpi_system_hot_add_init(dev->bus, s);
 428
 429     return 0;
 430 }
 431
 432 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 433                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 434                        int kvm_enabled)
 435 {
 436     PCIDevice *dev;
 437     PIIX4PMState *s;
 438
 439     dev = pci_create(bus, devfn, "PIIX4_PM");
 440     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 441
 442     s = DO_UPCAST(PIIX4PMState, dev, dev);
 443     s->irq = sci_irq;
 444     s->cmos_s3 = cmos_s3;
 445     s->smi_irq = smi_irq;
 446     s->kvm_enabled = kvm_enabled;
 447
 448     qdev_init_nofail(&dev->qdev);
 449
 450     return s->smb.smbus;
 451 }
 452
 453 static PCIDeviceInfo piix4_pm_info = {
 454     .qdev.name          = "PIIX4_PM",
 455     .qdev.desc          = "PM",
 456     .qdev.size          = sizeof(PIIX4PMState),
 457     .qdev.vmsd          = &vmstate_acpi,
 458     .init               = piix4_pm_initfn,
 459     .config_write       = pm_write_config,
 460     .qdev.props         = (Property[]) {
 461         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 462         DEFINE_PROP_END_OF_LIST(),
 463     }
 464 };
 465
 466 static void piix4_pm_register(void)
 467 {
 468     pci_qdev_register(&piix4_pm_info);
 469 }
 470
 471 device_init(piix4_pm_register);
 472
 473 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 474 {
 475     if (addr & 1)
 476         return (val >> 8) & 0xff;
 477     return val & 0xff;
 478 }
 479
 480 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 481 {
 482     uint32_t val = 0;
 483     PIIX4PMState *s = opaque;
 484     struct gpe_regs *g = &s->gpe;
 485
 486     switch (addr) {
 487         case PROC_BASE ... PROC_BASE+31:
 488             val = g->cpus_sts[addr - PROC_BASE];
 489             break;
 490
 491         case GPE_BASE:
 492         case GPE_BASE + 1:
 493             val = gpe_read_val(g->sts, addr);
 494             break;
 495         case GPE_BASE + 2:
 496         case GPE_BASE + 3:
 497             val = gpe_read_val(g->en, addr);
 498             break;
 499         default:
 500             break;
 501     }
 502
 503     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 504     return val;
 505 }
 506
 507 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 508 {
 509     if (addr & 1)
 510         *cur = (*cur & 0xff) | (val << 8);
 511     else
 512         *cur = (*cur & 0xff00) | (val & 0xff);
 513 }
 514
 515 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 516 {
 517     uint16_t x1, x0 = val & 0xff;
 518     int shift = (addr & 1) ? 8 : 0;
 519
 520     x1 = (*cur >> shift) & 0xff;
 521
 522     x1 = x1 & ~x0;
 523
 524     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 525 }
 526
 527 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 528 {
 529     PIIX4PMState *s = opaque;
 530     struct gpe_regs *g = &s->gpe;
 531
 532     switch (addr) {
 533         case GPE_BASE:
 534         case GPE_BASE + 1:
 535             gpe_reset_val(&g->sts, addr, val);
 536             break;
 537         case GPE_BASE + 2:
 538         case GPE_BASE + 3:
 539             gpe_write_val(&g->en, addr, val);
 540             break;
 541         default:
 542             break;
 543     }
 544
 545     pm_update_sci(s);
 546
 547     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 548 }
 549
 550 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 551 {
 552     uint32_t val = 0;
 553     struct pci_status *g = opaque;
 554     switch (addr) {
 555         case PCI_BASE:
 556             val = g->up;
 557             break;
 558         case PCI_BASE + 4:
 559             val = g->down;
 560             break;
 561         default:
 562             break;
 563     }
 564
 565     PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
 566     return val;
 567 }
 568
 569 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 570 {
 571     struct pci_status *g = opaque;
 572     switch (addr) {
 573         case PCI_BASE:
 574             g->up = val;
 575             break;
 576         case PCI_BASE + 4:
 577             g->down = val;
 578             break;
 579    }
 580
 581     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
 582 }
 583
 584 static uint32_t pciej_read(void *opaque, uint32_t addr)
 585 {
 586     PIIX4_DPRINTF("pciej read %x\n", addr);
 587     return 0;
 588 }
 589
 590 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 591 {
 592     BusState *bus = opaque;
 593     DeviceState *qdev, *next;
 594     PCIDevice *dev;
 595     int slot = ffs(val) - 1;
 596
 597     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 598         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 599         if (PCI_SLOT(dev->devfn) == slot) {
 600             qdev_free(qdev);
 601         }
 602     }
 603
 604
 605     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 606 }
 607
 608 extern const char *global_cpu_model;
 609
 610 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state);
 611
 612 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 613 {
 614     struct pci_status *pci0_status = &s->pci0_status;
 615     int i = 0, cpus = smp_cpus;
 616
 617     while (cpus > 0) {
 618         s->gpe.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
 619         cpus -= 8;
 620     }
 621
 622     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s);
 623     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, s);
 624
 625     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, s);
 626     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, s);
 627
 628     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
 629     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
 630
 631     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 632     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 633
 634     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 635 }
 636
 637 #if defined(TARGET_I386)
 638 static void enable_processor(struct gpe_regs *g, int cpu)
 639 {
 640     g->sts |= PIIX4_CPU_HOTPLUG_STATUS;
 641     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
 642 }
 643
 644 static void disable_processor(struct gpe_regs *g, int cpu)
 645 {
 646     g->sts |= PIIX4_CPU_HOTPLUG_STATUS;
 647     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
 648 }
 649
 650 void qemu_system_cpu_hot_add(int cpu, int state)
 651 {
 652     CPUState *env;
 653     PIIX4PMState *s = global_piix4_pm_state;
 654
 655     if (state && !qemu_get_cpu(cpu)) {
 656         env = pc_new_cpu(global_cpu_model);
 657         if (!env) {
 658             fprintf(stderr, "cpu %d creation failed\n", cpu);
 659             return;
 660         }
 661         env->cpuid_apic_id = cpu;
 662     }
 663
 664     if (state)
 665         enable_processor(&s->gpe, cpu);
 666     else
 667         disable_processor(&s->gpe, cpu);
 668
 669     pm_update_sci(s);
 670 }
 671 #endif
 672
 673 static void enable_device(PIIX4PMState *s, int slot)
 674 {
 675     s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
 676     s->pci0_status.up |= (1 << slot);
 677 }
 678
 679 static void disable_device(PIIX4PMState *s, int slot)
 680 {
 681     s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
 682     s->pci0_status.down |= (1 << slot);
 683 }
 684
 685 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state)
 686 {
 687     int slot = PCI_SLOT(dev->devfn);
 688     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 689                                 DO_UPCAST(PCIDevice, qdev, qdev));
 690
 691     if (!dev->qdev.hotplugged)
 692         return 0;
 693
 694     s->pci0_status.up = 0;
 695     s->pci0_status.down = 0;
 696     if (state) {
 697         enable_device(s, slot);
 698     } else {
 699         disable_device(s, slot);
 700     }
 701
 702     pm_update_sci(s);
 703
 704     return 0;
 705 }