cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "exec.h"
  21 #include "disas.h"
  22 #if !defined(TARGET_IA64)
  23 #include "tcg.h"
  24 #endif
  25 #include "kvm.h"
  26 #include "qemu-barrier.h"
  27
  28 #if !defined(CONFIG_SOFTMMU)
  29 #undef EAX
  30 #undef ECX
  31 #undef EDX
  32 #undef EBX
  33 #undef ESP
  34 #undef EBP
  35 #undef ESI
  36 #undef EDI
  37 #undef EIP
  38 #include <signal.h>
  39 #ifdef __linux__
  40 #include <sys/ucontext.h>
  41 #endif
  42 #endif
  43
  44 #include "qemu-kvm.h"
  45
  46 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
  47 // Work around ugly bugs in glibc that mangle global register contents
  48 #undef env
  49 #define env cpu_single_env
  50 #endif
  51
  52 int tb_invalidated_flag;
  53
  54 //#define CONFIG_DEBUG_EXEC
  55 //#define DEBUG_SIGNAL
  56
  57 int qemu_cpu_has_work(CPUState *env)
  58 {
  59     return cpu_has_work(env);
  60 }
  61
  62 void cpu_loop_exit(void)
  63 {
  64     env->current_tb = NULL;
  65     longjmp(env->jmp_env, 1);
  66 }
  67
  68 /* exit the current TB from a signal handler. The host registers are
  69    restored in a state compatible with the CPU emulator
  70  */
  71 void cpu_resume_from_signal(CPUState *env1, void *puc)
  72 {
  73 #if !defined(CONFIG_SOFTMMU)
  74 #ifdef __linux__
  75     struct ucontext *uc = puc;
  76 #elif defined(__OpenBSD__)
  77     struct sigcontext *uc = puc;
  78 #endif
  79 #endif
  80
  81     env = env1;
  82
  83     /* XXX: restore cpu registers saved in host registers */
  84
  85 #if !defined(CONFIG_SOFTMMU)
  86     if (puc) {
  87         /* XXX: use siglongjmp ? */
  88 #ifdef __linux__
  89 #ifdef __ia64
  90         sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
  91 #else
  92         sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
  93 #endif
  94 #elif defined(__OpenBSD__)
  95         sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
  96 #endif
  97     }
  98 #endif
  99     env->exception_index = -1;
 100     longjmp(env->jmp_env, 1);
 101 }
 102
 103 /* Execute the code without caching the generated code. An interpreter
 104    could be used if available. */
 105 static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
 106 {
 107     unsigned long next_tb;
 108     TranslationBlock *tb;
 109
 110     /* Should never happen.
 111        We only end up here when an existing TB is too long.  */
 112     if (max_cycles > CF_COUNT_MASK)
 113         max_cycles = CF_COUNT_MASK;
 114
 115     tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
 116                      max_cycles);
 117     env->current_tb = tb;
 118     /* execute the generated code */
 119     next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
 120     env->current_tb = NULL;
 121
 122     if ((next_tb & 3) == 2) {
 123         /* Restore PC.  This may happen if async event occurs before
 124            the TB starts executing.  */
 125         cpu_pc_from_tb(env, tb);
 126     }
 127     tb_phys_invalidate(tb, -1);
 128     tb_free(tb);
 129 }
 130
 131 static TranslationBlock *tb_find_slow(target_ulong pc,
 132                                       target_ulong cs_base,
 133                                       uint64_t flags)
 134 {
 135     TranslationBlock *tb, **ptb1;
 136     unsigned int h;
 137     tb_page_addr_t phys_pc, phys_page1, phys_page2;
 138     target_ulong virt_page2;
 139
 140     tb_invalidated_flag = 0;
 141
 142     /* find translated block using physical mappings */
 143     phys_pc = get_page_addr_code(env, pc);
 144     phys_page1 = phys_pc & TARGET_PAGE_MASK;
 145     phys_page2 = -1;
 146     h = tb_phys_hash_func(phys_pc);
 147     ptb1 = &tb_phys_hash[h];
 148     for(;;) {
 149         tb = *ptb1;
 150         if (!tb)
 151             goto not_found;
 152         if (tb->pc == pc &&
 153             tb->page_addr[0] == phys_page1 &&
 154             tb->cs_base == cs_base &&
 155             tb->flags == flags) {
 156             /* check next page if needed */
 157             if (tb->page_addr[1] != -1) {
 158                 virt_page2 = (pc & TARGET_PAGE_MASK) +
 159                     TARGET_PAGE_SIZE;
 160                 phys_page2 = get_page_addr_code(env, virt_page2);
 161                 if (tb->page_addr[1] == phys_page2)
 162                     goto found;
 163             } else {
 164                 goto found;
 165             }
 166         }
 167         ptb1 = &tb->phys_hash_next;
 168     }
 169  not_found:
 170    /* if no translated code available, then translate it now */
 171     tb = tb_gen_code(env, pc, cs_base, flags, 0);
 172
 173  found:
 174     /* we add the TB in the virtual pc hash table */
 175     env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
 176     return tb;
 177 }
 178
 179 static inline TranslationBlock *tb_find_fast(void)
 180 {
 181     TranslationBlock *tb;
 182     target_ulong cs_base, pc;
 183     int flags;
 184
 185     /* we record a subset of the CPU state. It will
 186        always be the same before a given translated block
 187        is executed. */
 188     cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
 189     tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
 190     if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
 191                  tb->flags != flags)) {
 192         tb = tb_find_slow(pc, cs_base, flags);
 193     }
 194     return tb;
 195 }
 196
 197 static CPUDebugExcpHandler *debug_excp_handler;
 198
 199 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
 200 {
 201     CPUDebugExcpHandler *old_handler = debug_excp_handler;
 202
 203     debug_excp_handler = handler;
 204     return old_handler;
 205 }
 206
 207 static void cpu_handle_debug_exception(CPUState *env)
 208 {
 209     CPUWatchpoint *wp;
 210
 211     if (!env->watchpoint_hit)
 212         QTAILQ_FOREACH(wp, &env->watchpoints, entry)
 213             wp->flags &= ~BP_WATCHPOINT_HIT;
 214
 215     if (debug_excp_handler)
 216         debug_excp_handler(env);
 217 }
 218
 219 /* main execution loop */
 220
 221 volatile sig_atomic_t exit_request;
 222
 223 int cpu_exec(CPUState *env1)
 224 {
 225     volatile host_reg_t saved_env_reg;
 226     int ret, interrupt_request;
 227     TranslationBlock *tb;
 228     uint8_t *tc_ptr;
 229     unsigned long next_tb;
 230
 231     if (cpu_halted(env1) == EXCP_HALTED)
 232         return EXCP_HALTED;
 233
 234     cpu_single_env = env1;
 235
 236     /* the access to env below is actually saving the global register's
 237        value, so that files not including target-xyz/exec.h are free to
 238        use it.  */
 239     QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env));
 240     saved_env_reg = (host_reg_t) env;
 241     barrier();
 242     env = env1;
 243
 244     if (unlikely(exit_request)) {
 245         env->exit_request = 1;
 246     }
 247
 248 #if defined(TARGET_I386)
 249     if (!kvm_enabled()) {
 250         /* put eflags in CPU temporary format */
 251         CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 252         DF = 1 - (2 * ((env->eflags >> 10) & 1));
 253         CC_OP = CC_OP_EFLAGS;
 254         env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 255     }
 256 #elif defined(TARGET_SPARC)
 257 #elif defined(TARGET_M68K)
 258     env->cc_op = CC_OP_FLAGS;
 259     env->cc_dest = env->sr & 0xf;
 260     env->cc_x = (env->sr >> 4) & 1;
 261 #elif defined(TARGET_ALPHA)
 262 #elif defined(TARGET_ARM)
 263 #elif defined(TARGET_PPC)
 264 #elif defined(TARGET_MICROBLAZE)
 265 #elif defined(TARGET_MIPS)
 266 #elif defined(TARGET_SH4)
 267 #elif defined(TARGET_CRIS)
 268 #elif defined(TARGET_S390X)
 269 #elif defined(TARGET_IA64)
 270     /* XXXXX */
 271 #else
 272 #error unsupported target CPU
 273 #endif
 274     env->exception_index = -1;
 275
 276     /* prepare setjmp context for exception handling */
 277     for(;;) {
 278         if (setjmp(env->jmp_env) == 0) {
 279 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
 280 #undef env
 281                     env = cpu_single_env;
 282 #define env cpu_single_env
 283 #endif
 284             /* if an exception is pending, we execute it here */
 285             if (env->exception_index >= 0) {
 286                 if (env->exception_index >= EXCP_INTERRUPT) {
 287                     /* exit request from the cpu execution loop */
 288                     ret = env->exception_index;
 289                     if (ret == EXCP_DEBUG)
 290                         cpu_handle_debug_exception(env);
 291                     break;
 292                 } else {
 293 #if defined(CONFIG_USER_ONLY)
 294                     /* if user mode only, we simulate a fake exception
 295                        which will be handled outside the cpu execution
 296                        loop */
 297 #if defined(TARGET_I386)
 298                     do_interrupt_user(env->exception_index,
 299                                       env->exception_is_int,
 300                                       env->error_code,
 301                                       env->exception_next_eip);
 302                     /* successfully delivered */
 303                     env->old_exception = -1;
 304 #endif
 305                     ret = env->exception_index;
 306                     break;
 307 #else
 308 #if defined(TARGET_I386)
 309                     /* simulate a real cpu exception. On i386, it can
 310                        trigger new exceptions, but we do not handle
 311                        double or triple faults yet. */
 312                     do_interrupt(env->exception_index,
 313                                  env->exception_is_int,
 314                                  env->error_code,
 315                                  env->exception_next_eip, 0);
 316                     /* successfully delivered */
 317                     env->old_exception = -1;
 318 #elif defined(TARGET_PPC)
 319                     do_interrupt(env);
 320 #elif defined(TARGET_MICROBLAZE)
 321                     do_interrupt(env);
 322 #elif defined(TARGET_MIPS)
 323                     do_interrupt(env);
 324 #elif defined(TARGET_SPARC)
 325                     do_interrupt(env);
 326 #elif defined(TARGET_ARM)
 327                     do_interrupt(env);
 328 #elif defined(TARGET_SH4)
 329                     do_interrupt(env);
 330 #elif defined(TARGET_ALPHA)
 331                     do_interrupt(env);
 332 #elif defined(TARGET_CRIS)
 333                     do_interrupt(env);
 334 #elif defined(TARGET_M68K)
 335                     do_interrupt(0);
 336 #elif defined(TARGET_IA64)
 337                     do_interrupt(env);
 338 #endif
 339                     env->exception_index = -1;
 340 #endif
 341                 }
 342             }
 343
 344             if (kvm_enabled()) {
 345                 kvm_cpu_exec(env);
 346                 longjmp(env->jmp_env, 1);
 347             }
 348
 349             next_tb = 0; /* force lookup of first TB */
 350             for(;;) {
 351                 interrupt_request = env->interrupt_request;
 352                 if (unlikely(interrupt_request)) {
 353                     if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
 354                         /* Mask out external interrupts for this step. */
 355                         interrupt_request &= ~(CPU_INTERRUPT_HARD |
 356                                                CPU_INTERRUPT_FIQ |
 357                                                CPU_INTERRUPT_SMI |
 358                                                CPU_INTERRUPT_NMI);
 359                     }
 360                     if (interrupt_request & CPU_INTERRUPT_DEBUG) {
 361                         env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
 362                         env->exception_index = EXCP_DEBUG;
 363                         cpu_loop_exit();
 364                     }
 365 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
 366     defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
 367     defined(TARGET_MICROBLAZE)
 368                     if (interrupt_request & CPU_INTERRUPT_HALT) {
 369                         env->interrupt_request &= ~CPU_INTERRUPT_HALT;
 370                         env->halted = 1;
 371                         env->exception_index = EXCP_HLT;
 372                         cpu_loop_exit();
 373                     }
 374 #endif
 375 #if defined(TARGET_I386)
 376                     if (interrupt_request & CPU_INTERRUPT_INIT) {
 377                             svm_check_intercept(SVM_EXIT_INIT);
 378                             do_cpu_init(env);
 379                             env->exception_index = EXCP_HALTED;
 380                             cpu_loop_exit();
 381                     } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
 382                             do_cpu_sipi(env);
 383                     } else if (env->hflags2 & HF2_GIF_MASK) {
 384                         if ((interrupt_request & CPU_INTERRUPT_SMI) &&
 385                             !(env->hflags & HF_SMM_MASK)) {
 386                             svm_check_intercept(SVM_EXIT_SMI);
 387                             env->interrupt_request &= ~CPU_INTERRUPT_SMI;
 388                             do_smm_enter();
 389                             next_tb = 0;
 390                         } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
 391                                    !(env->hflags2 & HF2_NMI_MASK)) {
 392                             env->interrupt_request &= ~CPU_INTERRUPT_NMI;
 393                             env->hflags2 |= HF2_NMI_MASK;
 394                             do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
 395                             next_tb = 0;
 396                         } else if (interrupt_request & CPU_INTERRUPT_MCE) {
 397                             env->interrupt_request &= ~CPU_INTERRUPT_MCE;
 398                             do_interrupt(EXCP12_MCHK, 0, 0, 0, 0);
 399                             next_tb = 0;
 400                         } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 401                                    (((env->hflags2 & HF2_VINTR_MASK) &&
 402                                      (env->hflags2 & HF2_HIF_MASK)) ||
 403                                     (!(env->hflags2 & HF2_VINTR_MASK) &&
 404                                      (env->eflags & IF_MASK &&
 405                                       !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
 406                             int intno;
 407                             svm_check_intercept(SVM_EXIT_INTR);
 408                             env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
 409                             intno = cpu_get_pic_interrupt(env);
 410                             qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
 411 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
 412 #undef env
 413                     env = cpu_single_env;
 414 #define env cpu_single_env
 415 #endif
 416                             do_interrupt(intno, 0, 0, 0, 1);
 417                             /* ensure that no TB jump will be modified as
 418                                the program flow was changed */
 419                             next_tb = 0;
 420 #if !defined(CONFIG_USER_ONLY)
 421                         } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
 422                                    (env->eflags & IF_MASK) &&
 423                                    !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
 424                             int intno;
 425                             /* FIXME: this should respect TPR */
 426                             svm_check_intercept(SVM_EXIT_VINTR);
 427                             intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
 428                             qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
 429                             do_interrupt(intno, 0, 0, 0, 1);
 430                             env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
 431                             next_tb = 0;
 432 #endif
 433                         }
 434                     }
 435 #elif defined(TARGET_PPC)
 436 #if 0
 437                     if ((interrupt_request & CPU_INTERRUPT_RESET)) {
 438                         cpu_reset(env);
 439                     }
 440 #endif
 441                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 442                         ppc_hw_interrupt(env);
 443                         if (env->pending_interrupts == 0)
 444                             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 445                         next_tb = 0;
 446                     }
 447 #elif defined(TARGET_MICROBLAZE)
 448                     if ((interrupt_request & CPU_INTERRUPT_HARD)
 449                         && (env->sregs[SR_MSR] & MSR_IE)
 450                         && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
 451                         && !(env->iflags & (D_FLAG | IMM_FLAG))) {
 452                         env->exception_index = EXCP_IRQ;
 453                         do_interrupt(env);
 454                         next_tb = 0;
 455                     }
 456 #elif defined(TARGET_MIPS)
 457                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 458                         cpu_mips_hw_interrupts_pending(env) &&
 459                         (env->CP0_Status & (1 << CP0St_IE)) &&
 460                         !(env->CP0_Status & (1 << CP0St_EXL)) &&
 461                         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 462                         !(env->hflags & MIPS_HFLAG_DM)) {
 463                         /* Raise it */
 464                         env->exception_index = EXCP_EXT_INTERRUPT;
 465                         env->error_code = 0;
 466                         do_interrupt(env);
 467                         next_tb = 0;
 468                     }
 469 #elif defined(TARGET_SPARC)
 470                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 471                         if (cpu_interrupts_enabled(env) &&
 472                             env->interrupt_index > 0) {
 473                             int pil = env->interrupt_index & 0xf;
 474                             int type = env->interrupt_index & 0xf0;
 475
 476                             if (((type == TT_EXTINT) &&
 477                                   cpu_pil_allowed(env, pil)) ||
 478                                   type != TT_EXTINT) {
 479                                 env->exception_index = env->interrupt_index;
 480                                 do_interrupt(env);
 481                                 next_tb = 0;
 482                             }
 483                         }
 484                     } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
 485                         //do_interrupt(0, 0, 0, 0, 0);
 486                         env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 487                     }
 488 #elif defined(TARGET_ARM)
 489                     if (interrupt_request & CPU_INTERRUPT_FIQ
 490                         && !(env->uncached_cpsr & CPSR_F)) {
 491                         env->exception_index = EXCP_FIQ;
 492                         do_interrupt(env);
 493                         next_tb = 0;
 494                     }
 495                     /* ARMv7-M interrupt return works by loading a magic value
 496                        into the PC.  On real hardware the load causes the
 497                        return to occur.  The qemu implementation performs the
 498                        jump normally, then does the exception return when the
 499                        CPU tries to execute code at the magic address.
 500                        This will cause the magic PC value to be pushed to
 501                        the stack if an interrupt occured at the wrong time.
 502                        We avoid this by disabling interrupts when
 503                        pc contains a magic address.  */
 504                     if (interrupt_request & CPU_INTERRUPT_HARD
 505                         && ((IS_M(env) && env->regs[15] < 0xfffffff0)
 506                             || !(env->uncached_cpsr & CPSR_I))) {
 507                         env->exception_index = EXCP_IRQ;
 508                         do_interrupt(env);
 509                         next_tb = 0;
 510                     }
 511 #elif defined(TARGET_SH4)
 512                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 513                         do_interrupt(env);
 514                         next_tb = 0;
 515                     }
 516 #elif defined(TARGET_ALPHA)
 517                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 518                         do_interrupt(env);
 519                         next_tb = 0;
 520                     }
 521 #elif defined(TARGET_CRIS)
 522                     if (interrupt_request & CPU_INTERRUPT_HARD
 523                         && (env->pregs[PR_CCS] & I_FLAG)
 524                         && !env->locked_irq) {
 525                         env->exception_index = EXCP_IRQ;
 526                         do_interrupt(env);
 527                         next_tb = 0;
 528                     }
 529                     if (interrupt_request & CPU_INTERRUPT_NMI
 530                         && (env->pregs[PR_CCS] & M_FLAG)) {
 531                         env->exception_index = EXCP_NMI;
 532                         do_interrupt(env);
 533                         next_tb = 0;
 534                     }
 535 #elif defined(TARGET_M68K)
 536                     if (interrupt_request & CPU_INTERRUPT_HARD
 537                         && ((env->sr & SR_I) >> SR_I_SHIFT)
 538                             < env->pending_level) {
 539                         /* Real hardware gets the interrupt vector via an
 540                            IACK cycle at this point.  Current emulated
 541                            hardware doesn't rely on this, so we
 542                            provide/save the vector when the interrupt is
 543                            first signalled.  */
 544                         env->exception_index = env->pending_vector;
 545                         do_interrupt(1);
 546                         next_tb = 0;
 547                     }
 548 #endif
 549                    /* Don't use the cached interupt_request value,
 550                       do_interrupt may have updated the EXITTB flag. */
 551                     if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
 552                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
 553                         /* ensure that no TB jump will be modified as
 554                            the program flow was changed */
 555                         next_tb = 0;
 556                     }
 557                 }
 558                 if (unlikely(env->exit_request)) {
 559                     env->exit_request = 0;
 560                     env->exception_index = EXCP_INTERRUPT;
 561                     cpu_loop_exit();
 562                 }
 563 #if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
 564                 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
 565                     /* restore flags in standard format */
 566 #if defined(TARGET_I386)
 567                     env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
 568                     log_cpu_state(env, X86_DUMP_CCOP);
 569                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 570 #elif defined(TARGET_M68K)
 571                     cpu_m68k_flush_flags(env, env->cc_op);
 572                     env->cc_op = CC_OP_FLAGS;
 573                     env->sr = (env->sr & 0xffe0)
 574                               | env->cc_dest | (env->cc_x << 4);
 575                     log_cpu_state(env, 0);
 576 #else
 577                     log_cpu_state(env, 0);
 578 #endif
 579                 }
 580 #endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
 581                 spin_lock(&tb_lock);
 582                 tb = tb_find_fast();
 583                 /* Note: we do it here to avoid a gcc bug on Mac OS X when
 584                    doing it in tb_find_slow */
 585                 if (tb_invalidated_flag) {
 586                     /* as some TB could have been invalidated because
 587                        of memory exceptions while generating the code, we
 588                        must recompute the hash index here */
 589                     next_tb = 0;
 590                     tb_invalidated_flag = 0;
 591                 }
 592 #ifdef CONFIG_DEBUG_EXEC
 593                 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
 594                              (long)tb->tc_ptr, tb->pc,
 595                              lookup_symbol(tb->pc));
 596 #endif
 597                 /* see if we can patch the calling TB. When the TB
 598                    spans two pages, we cannot safely do a direct
 599                    jump. */
 600                 if (next_tb != 0 && tb->page_addr[1] == -1) {
 601                     tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
 602                 }
 603                 spin_unlock(&tb_lock);
 604
 605                 /* cpu_interrupt might be called while translating the
 606                    TB, but before it is linked into a potentially
 607                    infinite loop and becomes env->current_tb. Avoid
 608                    starting execution if there is a pending interrupt. */
 609                 env->current_tb = tb;
 610                 barrier();
 611                 if (likely(!env->exit_request)) {
 612                     tc_ptr = tb->tc_ptr;
 613                 /* execute the generated code */
 614 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
 615 #undef env
 616                     env = cpu_single_env;
 617 #define env cpu_single_env
 618 #endif
 619                     next_tb = tcg_qemu_tb_exec(tc_ptr);
 620                     if ((next_tb & 3) == 2) {
 621                         /* Instruction counter expired.  */
 622                         int insns_left;
 623                         tb = (TranslationBlock *)(long)(next_tb & ~3);
 624                         /* Restore PC.  */
 625                         cpu_pc_from_tb(env, tb);
 626                         insns_left = env->icount_decr.u32;
 627                         if (env->icount_extra && insns_left >= 0) {
 628                             /* Refill decrementer and continue execution.  */
 629                             env->icount_extra += insns_left;
 630                             if (env->icount_extra > 0xffff) {
 631                                 insns_left = 0xffff;
 632                             } else {
 633                                 insns_left = env->icount_extra;
 634                             }
 635                             env->icount_extra -= insns_left;
 636                             env->icount_decr.u16.low = insns_left;
 637                         } else {
 638                             if (insns_left > 0) {
 639                                 /* Execute remaining instructions.  */
 640                                 cpu_exec_nocache(insns_left, tb);
 641                             }
 642                             env->exception_index = EXCP_INTERRUPT;
 643                             next_tb = 0;
 644                             cpu_loop_exit();
 645                         }
 646                     }
 647                 }
 648                 env->current_tb = NULL;
 649                 /* reset soft MMU for next block (it can currently
 650                    only be set by a memory fault) */
 651             } /* for(;;) */
 652         }
 653     } /* for(;;) */
 654
 655
 656 #if defined(TARGET_I386)
 657     /* restore flags in standard format */
 658     env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
 659 #elif defined(TARGET_ARM)
 660     /* XXX: Save/restore host fpu exception state?.  */
 661 #elif defined(TARGET_SPARC)
 662 #elif defined(TARGET_PPC)
 663 #elif defined(TARGET_M68K)
 664     cpu_m68k_flush_flags(env, env->cc_op);
 665     env->cc_op = CC_OP_FLAGS;
 666     env->sr = (env->sr & 0xffe0)
 667               | env->cc_dest | (env->cc_x << 4);
 668 #elif defined(TARGET_MICROBLAZE)
 669 #elif defined(TARGET_MIPS)
 670 #elif defined(TARGET_SH4)
 671 #elif defined(TARGET_IA64)
 672 #elif defined(TARGET_ALPHA)
 673 #elif defined(TARGET_CRIS)
 674 #elif defined(TARGET_S390X)
 675     /* XXXXX */
 676 #else
 677 #error unsupported target CPU
 678 #endif
 679
 680     /* restore global registers */
 681     barrier();
 682     env = (void *) saved_env_reg;
 683
 684     /* fail safe : never use cpu_single_env outside cpu_exec() */
 685     cpu_single_env = NULL;
 686     return ret;
 687 }
 688
 689 /* must only be called from the generated code as an exception can be
 690    generated */
 691 void tb_invalidate_page_range(target_ulong start, target_ulong end)
 692 {
 693     /* XXX: cannot enable it yet because it yields to MMU exception
 694        where NIP != read address on PowerPC */
 695 #if 0
 696     target_ulong phys_addr;
 697     phys_addr = get_phys_addr_code(env, start);
 698     tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
 699 #endif
 700 }
 701
 702 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
 703
 704 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
 705 {
 706     CPUX86State *saved_env;
 707
 708     saved_env = env;
 709     env = s;
 710     if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 711         selector &= 0xffff;
 712         cpu_x86_load_seg_cache(env, seg_reg, selector,
 713                                (selector << 4), 0xffff, 0);
 714     } else {
 715         helper_load_seg(seg_reg, selector);
 716     }
 717     env = saved_env;
 718 }
 719
 720 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
 721 {
 722     CPUX86State *saved_env;
 723
 724     saved_env = env;
 725     env = s;
 726
 727     helper_fsave(ptr, data32);
 728
 729     env = saved_env;
 730 }
 731
 732 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
 733 {
 734     CPUX86State *saved_env;
 735
 736     saved_env = env;
 737     env = s;
 738
 739     helper_frstor(ptr, data32);
 740
 741     env = saved_env;
 742 }
 743
 744 #endif /* TARGET_I386 */
 745
 746 #if !defined(CONFIG_SOFTMMU)
 747
 748 #if defined(TARGET_I386)
 749 #define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
 750 #else
 751 #define EXCEPTION_ACTION cpu_loop_exit()
 752 #endif
 753
 754 /* 'pc' is the host PC at which the exception was raised. 'address' is
 755    the effective address of the memory exception. 'is_write' is 1 if a
 756    write caused the exception and otherwise 0'. 'old_set' is the
 757    signal set which should be restored */
 758 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 759                                     int is_write, sigset_t *old_set,
 760                                     void *puc)
 761 {
 762     TranslationBlock *tb;
 763     int ret;
 764
 765     if (cpu_single_env)
 766         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 767 #if defined(DEBUG_SIGNAL)
 768     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 769                 pc, address, is_write, *(unsigned long *)old_set);
 770 #endif
 771     /* XXX: locking issue */
 772     if (is_write && page_unprotect(h2g(address), pc, puc)) {
 773         return 1;
 774     }
 775
 776     /* see if it is an MMU fault */
 777     ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
 778     if (ret < 0)
 779         return 0; /* not an MMU fault */
 780     if (ret == 0)
 781         return 1; /* the MMU fault was handled without causing real CPU fault */
 782     /* now we have a real cpu fault */
 783     tb = tb_find_pc(pc);
 784     if (tb) {
 785         /* the PC is inside the translated code. It means that we have
 786            a virtual CPU fault */
 787         cpu_restore_state(tb, env, pc, puc);
 788     }
 789
 790     /* we restore the process signal mask as the sigreturn should
 791        do it (XXX: use sigsetjmp) */
 792     sigprocmask(SIG_SETMASK, old_set, NULL);
 793     EXCEPTION_ACTION;
 794
 795     /* never comes here */
 796     return 1;
 797 }
 798
 799 #if defined(__i386__)
 800
 801 #if defined(__APPLE__)
 802 # include <sys/ucontext.h>
 803
 804 # define EIP_sig(context)  (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
 805 # define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
 806 # define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
 807 # define MASK_sig(context)    ((context)->uc_sigmask)
 808 #elif defined (__NetBSD__)
 809 # include <ucontext.h>
 810
 811 # define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 812 # define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 813 # define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 814 # define MASK_sig(context)    ((context)->uc_sigmask)
 815 #elif defined (__FreeBSD__) || defined(__DragonFly__)
 816 # include <ucontext.h>
 817
 818 # define EIP_sig(context)  (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
 819 # define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 820 # define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 821 # define MASK_sig(context)    ((context)->uc_sigmask)
 822 #elif defined(__OpenBSD__)
 823 # define EIP_sig(context)     ((context)->sc_eip)
 824 # define TRAP_sig(context)    ((context)->sc_trapno)
 825 # define ERROR_sig(context)   ((context)->sc_err)
 826 # define MASK_sig(context)    ((context)->sc_mask)
 827 #else
 828 # define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 829 # define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 830 # define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 831 # define MASK_sig(context)    ((context)->uc_sigmask)
 832 #endif
 833
 834 int cpu_signal_handler(int host_signum, void *pinfo,
 835                        void *puc)
 836 {
 837     siginfo_t *info = pinfo;
 838 #if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
 839     ucontext_t *uc = puc;
 840 #elif defined(__OpenBSD__)
 841     struct sigcontext *uc = puc;
 842 #else
 843     struct ucontext *uc = puc;
 844 #endif
 845     unsigned long pc;
 846     int trapno;
 847
 848 #ifndef REG_EIP
 849 /* for glibc 2.1 */
 850 #define REG_EIP    EIP
 851 #define REG_ERR    ERR
 852 #define REG_TRAPNO TRAPNO
 853 #endif
 854     pc = EIP_sig(uc);
 855     trapno = TRAP_sig(uc);
 856     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 857                              trapno == 0xe ?
 858                              (ERROR_sig(uc) >> 1) & 1 : 0,
 859                              &MASK_sig(uc), puc);
 860 }
 861
 862 #elif defined(__x86_64__)
 863
 864 #ifdef __NetBSD__
 865 #define PC_sig(context)       _UC_MACHINE_PC(context)
 866 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 867 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 868 #define MASK_sig(context)     ((context)->uc_sigmask)
 869 #elif defined(__OpenBSD__)
 870 #define PC_sig(context)       ((context)->sc_rip)
 871 #define TRAP_sig(context)     ((context)->sc_trapno)
 872 #define ERROR_sig(context)    ((context)->sc_err)
 873 #define MASK_sig(context)     ((context)->sc_mask)
 874 #elif defined (__FreeBSD__) || defined(__DragonFly__)
 875 #include <ucontext.h>
 876
 877 #define PC_sig(context)  (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
 878 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 879 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 880 #define MASK_sig(context)     ((context)->uc_sigmask)
 881 #else
 882 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 883 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 884 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 885 #define MASK_sig(context)     ((context)->uc_sigmask)
 886 #endif
 887
 888 int cpu_signal_handler(int host_signum, void *pinfo,
 889                        void *puc)
 890 {
 891     siginfo_t *info = pinfo;
 892     unsigned long pc;
 893 #if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
 894     ucontext_t *uc = puc;
 895 #elif defined(__OpenBSD__)
 896     struct sigcontext *uc = puc;
 897 #else
 898     struct ucontext *uc = puc;
 899 #endif
 900
 901     pc = PC_sig(uc);
 902     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 903                              TRAP_sig(uc) == 0xe ?
 904                              (ERROR_sig(uc) >> 1) & 1 : 0,
 905                              &MASK_sig(uc), puc);
 906 }
 907
 908 #elif defined(_ARCH_PPC)
 909
 910 /***********************************************************************
 911  * signal context platform-specific definitions
 912  * From Wine
 913  */
 914 #ifdef linux
 915 /* All Registers access - only for local access */
 916 # define REG_sig(reg_name, context)             ((context)->uc_mcontext.regs->reg_name)
 917 /* Gpr Registers access  */
 918 # define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 919 # define IAR_sig(context)                       REG_sig(nip, context)   /* Program counter */
 920 # define MSR_sig(context)                       REG_sig(msr, context)   /* Machine State Register (Supervisor) */
 921 # define CTR_sig(context)                       REG_sig(ctr, context)   /* Count register */
 922 # define XER_sig(context)                       REG_sig(xer, context) /* User's integer exception register */
 923 # define LR_sig(context)                        REG_sig(link, context) /* Link register */
 924 # define CR_sig(context)                        REG_sig(ccr, context) /* Condition register */
 925 /* Float Registers access  */
 926 # define FLOAT_sig(reg_num, context)            (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
 927 # define FPSCR_sig(context)                     (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
 928 /* Exception Registers access */
 929 # define DAR_sig(context)                       REG_sig(dar, context)
 930 # define DSISR_sig(context)                     REG_sig(dsisr, context)
 931 # define TRAP_sig(context)                      REG_sig(trap, context)
 932 #endif /* linux */
 933
 934 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 935 #include <ucontext.h>
 936 # define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 937 # define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 938 # define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 939 # define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 940 # define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 941 # define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 942 /* Exception Registers access */
 943 # define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 944 # define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 945 # define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 946 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 947
 948 #ifdef __APPLE__
 949 # include <sys/ucontext.h>
 950 typedef struct ucontext SIGCONTEXT;
 951 /* All Registers access - only for local access */
 952 # define REG_sig(reg_name, context)             ((context)->uc_mcontext->ss.reg_name)
 953 # define FLOATREG_sig(reg_name, context)        ((context)->uc_mcontext->fs.reg_name)
 954 # define EXCEPREG_sig(reg_name, context)        ((context)->uc_mcontext->es.reg_name)
 955 # define VECREG_sig(reg_name, context)          ((context)->uc_mcontext->vs.reg_name)
 956 /* Gpr Registers access */
 957 # define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
 958 # define IAR_sig(context)                       REG_sig(srr0, context)  /* Program counter */
 959 # define MSR_sig(context)                       REG_sig(srr1, context)  /* Machine State Register (Supervisor) */
 960 # define CTR_sig(context)                       REG_sig(ctr, context)
 961 # define XER_sig(context)                       REG_sig(xer, context) /* Link register */
 962 # define LR_sig(context)                        REG_sig(lr, context)  /* User's integer exception register */
 963 # define CR_sig(context)                        REG_sig(cr, context)  /* Condition register */
 964 /* Float Registers access */
 965 # define FLOAT_sig(reg_num, context)            FLOATREG_sig(fpregs[reg_num], context)
 966 # define FPSCR_sig(context)                     ((double)FLOATREG_sig(fpscr, context))
 967 /* Exception Registers access */
 968 # define DAR_sig(context)                       EXCEPREG_sig(dar, context)     /* Fault registers for coredump */
 969 # define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
 970 # define TRAP_sig(context)                      EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
 971 #endif /* __APPLE__ */
 972
 973 int cpu_signal_handler(int host_signum, void *pinfo,
 974                        void *puc)
 975 {
 976     siginfo_t *info = pinfo;
 977 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 978     ucontext_t *uc = puc;
 979 #else
 980     struct ucontext *uc = puc;
 981 #endif
 982     unsigned long pc;
 983     int is_write;
 984
 985     pc = IAR_sig(uc);
 986     is_write = 0;
 987 #if 0
 988     /* ppc 4xx case */
 989     if (DSISR_sig(uc) & 0x00800000)
 990         is_write = 1;
 991 #else
 992     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
 993         is_write = 1;
 994 #endif
 995     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 996                              is_write, &uc->uc_sigmask, puc);
 997 }
 998
 999 #elif defined(__alpha__)
1000
1001 int cpu_signal_handler(int host_signum, void *pinfo,
1002                            void *puc)
1003 {
1004     siginfo_t *info = pinfo;
1005     struct ucontext *uc = puc;
1006     uint32_t *pc = uc->uc_mcontext.sc_pc;
1007     uint32_t insn = *pc;
1008     int is_write = 0;
1009
1010     /* XXX: need kernel patch to get write flag faster */
1011     switch (insn >> 26) {
1012     case 0x0d: // stw
1013     case 0x0e: // stb
1014     case 0x0f: // stq_u
1015     case 0x24: // stf
1016     case 0x25: // stg
1017     case 0x26: // sts
1018     case 0x27: // stt
1019     case 0x2c: // stl
1020     case 0x2d: // stq
1021     case 0x2e: // stl_c
1022     case 0x2f: // stq_c
1023         is_write = 1;
1024     }
1025
1026     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1027                              is_write, &uc->uc_sigmask, puc);
1028 }
1029 #elif defined(__sparc__)
1030
1031 int cpu_signal_handler(int host_signum, void *pinfo,
1032                        void *puc)
1033 {
1034     siginfo_t *info = pinfo;
1035     int is_write;
1036     uint32_t insn;
1037 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
1038     uint32_t *regs = (uint32_t *)(info + 1);
1039     void *sigmask = (regs + 20);
1040     /* XXX: is there a standard glibc define ? */
1041     unsigned long pc = regs[1];
1042 #else
1043 #ifdef __linux__
1044     struct sigcontext *sc = puc;
1045     unsigned long pc = sc->sigc_regs.tpc;
1046     void *sigmask = (void *)sc->sigc_mask;
1047 #elif defined(__OpenBSD__)
1048     struct sigcontext *uc = puc;
1049     unsigned long pc = uc->sc_pc;
1050     void *sigmask = (void *)(long)uc->sc_mask;
1051 #endif
1052 #endif
1053
1054     /* XXX: need kernel patch to get write flag faster */
1055     is_write = 0;
1056     insn = *(uint32_t *)pc;
1057     if ((insn >> 30) == 3) {
1058       switch((insn >> 19) & 0x3f) {
1059       case 0x05: // stb
1060       case 0x15: // stba
1061       case 0x06: // sth
1062       case 0x16: // stha
1063       case 0x04: // st
1064       case 0x14: // sta
1065       case 0x07: // std
1066       case 0x17: // stda
1067       case 0x0e: // stx
1068       case 0x1e: // stxa
1069       case 0x24: // stf
1070       case 0x34: // stfa
1071       case 0x27: // stdf
1072       case 0x37: // stdfa
1073       case 0x26: // stqf
1074       case 0x36: // stqfa
1075       case 0x25: // stfsr
1076       case 0x3c: // casa
1077       case 0x3e: // casxa
1078         is_write = 1;
1079         break;
1080       }
1081     }
1082     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1083                              is_write, sigmask, NULL);
1084 }
1085
1086 #elif defined(__arm__)
1087
1088 int cpu_signal_handler(int host_signum, void *pinfo,
1089                        void *puc)
1090 {
1091     siginfo_t *info = pinfo;
1092     struct ucontext *uc = puc;
1093     unsigned long pc;
1094     int is_write;
1095
1096 #if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
1097     pc = uc->uc_mcontext.gregs[R15];
1098 #else
1099     pc = uc->uc_mcontext.arm_pc;
1100 #endif
1101     /* XXX: compute is_write */
1102     is_write = 0;
1103     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1104                              is_write,
1105                              &uc->uc_sigmask, puc);
1106 }
1107
1108 #elif defined(__mc68000)
1109
1110 int cpu_signal_handler(int host_signum, void *pinfo,
1111                        void *puc)
1112 {
1113     siginfo_t *info = pinfo;
1114     struct ucontext *uc = puc;
1115     unsigned long pc;
1116     int is_write;
1117
1118     pc = uc->uc_mcontext.gregs[16];
1119     /* XXX: compute is_write */
1120     is_write = 0;
1121     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1122                              is_write,
1123                              &uc->uc_sigmask, puc);
1124 }
1125
1126 #elif defined(__ia64)
1127
1128 #ifndef __ISR_VALID
1129   /* This ought to be in <bits/siginfo.h>... */
1130 # define __ISR_VALID    1
1131 #endif
1132
1133 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1134 {
1135     siginfo_t *info = pinfo;
1136     struct ucontext *uc = puc;
1137     unsigned long ip;
1138     int is_write = 0;
1139
1140     ip = uc->uc_mcontext.sc_ip;
1141     switch (host_signum) {
1142       case SIGILL:
1143       case SIGFPE:
1144       case SIGSEGV:
1145       case SIGBUS:
1146       case SIGTRAP:
1147           if (info->si_code && (info->si_segvflags & __ISR_VALID))
1148               /* ISR.W (write-access) is bit 33:  */
1149               is_write = (info->si_isr >> 33) & 1;
1150           break;
1151
1152       default:
1153           break;
1154     }
1155     return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1156                              is_write,
1157                              (sigset_t *)&uc->uc_sigmask, puc);
1158 }
1159
1160 #elif defined(__s390__)
1161
1162 int cpu_signal_handler(int host_signum, void *pinfo,
1163                        void *puc)
1164 {
1165     siginfo_t *info = pinfo;
1166     struct ucontext *uc = puc;
1167     unsigned long pc;
1168     uint16_t *pinsn;
1169     int is_write = 0;
1170
1171     pc = uc->uc_mcontext.psw.addr;
1172
1173     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
1174        of the normal 2 arguments.  The 3rd argument contains the "int_code"
1175        from the hardware which does in fact contain the is_write value.
1176        The rt signal handler, as far as I can tell, does not give this value
1177        at all.  Not that we could get to it from here even if it were.  */
1178     /* ??? This is not even close to complete, since it ignores all
1179        of the read-modify-write instructions.  */
1180     pinsn = (uint16_t *)pc;
1181     switch (pinsn[0] >> 8) {
1182     case 0x50: /* ST */
1183     case 0x42: /* STC */
1184     case 0x40: /* STH */
1185         is_write = 1;
1186         break;
1187     case 0xc4: /* RIL format insns */
1188         switch (pinsn[0] & 0xf) {
1189         case 0xf: /* STRL */
1190         case 0xb: /* STGRL */
1191         case 0x7: /* STHRL */
1192             is_write = 1;
1193         }
1194         break;
1195     case 0xe3: /* RXY format insns */
1196         switch (pinsn[2] & 0xff) {
1197         case 0x50: /* STY */
1198         case 0x24: /* STG */
1199         case 0x72: /* STCY */
1200         case 0x70: /* STHY */
1201         case 0x8e: /* STPQ */
1202         case 0x3f: /* STRVH */
1203         case 0x3e: /* STRV */
1204         case 0x2f: /* STRVG */
1205             is_write = 1;
1206         }
1207         break;
1208     }
1209     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1210                              is_write, &uc->uc_sigmask, puc);
1211 }
1212
1213 #elif defined(__mips__)
1214
1215 int cpu_signal_handler(int host_signum, void *pinfo,
1216                        void *puc)
1217 {
1218     siginfo_t *info = pinfo;
1219     struct ucontext *uc = puc;
1220     greg_t pc = uc->uc_mcontext.pc;
1221     int is_write;
1222
1223     /* XXX: compute is_write */
1224     is_write = 0;
1225     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1226                              is_write, &uc->uc_sigmask, puc);
1227 }
1228
1229 #elif defined(__hppa__)
1230
1231 int cpu_signal_handler(int host_signum, void *pinfo,
1232                        void *puc)
1233 {
1234     struct siginfo *info = pinfo;
1235     struct ucontext *uc = puc;
1236     unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
1237     uint32_t insn = *(uint32_t *)pc;
1238     int is_write = 0;
1239
1240     /* XXX: need kernel patch to get write flag faster.  */
1241     switch (insn >> 26) {
1242     case 0x1a: /* STW */
1243     case 0x19: /* STH */
1244     case 0x18: /* STB */
1245     case 0x1b: /* STWM */
1246         is_write = 1;
1247         break;
1248
1249     case 0x09: /* CSTWX, FSTWX, FSTWS */
1250     case 0x0b: /* CSTDX, FSTDX, FSTDS */
1251         /* Distinguish from coprocessor load ... */
1252         is_write = (insn >> 9) & 1;
1253         break;
1254
1255     case 0x03:
1256         switch ((insn >> 6) & 15) {
1257         case 0xa: /* STWS */
1258         case 0x9: /* STHS */
1259         case 0x8: /* STBS */
1260         case 0xe: /* STWAS */
1261         case 0xc: /* STBYS */
1262             is_write = 1;
1263         }
1264         break;
1265     }
1266
1267     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1268                              is_write, &uc->uc_sigmask, puc);
1269 }
1270
1271 #else
1272
1273 #error host CPU specific signal handler needed
1274
1275 #endif
1276
1277 #endif /* !defined(CONFIG_SOFTMMU) */