hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8
   9 struct kvm_irq_routing_entry;
  10
  11 /* PCI includes legacy ISA access.  */
  12 #include "isa.h"
  13
  14 /* PCI bus */
  15
  16 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  17 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  18 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  19 #define PCI_FUNC_MAX            8
  20
  21 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  22 #include "pci_ids.h"
  23
  24 /* QEMU-specific Vendor and Device ID definitions */
  25
  26 /* IBM (0x1014) */
  27 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  28 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  29
  30 /* Hitachi (0x1054) */
  31 #define PCI_VENDOR_ID_HITACHI            0x1054
  32 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  33
  34 /* Apple (0x106b) */
  35 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  36 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  37 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  39 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  40
  41 /* Realtek (0x10ec) */
  42 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  43
  44 /* Xilinx (0x10ee) */
  45 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  46
  47 /* Marvell (0x11ab) */
  48 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  49
  50 /* QEMU/Bochs VGA (0x1234) */
  51 #define PCI_VENDOR_ID_QEMU               0x1234
  52 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  53
  54 /* VMWare (0x15ad) */
  55 #define PCI_VENDOR_ID_VMWARE             0x15ad
  56 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  57 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  58 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  59 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  60 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  61
  62 /* Intel (0x8086) */
  63 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  64 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  65
  66 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  67 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  68 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  69 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  70
  71 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  72 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  73 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  74 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  75
  76 #define FMT_PCIBUS                      PRIx64
  77
  78 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  79                                 uint32_t address, uint32_t data, int len);
  80 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  81                                    uint32_t address, int len);
  82 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  83                                 pcibus_t addr, pcibus_t size, int type);
  84 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  85
  86 typedef void PCICapConfigWriteFunc(PCIDevice *pci_dev,
  87                                    uint32_t address, uint32_t val, int len);
  88 typedef uint32_t PCICapConfigReadFunc(PCIDevice *pci_dev,
  89                                       uint32_t address, int len);
  90 typedef int PCICapConfigInitFunc(PCIDevice *pci_dev);
  91
  92 typedef struct PCIIORegion {
  93     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  94 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  95     pcibus_t size;
  96     pcibus_t filtered_size;
  97     uint8_t type;
  98     PCIMapIORegionFunc *map_func;
  99 } PCIIORegion;
 100
 101 #define PCI_ROM_SLOT 6
 102 #define PCI_NUM_REGIONS 7
 103
 104 #include "pci_regs.h"
 105
 106 /* PCI HEADER_TYPE */
 107 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 108
 109 /* Size of the standard PCI config header */
 110 #define PCI_CONFIG_HEADER_SIZE 0x40
 111 /* Size of the standard PCI config space */
 112 #define PCI_CONFIG_SPACE_SIZE 0x100
 113 /* Size of the standart PCIe config space: 4KB */
 114 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 115
 116 #define PCI_NUM_PINS 4 /* A-D */
 117
 118 /* Bits in cap_present field. */
 119 enum {
 120     QEMU_PCI_CAP_MSIX = 0x1,
 121     QEMU_PCI_CAP_EXPRESS = 0x2,
 122
 123     /* multifunction capable device */
 124 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        2
 125     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 126 };
 127
 128 #define PCI_CAPABILITY_CONFIG_MAX_LENGTH 0x60
 129 #define PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR 0x40
 130 #define PCI_CAPABILITY_CONFIG_MSI_LENGTH 0x10
 131 #define PCI_CAPABILITY_CONFIG_MSIX_LENGTH 0x10
 132
 133 typedef int (*msix_mask_notifier_func)(PCIDevice *, unsigned vector,
 134                                        int masked);
 135
 136 struct kvm_msix_message {
 137     uint32_t gsi;
 138     uint32_t addr_lo;
 139     uint32_t addr_hi;
 140     uint32_t data;
 141 };
 142
 143 struct PCIDevice {
 144     DeviceState qdev;
 145     /* PCI config space */
 146     uint8_t *config;
 147
 148     /* Used to enable config checks on load. Note that writeable bits are
 149      * never checked even if set in cmask. */
 150     uint8_t *cmask;
 151
 152     /* Used to implement R/W bytes */
 153     uint8_t *wmask;
 154
 155     /* Used to allocate config space for capabilities. */
 156     uint8_t *used;
 157
 158     /* the following fields are read only */
 159     PCIBus *bus;
 160     uint32_t devfn;
 161     char name[64];
 162     PCIIORegion io_regions[PCI_NUM_REGIONS];
 163
 164     /* do not access the following fields */
 165     PCIConfigReadFunc *config_read;
 166     PCIConfigWriteFunc *config_write;
 167
 168     /* IRQ objects for the INTA-INTD pins.  */
 169     qemu_irq *irq;
 170
 171     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 172     uint8_t irq_state;
 173
 174     /* Capability bits */
 175     uint32_t cap_present;
 176
 177     /* Offset of MSI-X capability in config space */
 178     uint8_t msix_cap;
 179
 180     /* MSI-X entries */
 181     int msix_entries_nr;
 182
 183     /* Space to store MSIX table */
 184     uint8_t *msix_table_page;
 185     /* MMIO index used to map MSIX table and pending bit entries. */
 186     int msix_mmio_index;
 187     /* Reference-count for entries actually in use by driver. */
 188     unsigned *msix_entry_used;
 189     /* Region including the MSI-X table */
 190     uint32_t msix_bar_size;
 191     /* Version id needed for VMState */
 192     int32_t version_id;
 193
 194     /* Location of option rom */
 195     char *romfile;
 196     ram_addr_t rom_offset;
 197     uint32_t rom_bar;
 198
 199     /* How much space does an MSIX table need. */
 200     /* The spec requires giving the table structure
 201      * a 4K aligned region all by itself. Align it to
 202      * target pages so that drivers can do passthrough
 203      * on the rest of the region. */
 204     target_phys_addr_t msix_page_size;
 205
 206     struct kvm_msix_message *msix_irq_entries;
 207
 208     msix_mask_notifier_func msix_mask_notifier;
 209
 210     /* Device capability configuration space */
 211     struct {
 212         int supported;
 213         unsigned int start, length;
 214         PCICapConfigReadFunc *config_read;
 215         PCICapConfigWriteFunc *config_write;
 216     } cap;
 217 };
 218
 219 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 220                                int instance_size, int devfn,
 221                                PCIConfigReadFunc *config_read,
 222                                PCIConfigWriteFunc *config_write);
 223
 224 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 225                             pcibus_t size, int type,
 226                             PCIMapIORegionFunc *map_func);
 227
 228 void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr,
 229                         pcibus_t size, int type);
 230
 231 int pci_enable_capability_support(PCIDevice *pci_dev,
 232                                   uint32_t config_start,
 233                                   PCICapConfigReadFunc *config_read,
 234                                   PCICapConfigWriteFunc *config_write,
 235                                   PCICapConfigInitFunc *config_init);
 236
 237 int pci_map_irq(PCIDevice *pci_dev, int pin);
 238
 239 int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 240 int pci_add_capability_at_offset(PCIDevice *pci_dev, uint8_t cap_id,
 241                                  uint8_t cap_offset, uint8_t cap_size);
 242
 243 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 244
 245 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 246
 247 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 248
 249 uint32_t pci_default_read_config(PCIDevice *d,
 250                                  uint32_t address, int len);
 251 void pci_default_write_config(PCIDevice *d,
 252                               uint32_t address, uint32_t val, int len);
 253 void pci_device_save(PCIDevice *s, QEMUFile *f);
 254 int pci_device_load(PCIDevice *s, QEMUFile *f);
 255 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 256                                      uint32_t address, int len);
 257 void pci_default_cap_write_config(PCIDevice *pci_dev,
 258                                   uint32_t address, uint32_t val, int len);
 259 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len);
 260
 261 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 262 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 263 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, int state);
 264 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 265                          const char *name, int devfn_min);
 266 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 267 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 268                   void *irq_opaque, int nirq);
 269 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 270 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 271                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 272                          void *irq_opaque, int devfn_min, int nirq);
 273
 274 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 275
 276 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 277                         const char *default_devaddr);
 278 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 279                                const char *default_devaddr);
 280 int pci_bus_num(PCIBus *s);
 281 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 282 PCIBus *pci_find_root_bus(int domain);
 283 int pci_find_domain(const PCIBus *bus);
 284 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 285 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
 286 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 287
 288 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 289                      unsigned *slotp);
 290
 291 int pci_parse_host_devaddr(const char *addr, int *segp, int *busp,
 292                            int *slotp, int *funcp);
 293
 294 void do_pci_info_print(Monitor *mon, const QObject *data);
 295 void do_pci_info(Monitor *mon, QObject **ret_data);
 296 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, bool multifunction,
 297                         uint16_t vid, uint16_t did,
 298                         pci_map_irq_fn map_irq, const char *name);
 299 PCIDevice *pci_bridge_get_device(PCIBus *bus);
 300
 301 static inline void
 302 pci_set_byte(uint8_t *config, uint8_t val)
 303 {
 304     *config = val;
 305 }
 306
 307 static inline uint8_t
 308 pci_get_byte(const uint8_t *config)
 309 {
 310     return *config;
 311 }
 312
 313 static inline void
 314 pci_set_word(uint8_t *config, uint16_t val)
 315 {
 316     cpu_to_le16wu((uint16_t *)config, val);
 317 }
 318
 319 static inline uint16_t
 320 pci_get_word(const uint8_t *config)
 321 {
 322     return le16_to_cpupu((const uint16_t *)config);
 323 }
 324
 325 static inline void
 326 pci_set_long(uint8_t *config, uint32_t val)
 327 {
 328     cpu_to_le32wu((uint32_t *)config, val);
 329 }
 330
 331 static inline uint32_t
 332 pci_get_long(const uint8_t *config)
 333 {
 334     return le32_to_cpupu((const uint32_t *)config);
 335 }
 336
 337 static inline void
 338 pci_set_quad(uint8_t *config, uint64_t val)
 339 {
 340     cpu_to_le64w((uint64_t *)config, val);
 341 }
 342
 343 static inline uint64_t
 344 pci_get_quad(const uint8_t *config)
 345 {
 346     return le64_to_cpup((const uint64_t *)config);
 347 }
 348
 349 static inline void
 350 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 351 {
 352     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 353 }
 354
 355 static inline void
 356 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 357 {
 358     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 359 }
 360
 361 static inline void
 362 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 363 {
 364     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 365 }
 366
 367 static inline void
 368 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 369 {
 370     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 371 }
 372
 373 static inline void
 374 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 375 {
 376     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 377 }
 378
 379 static inline void
 380 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 381 {
 382     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 383 }
 384
 385 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 386 typedef struct {
 387     DeviceInfo qdev;
 388     pci_qdev_initfn init;
 389     PCIUnregisterFunc *exit;
 390     PCIConfigReadFunc *config_read;
 391     PCIConfigWriteFunc *config_write;
 392
 393     /*
 394      * pci-to-pci bridge or normal device.
 395      * This doesn't mean pci host switch.
 396      * When card bus bridge is supported, this would be enhanced.
 397      */
 398     int is_bridge;
 399
 400     /* pcie stuff */
 401     int is_express;   /* is this device pci express? */
 402
 403     /* rom bar */
 404     const char *romfile;
 405 } PCIDeviceInfo;
 406
 407 void pci_qdev_register(PCIDeviceInfo *info);
 408 void pci_qdev_register_many(PCIDeviceInfo *info);
 409
 410 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 411                                     const char *name);
 412 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 413                                            bool multifunction,
 414                                            const char *name);
 415 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 416 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 417
 418 static inline int pci_is_express(const PCIDevice *d)
 419 {
 420     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 421 }
 422
 423 static inline uint32_t pci_config_size(const PCIDevice *d)
 424 {
 425     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 426 }
 427
 428 #endif