hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32
  33 //#define HPET_DEBUG
  34 #ifdef HPET_DEBUG
  35 #define dprintf printf
  36 #else
  37 #define dprintf(...)
  38 #endif
  39
  40 static HPETState *hpet_statep;
  41
  42 uint32_t hpet_in_legacy_mode(void)
  43 {
  44     if (hpet_statep)
  45         return hpet_statep->config & HPET_CFG_LEGACY;
  46     else
  47         return 0;
  48 }
  49
  50 static uint32_t timer_int_route(struct HPETTimer *timer)
  51 {
  52     uint32_t route;
  53     route = (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  54     return route;
  55 }
  56
  57 static uint32_t hpet_enabled(void)
  58 {
  59     return hpet_statep->config & HPET_CFG_ENABLE;
  60 }
  61
  62 static uint32_t timer_is_periodic(HPETTimer *t)
  63 {
  64     return t->config & HPET_TN_PERIODIC;
  65 }
  66
  67 static uint32_t timer_enabled(HPETTimer *t)
  68 {
  69     return t->config & HPET_TN_ENABLE;
  70 }
  71
  72 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
  73 {
  74     return ((int32_t)(b) - (int32_t)(a) < 0);
  75 }
  76
  77 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
  78 {
  79     return ((int64_t)(b) - (int64_t)(a) < 0);
  80 }
  81
  82 static uint64_t ticks_to_ns(uint64_t value)
  83 {
  84     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
  85 }
  86
  87 static uint64_t ns_to_ticks(uint64_t value)
  88 {
  89     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
  90 }
  91
  92 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
  93 {
  94     new &= mask;
  95     new |= old & ~mask;
  96     return new;
  97 }
  98
  99 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 100 {
 101     return (!(old & mask) && (new & mask));
 102 }
 103
 104 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 105 {
 106     return ((old & mask) && !(new & mask));
 107 }
 108
 109 static uint64_t hpet_get_ticks(void)
 110 {
 111     uint64_t ticks;
 112     ticks = ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
 113     return ticks;
 114 }
 115
 116 /*
 117  * calculate diff between comparator value and current ticks
 118  */
 119 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 120 {
 121
 122     if (t->config & HPET_TN_32BIT) {
 123         uint32_t diff, cmp;
 124         cmp = (uint32_t)t->cmp;
 125         diff = cmp - (uint32_t)current;
 126         diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
 127         return (uint64_t)diff;
 128     } else {
 129         uint64_t diff, cmp;
 130         cmp = t->cmp;
 131         diff = cmp - current;
 132         diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
 133         return diff;
 134     }
 135 }
 136
 137 static void update_irq(struct HPETTimer *timer)
 138 {
 139     qemu_irq irq;
 140     int route;
 141
 142     if (timer->tn <= 1 && hpet_in_legacy_mode()) {
 143         /* if LegacyReplacementRoute bit is set, HPET specification requires
 144          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 145          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 146          */
 147         if (timer->tn == 0) {
 148             irq=timer->state->irqs[0];
 149         } else
 150             irq=timer->state->irqs[8];
 151     } else {
 152         route=timer_int_route(timer);
 153         irq=timer->state->irqs[route];
 154     }
 155     if (timer_enabled(timer) && hpet_enabled()) {
 156         qemu_irq_pulse(irq);
 157     }
 158 }
 159
 160 static void hpet_pre_save(void *opaque)
 161 {
 162     HPETState *s = opaque;
 163     /* save current counter value */
 164     s->hpet_counter = hpet_get_ticks();
 165 }
 166
 167 static int hpet_post_load(void *opaque, int version_id)
 168 {
 169     HPETState *s = opaque;
 170
 171     /* Recalculate the offset between the main counter and guest time */
 172     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 173
 174     if (hpet_in_legacy_mode()) {
 175         hpet_disable_pit();
 176     }
 177
 178     return 0;
 179 }
 180
 181 static const VMStateDescription vmstate_hpet_timer = {
 182     .name = "hpet_timer",
 183     .version_id = 1,
 184     .minimum_version_id = 1,
 185     .minimum_version_id_old = 1,
 186     .fields      = (VMStateField []) {
 187         VMSTATE_UINT8(tn, HPETTimer),
 188         VMSTATE_UINT64(config, HPETTimer),
 189         VMSTATE_UINT64(cmp, HPETTimer),
 190         VMSTATE_UINT64(fsb, HPETTimer),
 191         VMSTATE_UINT64(period, HPETTimer),
 192         VMSTATE_UINT8(wrap_flag, HPETTimer),
 193         VMSTATE_TIMER(qemu_timer, HPETTimer),
 194         VMSTATE_END_OF_LIST()
 195     }
 196 };
 197
 198 static const VMStateDescription vmstate_hpet = {
 199     .name = "hpet",
 200     .version_id = 1,
 201     .minimum_version_id = 1,
 202     .minimum_version_id_old = 1,
 203     .pre_save = hpet_pre_save,
 204     .post_load = hpet_post_load,
 205     .fields      = (VMStateField []) {
 206         VMSTATE_UINT64(config, HPETState),
 207         VMSTATE_UINT64(isr, HPETState),
 208         VMSTATE_UINT64(hpet_counter, HPETState),
 209         VMSTATE_STRUCT_ARRAY(timer, HPETState, HPET_NUM_TIMERS, 0,
 210                              vmstate_hpet_timer, HPETTimer),
 211         VMSTATE_END_OF_LIST()
 212     }
 213 };
 214
 215 /*
 216  * timer expiration callback
 217  */
 218 static void hpet_timer(void *opaque)
 219 {
 220     HPETTimer *t = (HPETTimer*)opaque;
 221     uint64_t diff;
 222
 223     uint64_t period = t->period;
 224     uint64_t cur_tick = hpet_get_ticks();
 225
 226     if (timer_is_periodic(t) && period != 0) {
 227         if (t->config & HPET_TN_32BIT) {
 228             while (hpet_time_after(cur_tick, t->cmp))
 229                 t->cmp = (uint32_t)(t->cmp + t->period);
 230         } else
 231             while (hpet_time_after64(cur_tick, t->cmp))
 232                 t->cmp += period;
 233
 234         diff = hpet_calculate_diff(t, cur_tick);
 235         qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
 236                        + (int64_t)ticks_to_ns(diff));
 237     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 238         if (t->wrap_flag) {
 239             diff = hpet_calculate_diff(t, cur_tick);
 240             qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
 241                            + (int64_t)ticks_to_ns(diff));
 242             t->wrap_flag = 0;
 243         }
 244     }
 245     update_irq(t);
 246 }
 247
 248 static void hpet_set_timer(HPETTimer *t)
 249 {
 250     uint64_t diff;
 251     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 252     uint64_t cur_tick = hpet_get_ticks();
 253
 254     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 255     t->wrap_flag = 0;
 256     diff = hpet_calculate_diff(t, cur_tick);
 257
 258     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 259      * counter wraps in addition to an interrupt with comparator match.
 260      */
 261     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 262         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 263         if (wrap_diff < (uint32_t)diff) {
 264             diff = wrap_diff;
 265             t->wrap_flag = 1;
 266         }
 267     }
 268     qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
 269                    + (int64_t)ticks_to_ns(diff));
 270 }
 271
 272 static void hpet_del_timer(HPETTimer *t)
 273 {
 274     qemu_del_timer(t->qemu_timer);
 275 }
 276
 277 #ifdef HPET_DEBUG
 278 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 279 {
 280     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 281     return 0;
 282 }
 283
 284 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 285 {
 286     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 287     return 0;
 288 }
 289 #endif
 290
 291 static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
 292 {
 293     HPETState *s = (HPETState *)opaque;
 294     uint64_t cur_tick, index;
 295
 296     dprintf("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 297     index = addr;
 298     /*address range of all TN regs*/
 299     if (index >= 0x100 && index <= 0x3ff) {
 300         uint8_t timer_id = (addr - 0x100) / 0x20;
 301         if (timer_id > HPET_NUM_TIMERS - 1) {
 302             printf("qemu: timer id out of range\n");
 303             return 0;
 304         }
 305         HPETTimer *timer = &s->timer[timer_id];
 306
 307         switch ((addr - 0x100) % 0x20) {
 308             case HPET_TN_CFG:
 309                 return timer->config;
 310             case HPET_TN_CFG + 4: // Interrupt capabilities
 311                 return timer->config >> 32;
 312             case HPET_TN_CMP: // comparator register
 313                 return timer->cmp;
 314             case HPET_TN_CMP + 4:
 315                 return timer->cmp >> 32;
 316             case HPET_TN_ROUTE:
 317                 return timer->fsb >> 32;
 318             default:
 319                 dprintf("qemu: invalid hpet_ram_readl\n");
 320                 break;
 321         }
 322     } else {
 323         switch (index) {
 324             case HPET_ID:
 325                 return s->capability;
 326             case HPET_PERIOD:
 327                 return s->capability >> 32;
 328             case HPET_CFG:
 329                 return s->config;
 330             case HPET_CFG + 4:
 331                 dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
 332                 return 0;
 333             case HPET_COUNTER:
 334                 if (hpet_enabled())
 335                     cur_tick = hpet_get_ticks();
 336                 else
 337                     cur_tick = s->hpet_counter;
 338                 dprintf("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 339                 return cur_tick;
 340             case HPET_COUNTER + 4:
 341                 if (hpet_enabled())
 342                     cur_tick = hpet_get_ticks();
 343                 else
 344                     cur_tick = s->hpet_counter;
 345                 dprintf("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 346                 return cur_tick >> 32;
 347             case HPET_STATUS:
 348                 return s->isr;
 349             default:
 350                 dprintf("qemu: invalid hpet_ram_readl\n");
 351                 break;
 352         }
 353     }
 354     return 0;
 355 }
 356
 357 #ifdef HPET_DEBUG
 358 static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
 359                             uint32_t value)
 360 {
 361     printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
 362            addr, value);
 363 }
 364
 365 static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
 366                             uint32_t value)
 367 {
 368     printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
 369            addr, value);
 370 }
 371 #endif
 372
 373 static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
 374                             uint32_t value)
 375 {
 376     int i;
 377     HPETState *s = (HPETState *)opaque;
 378     uint64_t old_val, new_val, val, index;
 379
 380     dprintf("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 381     index = addr;
 382     old_val = hpet_ram_readl(opaque, addr);
 383     new_val = value;
 384
 385     /*address range of all TN regs*/
 386     if (index >= 0x100 && index <= 0x3ff) {
 387         uint8_t timer_id = (addr - 0x100) / 0x20;
 388         dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
 389         HPETTimer *timer = &s->timer[timer_id];
 390
 391         switch ((addr - 0x100) % 0x20) {
 392             case HPET_TN_CFG:
 393                 dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
 394                 val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 395                 timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 396                 if (new_val & HPET_TN_32BIT) {
 397                     timer->cmp = (uint32_t)timer->cmp;
 398                     timer->period = (uint32_t)timer->period;
 399                 }
 400                 if (new_val & HPET_TIMER_TYPE_LEVEL) {
 401                     printf("qemu: level-triggered hpet not supported\n");
 402                     exit (-1);
 403                 }
 404
 405                 break;
 406             case HPET_TN_CFG + 4: // Interrupt capabilities
 407                 dprintf("qemu: invalid HPET_TN_CFG+4 write\n");
 408                 break;
 409             case HPET_TN_CMP: // comparator register
 410                 dprintf("qemu: hpet_ram_writel HPET_TN_CMP \n");
 411                 if (timer->config & HPET_TN_32BIT)
 412                     new_val = (uint32_t)new_val;
 413                 if (!timer_is_periodic(timer) ||
 414                            (timer->config & HPET_TN_SETVAL))
 415                     timer->cmp = (timer->cmp & 0xffffffff00000000ULL)
 416                                   | new_val;
 417                 if (timer_is_periodic(timer)) {
 418                     /*
 419                      * FIXME: Clamp period to reasonable min value?
 420                      * Clamp period to reasonable max value
 421                      */
 422                     new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 423                     timer->period = (timer->period & 0xffffffff00000000ULL)
 424                                      | new_val;
 425                 }
 426                 timer->config &= ~HPET_TN_SETVAL;
 427                 if (hpet_enabled())
 428                     hpet_set_timer(timer);
 429                 break;
 430             case HPET_TN_CMP + 4: // comparator register high order
 431                 dprintf("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 432                 if (!timer_is_periodic(timer) ||
 433                            (timer->config & HPET_TN_SETVAL))
 434                     timer->cmp = (timer->cmp & 0xffffffffULL)
 435                                   | new_val << 32;
 436                 else {
 437                     /*
 438                      * FIXME: Clamp period to reasonable min value?
 439                      * Clamp period to reasonable max value
 440                      */
 441                     new_val &= (timer->config
 442                                 & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 443                     timer->period = (timer->period & 0xffffffffULL)
 444                                      | new_val << 32;
 445                 }
 446                 timer->config &= ~HPET_TN_SETVAL;
 447                 if (hpet_enabled())
 448                     hpet_set_timer(timer);
 449                 break;
 450             case HPET_TN_ROUTE + 4:
 451                 dprintf("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
 452                 break;
 453             default:
 454                 dprintf("qemu: invalid hpet_ram_writel\n");
 455                 break;
 456         }
 457         return;
 458     } else {
 459         switch (index) {
 460             case HPET_ID:
 461                 return;
 462             case HPET_CFG:
 463                 val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 464                 s->config = (s->config & 0xffffffff00000000ULL) | val;
 465                 if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 466                     /* Enable main counter and interrupt generation. */
 467                     s->hpet_offset = ticks_to_ns(s->hpet_counter)
 468                                      - qemu_get_clock(vm_clock);
 469                     for (i = 0; i < HPET_NUM_TIMERS; i++)
 470                         if ((&s->timer[i])->cmp != ~0ULL)
 471                             hpet_set_timer(&s->timer[i]);
 472                 }
 473                 else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 474                     /* Halt main counter and disable interrupt generation. */
 475                     s->hpet_counter = hpet_get_ticks();
 476                     for (i = 0; i < HPET_NUM_TIMERS; i++)
 477                         hpet_del_timer(&s->timer[i]);
 478                 }
 479                 /* i8254 and RTC are disabled when HPET is in legacy mode */
 480                 if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 481                     hpet_disable_pit();
 482                     dprintf("qemu: hpet disabled pit\n");
 483                 } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 484                     hpet_enable_pit();
 485                     dprintf("qemu: hpet enabled pit\n");
 486                 }
 487                 break;
 488             case HPET_CFG + 4:
 489                 dprintf("qemu: invalid HPET_CFG+4 write \n");
 490                 break;
 491             case HPET_STATUS:
 492                 /* FIXME: need to handle level-triggered interrupts */
 493                 break;
 494             case HPET_COUNTER:
 495                if (hpet_enabled())
 496                    printf("qemu: Writing counter while HPET enabled!\n");
 497                s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
 498                                   | value;
 499                dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 500                         value, s->hpet_counter);
 501                break;
 502             case HPET_COUNTER + 4:
 503                if (hpet_enabled())
 504                    printf("qemu: Writing counter while HPET enabled!\n");
 505                s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
 506                                   | (((uint64_t)value) << 32);
 507                dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 508                         value, s->hpet_counter);
 509                break;
 510             default:
 511                dprintf("qemu: invalid hpet_ram_writel\n");
 512                break;
 513         }
 514     }
 515 }
 516
 517 static CPUReadMemoryFunc * const hpet_ram_read[] = {
 518 #ifdef HPET_DEBUG
 519     hpet_ram_readb,
 520     hpet_ram_readw,
 521 #else
 522     NULL,
 523     NULL,
 524 #endif
 525     hpet_ram_readl,
 526 };
 527
 528 static CPUWriteMemoryFunc * const hpet_ram_write[] = {
 529 #ifdef HPET_DEBUG
 530     hpet_ram_writeb,
 531     hpet_ram_writew,
 532 #else
 533     NULL,
 534     NULL,
 535 #endif
 536     hpet_ram_writel,
 537 };
 538
 539 static void hpet_reset(void *opaque) {
 540     HPETState *s = opaque;
 541     int i;
 542     static int count = 0;
 543
 544     for (i=0; i<HPET_NUM_TIMERS; i++) {
 545         HPETTimer *timer = &s->timer[i];
 546         hpet_del_timer(timer);
 547         timer->tn = i;
 548         timer->cmp = ~0ULL;
 549         timer->config =  HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 550         /* advertise availability of ioapic inti2 */
 551         timer->config |=  0x00000004ULL << 32;
 552         timer->state = s;
 553         timer->period = 0ULL;
 554         timer->wrap_flag = 0;
 555     }
 556
 557     s->hpet_counter = 0ULL;
 558     s->hpet_offset = 0ULL;
 559     /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
 560     s->capability = 0x8086a201ULL;
 561     s->capability |= ((HPET_CLK_PERIOD) << 32);
 562     s->config = 0ULL;
 563     if (count > 0)
 564         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 565          * because hpet is taking over for pit here. On subsequent invocations,
 566          * hpet_reset is called due to system reset. At this point control must
 567          * be returned to pit until SW reenables hpet.
 568          */
 569         hpet_enable_pit();
 570     count = 1;
 571 }
 572
 573
 574 void hpet_init(qemu_irq *irq) {
 575     int i, iomemtype;
 576     HPETState *s;
 577
 578     dprintf ("hpet_init\n");
 579
 580     s = qemu_mallocz(sizeof(HPETState));
 581     hpet_statep = s;
 582     s->irqs = irq;
 583     for (i=0; i<HPET_NUM_TIMERS; i++) {
 584         HPETTimer *timer = &s->timer[i];
 585         timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
 586     }
 587     hpet_reset(s);
 588     vmstate_register(-1, &vmstate_hpet, s);
 589     qemu_register_reset(hpet_reset, s);
 590     /* HPET Area */
 591     iomemtype = cpu_register_io_memory(hpet_ram_read,
 592                                        hpet_ram_write, s);
 593     cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
 594 }