Merge branch 'upstream-merge'
[qemu-kvm/markmc.git] / target-cris / mmu.c
blobb6892bbbf29d38eb3765d7a6f5fc0b1d60078703
1 /*
2 * CRIS mmu emulation.
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #ifndef CONFIG_USER_ONLY
23 #include <stdio.h>
24 #include <string.h>
25 #include <stdlib.h>
27 #include "config.h"
28 #include "cpu.h"
29 #include "mmu.h"
30 #include "exec-all.h"
32 #ifdef DEBUG
33 #define D(x) x
34 #define D_LOG(...) qemu_log(__VA__ARGS__)
35 #else
36 #define D(x)
37 #define D_LOG(...) do { } while (0)
38 #endif
40 void cris_mmu_init(CPUState *env)
42 env->mmu_rand_lfsr = 0xcccc;
45 #define SR_POLYNOM 0x8805
46 static inline unsigned int compute_polynom(unsigned int sr)
48 unsigned int i;
49 unsigned int f;
51 f = 0;
52 for (i = 0; i < 16; i++)
53 f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
55 return f;
58 static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
60 return (rw_gc_cfg & 12) != 0;
63 static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
65 return (1 << seg) & rw_mm_cfg;
68 static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
70 uint32_t base;
71 int i;
73 if (seg < 8)
74 base = env->sregs[SFR_RW_MM_KBASE_LO];
75 else
76 base = env->sregs[SFR_RW_MM_KBASE_HI];
78 i = seg & 7;
79 base >>= i * 4;
80 base &= 15;
82 base <<= 28;
83 return base;
85 /* Used by the tlb decoder. */
86 #define EXTRACT_FIELD(src, start, end) \
87 (((src) >> start) & ((1 << (end - start + 1)) - 1))
89 static inline void set_field(uint32_t *dst, unsigned int val,
90 unsigned int offset, unsigned int width)
92 uint32_t mask;
94 mask = (1 << width) - 1;
95 mask <<= offset;
96 val <<= offset;
98 val &= mask;
99 *dst &= ~(mask);
100 *dst |= val;
103 #ifdef DEBUG
104 static void dump_tlb(CPUState *env, int mmu)
106 int set;
107 int idx;
108 uint32_t hi, lo, tlb_vpn, tlb_pfn;
110 for (set = 0; set < 4; set++) {
111 for (idx = 0; idx < 16; idx++) {
112 lo = env->tlbsets[mmu][set][idx].lo;
113 hi = env->tlbsets[mmu][set][idx].hi;
114 tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
115 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
117 printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
118 set, idx, hi, lo, tlb_vpn, tlb_pfn);
122 #endif
124 /* rw 0 = read, 1 = write, 2 = exec. */
125 static int cris_mmu_translate_page(struct cris_mmu_result *res,
126 CPUState *env, uint32_t vaddr,
127 int rw, int usermode)
129 unsigned int vpage;
130 unsigned int idx;
131 uint32_t pid, lo, hi;
132 uint32_t tlb_vpn, tlb_pfn = 0;
133 int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
134 int cfg_v, cfg_k, cfg_w, cfg_x;
135 int set, match = 0;
136 uint32_t r_cause;
137 uint32_t r_cfg;
138 int rwcause;
139 int mmu = 1; /* Data mmu is default. */
140 int vect_base;
142 r_cause = env->sregs[SFR_R_MM_CAUSE];
143 r_cfg = env->sregs[SFR_RW_MM_CFG];
144 pid = env->pregs[PR_PID] & 0xff;
146 switch (rw) {
147 case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
148 case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
149 default:
150 case 0: rwcause = CRIS_MMU_ERR_READ; break;
153 /* I exception vectors 4 - 7, D 8 - 11. */
154 vect_base = (mmu + 1) * 4;
156 vpage = vaddr >> 13;
158 /* We know the index which to check on each set.
159 Scan both I and D. */
160 #if 0
161 for (set = 0; set < 4; set++) {
162 for (idx = 0; idx < 16; idx++) {
163 lo = env->tlbsets[mmu][set][idx].lo;
164 hi = env->tlbsets[mmu][set][idx].hi;
165 tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
166 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
168 printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
169 set, idx, hi, lo, tlb_vpn, tlb_pfn);
172 #endif
174 idx = vpage & 15;
175 for (set = 0; set < 4; set++)
177 lo = env->tlbsets[mmu][set][idx].lo;
178 hi = env->tlbsets[mmu][set][idx].hi;
180 tlb_vpn = hi >> 13;
181 tlb_pid = EXTRACT_FIELD(hi, 0, 7);
182 tlb_g = EXTRACT_FIELD(lo, 4, 4);
184 D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
185 mmu, set, idx, tlb_vpn, vpage, lo, hi);
186 if ((tlb_g || (tlb_pid == pid))
187 && tlb_vpn == vpage) {
188 match = 1;
189 break;
193 res->bf_vec = vect_base;
194 if (match) {
195 cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
196 cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
197 cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
198 cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
200 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
201 tlb_v = EXTRACT_FIELD(lo, 3, 3);
202 tlb_k = EXTRACT_FIELD(lo, 2, 2);
203 tlb_w = EXTRACT_FIELD(lo, 1, 1);
204 tlb_x = EXTRACT_FIELD(lo, 0, 0);
207 set_exception_vector(0x04, i_mmu_refill);
208 set_exception_vector(0x05, i_mmu_invalid);
209 set_exception_vector(0x06, i_mmu_access);
210 set_exception_vector(0x07, i_mmu_execute);
211 set_exception_vector(0x08, d_mmu_refill);
212 set_exception_vector(0x09, d_mmu_invalid);
213 set_exception_vector(0x0a, d_mmu_access);
214 set_exception_vector(0x0b, d_mmu_write);
216 if (cfg_k && tlb_k && usermode) {
217 D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
218 vaddr, lo, env->pc));
219 match = 0;
220 res->bf_vec = vect_base + 2;
221 } else if (rw == 1 && cfg_w && !tlb_w) {
222 D(printf ("tlb: write protected %x lo=%x pc=%x\n",
223 vaddr, lo, env->pc));
224 match = 0;
225 /* write accesses never go through the I mmu. */
226 res->bf_vec = vect_base + 3;
227 } else if (rw == 2 && cfg_x && !tlb_x) {
228 D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
229 vaddr, lo, env->pc));
230 match = 0;
231 res->bf_vec = vect_base + 3;
232 } else if (cfg_v && !tlb_v) {
233 D(printf ("tlb: invalid %x\n", vaddr));
234 match = 0;
235 res->bf_vec = vect_base + 1;
238 res->prot = 0;
239 if (match) {
240 res->prot |= PAGE_READ;
241 if (tlb_w)
242 res->prot |= PAGE_WRITE;
243 if (tlb_x)
244 res->prot |= PAGE_EXEC;
246 else
247 D(dump_tlb(env, mmu));
248 } else {
249 /* If refill, provide a randomized set. */
250 set = env->mmu_rand_lfsr & 3;
253 if (!match) {
254 unsigned int f;
256 /* Update lfsr at every fault. */
257 f = compute_polynom(env->mmu_rand_lfsr);
258 env->mmu_rand_lfsr >>= 1;
259 env->mmu_rand_lfsr |= (f << 15);
260 env->mmu_rand_lfsr &= 0xffff;
262 /* Compute index. */
263 idx = vpage & 15;
265 /* Update RW_MM_TLB_SEL. */
266 env->sregs[SFR_RW_MM_TLB_SEL] = 0;
267 set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
268 set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
270 /* Update RW_MM_CAUSE. */
271 set_field(&r_cause, rwcause, 8, 2);
272 set_field(&r_cause, vpage, 13, 19);
273 set_field(&r_cause, pid, 0, 8);
274 env->sregs[SFR_R_MM_CAUSE] = r_cause;
275 D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
278 D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
279 " %x cause=%x sel=%x sp=%x %x %x\n",
280 __func__, rw, match, env->pc,
281 vaddr, vpage,
282 tlb_vpn, tlb_pfn, tlb_pid,
283 pid,
284 r_cause,
285 env->sregs[SFR_RW_MM_TLB_SEL],
286 env->regs[R_SP], env->pregs[PR_USP], env->ksp));
288 res->phy = tlb_pfn << TARGET_PAGE_BITS;
289 return !match;
292 void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
294 target_ulong vaddr;
295 unsigned int idx;
296 uint32_t lo, hi;
297 uint32_t tlb_vpn;
298 int tlb_pid, tlb_g, tlb_v;
299 unsigned int set;
300 unsigned int mmu;
302 pid &= 0xff;
303 for (mmu = 0; mmu < 2; mmu++) {
304 for (set = 0; set < 4; set++)
306 for (idx = 0; idx < 16; idx++) {
307 lo = env->tlbsets[mmu][set][idx].lo;
308 hi = env->tlbsets[mmu][set][idx].hi;
310 tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
311 tlb_pid = EXTRACT_FIELD(hi, 0, 7);
312 tlb_g = EXTRACT_FIELD(lo, 4, 4);
313 tlb_v = EXTRACT_FIELD(lo, 3, 3);
315 if (tlb_v && !tlb_g && (tlb_pid == pid)) {
316 vaddr = tlb_vpn << TARGET_PAGE_BITS;
317 D_LOG("flush pid=%x vaddr=%x\n",
318 pid, vaddr);
319 tlb_flush_page(env, vaddr);
326 int cris_mmu_translate(struct cris_mmu_result *res,
327 CPUState *env, uint32_t vaddr,
328 int rw, int mmu_idx)
330 uint32_t phy = vaddr;
331 int seg;
332 int miss = 0;
333 int is_user = mmu_idx == MMU_USER_IDX;
334 uint32_t old_srs;
336 old_srs= env->pregs[PR_SRS];
338 /* rw == 2 means exec, map the access to the insn mmu. */
339 env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
341 if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
342 res->phy = vaddr;
343 res->prot = PAGE_BITS;
344 goto done;
347 seg = vaddr >> 28;
348 if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
350 uint32_t base;
352 miss = 0;
353 base = cris_mmu_translate_seg(env, seg);
354 phy = base | (0x0fffffff & vaddr);
355 res->phy = phy;
356 res->prot = PAGE_BITS;
358 else
359 miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user);
360 done:
361 env->pregs[PR_SRS] = old_srs;
362 return miss;
364 #endif