Merge branch 'upstream-merge'
[qemu-kvm/markmc.git] / hw / xilinx_uartlite.c
blobadab759fdbd5617b8511112cc56d4119f3581ae1
1 /*
2 * QEMU model of Xilinx uartlite.
4 * Copyright (c) 2009 Edgar E. Iglesias.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "sysbus.h"
26 #include "qemu-char.h"
28 #define DUART(x)
30 #define R_RX 0
31 #define R_TX 1
32 #define R_STATUS 2
33 #define R_CTRL 3
34 #define R_MAX 4
36 #define STATUS_RXVALID 0x01
37 #define STATUS_RXFULL 0x02
38 #define STATUS_TXEMPTY 0x04
39 #define STATUS_TXFULL 0x08
40 #define STATUS_IE 0x10
41 #define STATUS_OVERRUN 0x20
42 #define STATUS_FRAME 0x40
43 #define STATUS_PARITY 0x80
45 #define CONTROL_RST_TX 0x01
46 #define CONTROL_RST_RX 0x02
47 #define CONTROL_IE 0x10
49 struct xlx_uartlite
51 SysBusDevice busdev;
52 CharDriverState *chr;
53 qemu_irq irq;
55 uint8_t rx_fifo[8];
56 unsigned int rx_fifo_pos;
57 unsigned int rx_fifo_len;
59 uint32_t regs[R_MAX];
62 static void uart_update_irq(struct xlx_uartlite *s)
64 unsigned int irq;
66 if (s->rx_fifo_len)
67 s->regs[R_STATUS] |= STATUS_IE;
69 irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE);
70 qemu_set_irq(s->irq, irq);
73 static void uart_update_status(struct xlx_uartlite *s)
75 uint32_t r;
77 r = s->regs[R_STATUS];
78 r &= ~7;
79 r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */
80 r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1;
81 r |= (!!s->rx_fifo_len);
82 s->regs[R_STATUS] = r;
85 static uint32_t uart_readl (void *opaque, target_phys_addr_t addr)
87 struct xlx_uartlite *s = opaque;
88 uint32_t r = 0;
89 addr >>= 2;
90 switch (addr)
92 case R_RX:
93 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
94 if (s->rx_fifo_len)
95 s->rx_fifo_len--;
96 uart_update_status(s);
97 uart_update_irq(s);
98 break;
100 default:
101 if (addr < ARRAY_SIZE(s->regs))
102 r = s->regs[addr];
103 DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
104 break;
106 return r;
109 static void
110 uart_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
112 struct xlx_uartlite *s = opaque;
113 unsigned char ch = value;
115 addr >>= 2;
116 switch (addr)
118 case R_STATUS:
119 hw_error("write to UART STATUS?\n");
120 break;
122 case R_CTRL:
123 if (value & CONTROL_RST_RX) {
124 s->rx_fifo_pos = 0;
125 s->rx_fifo_len = 0;
127 s->regs[addr] = value;
128 break;
130 case R_TX:
131 if (s->chr)
132 qemu_chr_write(s->chr, &ch, 1);
134 s->regs[addr] = value;
136 /* hax. */
137 s->regs[R_STATUS] |= STATUS_IE;
138 break;
140 default:
141 DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
142 if (addr < ARRAY_SIZE(s->regs))
143 s->regs[addr] = value;
144 break;
146 uart_update_status(s);
147 uart_update_irq(s);
150 static CPUReadMemoryFunc * const uart_read[] = {
151 &uart_readl,
152 &uart_readl,
153 &uart_readl,
156 static CPUWriteMemoryFunc * const uart_write[] = {
157 &uart_writel,
158 &uart_writel,
159 &uart_writel,
162 static void uart_rx(void *opaque, const uint8_t *buf, int size)
164 struct xlx_uartlite *s = opaque;
166 /* Got a byte. */
167 if (s->rx_fifo_len >= 8) {
168 printf("WARNING: UART dropped char.\n");
169 return;
171 s->rx_fifo[s->rx_fifo_pos] = *buf;
172 s->rx_fifo_pos++;
173 s->rx_fifo_pos &= 0x7;
174 s->rx_fifo_len++;
176 uart_update_status(s);
177 uart_update_irq(s);
180 static int uart_can_rx(void *opaque)
182 struct xlx_uartlite *s = opaque;
183 int r;
185 r = s->rx_fifo_len < sizeof(s->rx_fifo);
186 if (!r)
187 printf("cannot receive!\n");
188 return r;
191 static void uart_event(void *opaque, int event)
196 static int xilinx_uartlite_init(SysBusDevice *dev)
198 struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev);
199 int uart_regs;
201 sysbus_init_irq(dev, &s->irq);
203 uart_update_status(s);
204 uart_regs = cpu_register_io_memory(uart_read, uart_write, s);
205 sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
207 s->chr = qdev_init_chardev(&dev->qdev);
208 if (s->chr)
209 qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
210 return 0;
213 static void xilinx_uart_register(void)
215 sysbus_register_dev("xilinx,uartlite", sizeof (struct xlx_uartlite),
216 xilinx_uartlite_init);
219 device_init(xilinx_uart_register)