hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "isa.h"
  29 #include "sysbus.h"
  30
  31 #include "qemu-kvm.h"
  32
  33 typedef uint32_t pci_addr_t;
  34 #include "pci_host.h"
  35
  36 typedef PCIHostState I440FXState;
  37
  38 typedef struct PIIX3State {
  39     PCIDevice dev;
  40     int pci_irq_levels[4];
  41     qemu_irq *pic;
  42 } PIIX3State;
  43
  44 struct PCII440FXState {
  45     PCIDevice dev;
  46     target_phys_addr_t isa_page_descs[384 / 4];
  47     uint8_t smm_enabled;
  48     PIIX3State *piix3;
  49 };
  50
  51 static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
  52 {
  53     I440FXState *s = opaque;
  54     s->config_reg = val;
  55 }
  56
  57 static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
  58 {
  59     I440FXState *s = opaque;
  60     return s->config_reg;
  61 }
  62
  63 static void piix3_set_irq(void *opaque, int irq_num, int level);
  64
  65 /* return the global irq number corresponding to a given device irq
  66    pin. We could also use the bus number to have a more precise
  67    mapping. */
  68 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
  69 {
  70     int slot_addend;
  71     slot_addend = (pci_dev->devfn >> 3) - 1;
  72     return (irq_num + slot_addend) & 3;
  73 }
  74
  75 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
  76 {
  77     uint32_t addr;
  78
  79     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
  80     switch(r) {
  81     case 3:
  82         /* RAM */
  83         cpu_register_physical_memory(start, end - start,
  84                                      start);
  85         break;
  86     case 1:
  87         /* ROM (XXX: not quite correct) */
  88         cpu_register_physical_memory(start, end - start,
  89                                      start | IO_MEM_ROM);
  90         break;
  91     case 2:
  92     case 0:
  93         /* XXX: should distinguish read/write cases */
  94         for(addr = start; addr < end; addr += 4096) {
  95             cpu_register_physical_memory(addr, 4096,
  96                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
  97         }
  98         break;
  99     }
 100 }
 101
 102 static void i440fx_update_memory_mappings(PCII440FXState *d)
 103 {
 104     int i, r;
 105     uint32_t smram, addr;
 106
 107     if (kvm_enabled()) {
 108         /* FIXME: Support remappings and protection changes. */
 109         return;
 110     }
 111     update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3);
 112     for(i = 0; i < 12; i++) {
 113         r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
 114         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
 115     }
 116     smram = d->dev.config[0x72];
 117     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 118         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
 119     } else {
 120         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 121             cpu_register_physical_memory(addr, 4096,
 122                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 123         }
 124     }
 125 }
 126
 127 void i440fx_set_smm(PCII440FXState *d, int val)
 128 {
 129     val = (val != 0);
 130     if (d->smm_enabled != val) {
 131         d->smm_enabled = val;
 132         i440fx_update_memory_mappings(d);
 133     }
 134 }
 135
 136
 137 /* XXX: suppress when better memory API. We make the assumption that
 138    no device (in particular the VGA) changes the memory mappings in
 139    the 0xa0000-0x100000 range */
 140 void i440fx_init_memory_mappings(PCII440FXState *d)
 141 {
 142     int i;
 143     for(i = 0; i < 96; i++) {
 144         d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 145     }
 146 }
 147
 148 static void i440fx_write_config(PCIDevice *dev,
 149                                 uint32_t address, uint32_t val, int len)
 150 {
 151     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 152
 153     /* XXX: implement SMRAM.D_LOCK */
 154     pci_default_write_config(dev, address, val, len);
 155     if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
 156         i440fx_update_memory_mappings(d);
 157 }
 158
 159 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 160 {
 161     PCII440FXState *d = opaque;
 162     int ret, i;
 163
 164     ret = pci_device_load(&d->dev, f);
 165     if (ret < 0)
 166         return ret;
 167     i440fx_update_memory_mappings(d);
 168     qemu_get_8s(f, &d->smm_enabled);
 169
 170     if (version_id == 2)
 171         for (i = 0; i < 4; i++)
 172             d->piix3->pci_irq_levels[i] = qemu_get_be32(f);
 173
 174     return 0;
 175 }
 176
 177 static int i440fx_post_load(void *opaque, int version_id)
 178 {
 179     PCII440FXState *d = opaque;
 180
 181     i440fx_update_memory_mappings(d);
 182     return 0;
 183 }
 184
 185 static const VMStateDescription vmstate_i440fx = {
 186     .name = "I440FX",
 187     .version_id = 3,
 188     .minimum_version_id = 3,
 189     .minimum_version_id_old = 1,
 190     .load_state_old = i440fx_load_old,
 191     .post_load = i440fx_post_load,
 192     .fields      = (VMStateField []) {
 193         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 194         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 195         VMSTATE_END_OF_LIST()
 196     }
 197 };
 198
 199 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 200 {
 201     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 202
 203     register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
 204     register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
 205
 206     register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
 207     register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
 208     register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
 209     register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
 210     register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
 211     register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
 212     return 0;
 213 }
 214
 215 static int i440fx_initfn(PCIDevice *dev)
 216 {
 217     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 218
 219     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
 220     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
 221     d->dev.config[0x08] = 0x02; // revision
 222     pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
 223     d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 224
 225     d->dev.config[0x72] = 0x02; /* SMRAM */
 226
 227     vmstate_register(0, &vmstate_i440fx, d);
 228     return 0;
 229 }
 230
 231 static PIIX3State *piix3_dev;
 232
 233 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
 234 {
 235     DeviceState *dev;
 236     PCIBus *b;
 237     PCIDevice *d;
 238     I440FXState *s;
 239     PIIX3State *piix3;
 240
 241     dev = qdev_create(NULL, "i440FX-pcihost");
 242     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 243     b = pci_bus_new(&s->busdev.qdev, NULL, 0);
 244     s->bus = b;
 245     qdev_init_nofail(dev);
 246
 247     d = pci_create_simple(b, 0, "i440FX");
 248     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 249
 250     piix3 = DO_UPCAST(PIIX3State, dev,
 251                                  pci_create_simple(b, -1, "PIIX3"));
 252     piix3->pic = pic;
 253     pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4);
 254     (*pi440fx_state)->piix3 = piix3;
 255
 256     *piix3_devfn = piix3->dev.devfn;
 257
 258     piix3_dev = piix3;
 259
 260     return b;
 261 }
 262
 263 /* PIIX3 PCI to ISA bridge */
 264
 265 static void piix3_set_irq(void *opaque, int irq_num, int level)
 266 {
 267     int i, pic_irq, pic_level;
 268     PIIX3State *piix3 = opaque;
 269
 270     piix3->pci_irq_levels[irq_num] = level;
 271
 272     /* now we change the pic irq level according to the piix irq mappings */
 273     /* XXX: optimize */
 274     pic_irq = piix3->dev.config[0x60 + irq_num];
 275     if (pic_irq < 16) {
 276         /* The pic level is the logical OR of all the PCI irqs mapped
 277            to it */
 278         pic_level = 0;
 279         for (i = 0; i < 4; i++) {
 280             if (pic_irq == piix3->dev.config[0x60 + i])
 281                 pic_level |= piix3->pci_irq_levels[i];
 282         }
 283         qemu_set_irq(piix3->pic[pic_irq], pic_level);
 284     }
 285 }
 286
 287 int piix_get_irq(int pin)
 288 {
 289     if (piix3_dev)
 290         return piix3_dev->dev.config[0x60+pin];
 291     return 0;
 292 }
 293
 294 static void piix3_reset(void *opaque)
 295 {
 296     PIIX3State *d = opaque;
 297     uint8_t *pci_conf = d->dev.config;
 298
 299     pci_conf[0x04] = 0x07; // master, memory and I/O
 300     pci_conf[0x05] = 0x00;
 301     pci_conf[0x06] = 0x00;
 302     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 303     pci_conf[0x4c] = 0x4d;
 304     pci_conf[0x4e] = 0x03;
 305     pci_conf[0x4f] = 0x00;
 306     pci_conf[0x60] = 0x80;
 307     pci_conf[0x61] = 0x80;
 308     pci_conf[0x62] = 0x80;
 309     pci_conf[0x63] = 0x80;
 310     pci_conf[0x69] = 0x02;
 311     pci_conf[0x70] = 0x80;
 312     pci_conf[0x76] = 0x0c;
 313     pci_conf[0x77] = 0x0c;
 314     pci_conf[0x78] = 0x02;
 315     pci_conf[0x79] = 0x00;
 316     pci_conf[0x80] = 0x00;
 317     pci_conf[0x82] = 0x00;
 318     pci_conf[0xa0] = 0x08;
 319     pci_conf[0xa2] = 0x00;
 320     pci_conf[0xa3] = 0x00;
 321     pci_conf[0xa4] = 0x00;
 322     pci_conf[0xa5] = 0x00;
 323     pci_conf[0xa6] = 0x00;
 324     pci_conf[0xa7] = 0x00;
 325     pci_conf[0xa8] = 0x0f;
 326     pci_conf[0xaa] = 0x00;
 327     pci_conf[0xab] = 0x00;
 328     pci_conf[0xac] = 0x00;
 329     pci_conf[0xae] = 0x00;
 330
 331     memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
 332 }
 333
 334 static const VMStateDescription vmstate_piix3 = {
 335     .name = "PIIX3",
 336     .version_id = 3,
 337     .minimum_version_id = 2,
 338     .minimum_version_id_old = 2,
 339     .fields      = (VMStateField []) {
 340         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 341         VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3),
 342         VMSTATE_END_OF_LIST()
 343     }
 344 };
 345
 346 static int piix3_initfn(PCIDevice *dev)
 347 {
 348     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 349     uint8_t *pci_conf;
 350
 351     isa_bus_new(&d->dev.qdev);
 352     vmstate_register(0, &vmstate_piix3, d);
 353
 354     pci_conf = d->dev.config;
 355     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 356     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 357     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 358     pci_conf[PCI_HEADER_TYPE] =
 359         PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
 360
 361     piix3_reset(d);
 362     qemu_register_reset(piix3_reset, d);
 363     return 0;
 364 }
 365
 366 static PCIDeviceInfo i440fx_info[] = {
 367     {
 368         .qdev.name    = "i440FX",
 369         .qdev.desc    = "Host bridge",
 370         .qdev.size    = sizeof(PCII440FXState),
 371         .qdev.no_user = 1,
 372         .init         = i440fx_initfn,
 373         .config_write = i440fx_write_config,
 374     },{
 375         .qdev.name    = "PIIX3",
 376         .qdev.desc    = "ISA bridge",
 377         .qdev.size    = sizeof(PIIX3State),
 378         .qdev.no_user = 1,
 379         .init         = piix3_initfn,
 380     },{
 381         /* end of list */
 382     }
 383 };
 384
 385 static SysBusDeviceInfo i440fx_pcihost_info = {
 386     .init         = i440fx_pcihost_initfn,
 387     .qdev.name    = "i440FX-pcihost",
 388     .qdev.size    = sizeof(I440FXState),
 389     .qdev.no_user = 1,
 390 };
 391
 392 static void i440fx_register(void)
 393 {
 394     sysbus_register_withprop(&i440fx_pcihost_info);
 395     pci_qdev_register_many(i440fx_info);
 396 }
 397 device_init(i440fx_register);