hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29 #include "qemu-kvm.h"
  30 #include "hw/pc.h"
  31 #include "device-assignment.h"
  32
  33 //#define DEBUG_PCI
  34 #ifdef DEBUG_PCI
  35 # define PCI_DPRINTF(format, ...)       printf(format, __VA_ARGS__)
  36 #else
  37 # define PCI_DPRINTF(format, ...)       do { } while (0)
  38 #endif
  39
  40 struct PCIBus {
  41     BusState qbus;
  42     int bus_num;
  43     int devfn_min;
  44     pci_set_irq_fn set_irq;
  45     pci_map_irq_fn map_irq;
  46     pci_hotplug_fn hotplug;
  47     uint32_t config_reg; /* XXX: suppress */
  48     void *irq_opaque;
  49     PCIDevice *devices[256];
  50     PCIDevice *parent_dev;
  51     PCIBus *next;
  52     /* The bus IRQ state is the logical OR of the connected devices.
  53        Keep a count of the number of devices with raised IRQs.  */
  54     int nirq;
  55     int *irq_count;
  56 };
  57
  58 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  59
  60 static struct BusInfo pci_bus_info = {
  61     .name       = "PCI",
  62     .size       = sizeof(PCIBus),
  63     .print_dev  = pcibus_dev_print,
  64     .props      = (Property[]) {
  65         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  66         DEFINE_PROP_END_OF_LIST()
  67     }
  68 };
  69
  70 static void pci_update_mappings(PCIDevice *d);
  71 static void pci_set_irq(void *opaque, int irq_num, int level);
  72
  73 target_phys_addr_t pci_mem_base;
  74 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  75 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  76 static PCIBus *first_bus;
  77
  78 static const VMStateDescription vmstate_pcibus = {
  79     .name = "PCIBUS",
  80     .version_id = 1,
  81     .minimum_version_id = 1,
  82     .minimum_version_id_old = 1,
  83     .fields      = (VMStateField []) {
  84         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  85         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
  86         VMSTATE_END_OF_LIST()
  87     }
  88 };
  89
  90 static inline int pci_bar(int reg)
  91 {
  92     return reg == PCI_ROM_SLOT ? PCI_ROM_ADDRESS : PCI_BASE_ADDRESS_0 + reg * 4;
  93 }
  94
  95 static void pci_device_reset(PCIDevice *dev)
  96 {
  97     memset(dev->irq_state, 0, sizeof dev->irq_state);
  98 }
  99
 100 static void pci_bus_reset(void *opaque)
 101 {
 102     PCIBus *bus = opaque;
 103     int i;
 104
 105     for (i = 0; i < bus->nirq; i++) {
 106         bus->irq_count[i] = 0;
 107     }
 108     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 109         if (bus->devices[i]) {
 110             pci_device_reset(bus->devices[i]);
 111         }
 112     }
 113 }
 114
 115 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 116                          const char *name, int devfn_min)
 117 {
 118     static int nbus = 0;
 119
 120     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 121     bus->devfn_min = devfn_min;
 122     bus->next = first_bus;
 123     first_bus = bus;
 124     vmstate_register(nbus++, &vmstate_pcibus, bus);
 125     qemu_register_reset(pci_bus_reset, bus);
 126 }
 127
 128 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 129 {
 130     PCIBus *bus;
 131
 132     bus = qemu_mallocz(sizeof(*bus));
 133     bus->qbus.qdev_allocated = 1;
 134     pci_bus_new_inplace(bus, parent, name, devfn_min);
 135     return bus;
 136 }
 137
 138 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 139                   void *irq_opaque, int nirq)
 140 {
 141     bus->set_irq = set_irq;
 142     bus->map_irq = map_irq;
 143     bus->irq_opaque = irq_opaque;
 144     bus->nirq = nirq;
 145     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 146 }
 147
 148 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
 149 {
 150     bus->qbus.allow_hotplug = 1;
 151     bus->hotplug = hotplug;
 152 }
 153
 154 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 155                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 156                          void *irq_opaque, int devfn_min, int nirq)
 157 {
 158     PCIBus *bus;
 159
 160     bus = pci_bus_new(parent, name, devfn_min);
 161     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 162     return bus;
 163 }
 164
 165 static void pci_register_secondary_bus(PCIBus *bus,
 166                                        PCIDevice *dev,
 167                                        pci_map_irq_fn map_irq,
 168                                        const char *name)
 169 {
 170     qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
 171     bus->map_irq = map_irq;
 172     bus->parent_dev = dev;
 173     bus->next = dev->bus->next;
 174     dev->bus->next = bus;
 175 }
 176
 177 int pci_bus_num(PCIBus *s)
 178 {
 179     return s->bus_num;
 180 }
 181
 182 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 183 {
 184     PCIDevice *s = container_of(pv, PCIDevice, config);
 185     uint8_t config[PCI_CONFIG_SPACE_SIZE];
 186     int i;
 187
 188     assert(size == sizeof config);
 189     qemu_get_buffer(f, config, sizeof config);
 190     for (i = 0; i < sizeof config; ++i)
 191         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 192             return -EINVAL;
 193     memcpy(s->config, config, sizeof config);
 194
 195     pci_update_mappings(s);
 196
 197     return 0;
 198 }
 199
 200 /* just put buffer */
 201 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 202 {
 203     const uint8_t *v = pv;
 204     qemu_put_buffer(f, v, size);
 205 }
 206
 207 static VMStateInfo vmstate_info_pci_config = {
 208     .name = "pci config",
 209     .get  = get_pci_config_device,
 210     .put  = put_pci_config_device,
 211 };
 212
 213 const VMStateDescription vmstate_pci_device = {
 214     .name = "PCIDevice",
 215     .version_id = 2,
 216     .minimum_version_id = 1,
 217     .minimum_version_id_old = 1,
 218     .fields      = (VMStateField []) {
 219         VMSTATE_INT32_LE(version_id, PCIDevice),
 220         VMSTATE_SINGLE(config, PCIDevice, 0, vmstate_info_pci_config,
 221                        typeof_field(PCIDevice,config)),
 222         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, 4, 2),
 223         VMSTATE_END_OF_LIST()
 224     }
 225 };
 226
 227 void pci_device_save(PCIDevice *s, QEMUFile *f)
 228 {
 229     vmstate_save_state(f, &vmstate_pci_device, s);
 230 }
 231
 232 int pci_device_load(PCIDevice *s, QEMUFile *f)
 233 {
 234     return vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
 235 }
 236
 237 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 238 {
 239     uint16_t *id;
 240
 241     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 242     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 243     id[1] = cpu_to_le16(pci_default_sub_device_id);
 244     return 0;
 245 }
 246
 247 /*
 248  * Parse pci address in qemu command
 249  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 250  */
 251 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 252 {
 253     const char *p;
 254     char *e;
 255     unsigned long val;
 256     unsigned long dom = 0, bus = 0;
 257     unsigned slot = 0;
 258
 259     p = addr;
 260     val = strtoul(p, &e, 16);
 261     if (e == p)
 262         return -1;
 263     if (*e == ':') {
 264         bus = val;
 265         p = e + 1;
 266         val = strtoul(p, &e, 16);
 267         if (e == p)
 268             return -1;
 269         if (*e == ':') {
 270             dom = bus;
 271             bus = val;
 272             p = e + 1;
 273             val = strtoul(p, &e, 16);
 274             if (e == p)
 275                 return -1;
 276         }
 277     }
 278
 279     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 280         return -1;
 281
 282     slot = val;
 283
 284     if (*e)
 285         return -1;
 286
 287     /* Note: QEMU doesn't implement domains other than 0 */
 288     if (dom != 0 || pci_find_bus(bus) == NULL)
 289         return -1;
 290
 291     *domp = dom;
 292     *busp = bus;
 293     *slotp = slot;
 294     return 0;
 295 }
 296
 297 /*
 298  * Parse device bdf in device assignment command:
 299  *
 300  * -pcidevice host=bus:dev.func
 301  *
 302  * Parse <bus>:<slot>.<func> return -1 on error
 303  */
 304 int pci_parse_host_devaddr(const char *addr, int *busp,
 305                            int *slotp, int *funcp)
 306 {
 307     const char *p;
 308     char *e;
 309     int val;
 310     int bus = 0, slot = 0, func = 0;
 311
 312     p = addr;
 313     val = strtoul(p, &e, 16);
 314     if (e == p)
 315         return -1;
 316     if (*e == ':') {
 317         bus = val;
 318         p = e + 1;
 319         val = strtoul(p, &e, 16);
 320         if (e == p)
 321             return -1;
 322         if (*e == '.') {
 323             slot = val;
 324             p = e + 1;
 325             val = strtoul(p, &e, 16);
 326             if (e == p)
 327                 return -1;
 328             func = val;
 329         } else
 330             return -1;
 331     } else
 332         return -1;
 333
 334     if (bus > 0xff || slot > 0x1f || func > 0x7)
 335         return -1;
 336
 337     if (*e)
 338         return -1;
 339
 340     *busp = bus;
 341     *slotp = slot;
 342     *funcp = func;
 343     return 0;
 344 }
 345
 346 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 347                      unsigned *slotp)
 348 {
 349     /* strip legacy tag */
 350     if (!strncmp(addr, "pci_addr=", 9)) {
 351         addr += 9;
 352     }
 353     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 354         monitor_printf(mon, "Invalid pci address\n");
 355         return -1;
 356     }
 357     return 0;
 358 }
 359
 360 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 361 {
 362     int dom, bus;
 363     unsigned slot;
 364
 365     if (!devaddr) {
 366         *devfnp = -1;
 367         return pci_find_bus(0);
 368     }
 369
 370     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 371         return NULL;
 372     }
 373
 374     *devfnp = slot << 3;
 375     return pci_find_bus(bus);
 376 }
 377
 378 static void pci_init_cmask(PCIDevice *dev)
 379 {
 380     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 381     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 382     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 383     dev->cmask[PCI_REVISION_ID] = 0xff;
 384     dev->cmask[PCI_CLASS_PROG] = 0xff;
 385     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 386     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 387     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 388 }
 389
 390 static void pci_init_wmask(PCIDevice *dev)
 391 {
 392     int i;
 393     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 394     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 395     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 396                               | PCI_COMMAND_MASTER;
 397     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 398         dev->wmask[i] = 0xff;
 399 }
 400
 401 /* -1 for devfn means auto assign */
 402 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 403                                          const char *name, int devfn,
 404                                          PCIConfigReadFunc *config_read,
 405                                          PCIConfigWriteFunc *config_write)
 406 {
 407     if (devfn < 0) {
 408         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 409             if (!bus->devices[devfn])
 410                 goto found;
 411         }
 412         return NULL;
 413     found: ;
 414     } else if (bus->devices[devfn]) {
 415         return NULL;
 416     }
 417     pci_dev->bus = bus;
 418     pci_dev->devfn = devfn;
 419     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 420     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 421     pci_set_default_subsystem_id(pci_dev);
 422     pci_init_cmask(pci_dev);
 423     pci_init_wmask(pci_dev);
 424
 425     if (!config_read)
 426         config_read = pci_default_read_config;
 427     if (!config_write)
 428         config_write = pci_default_write_config;
 429     pci_dev->config_read = config_read;
 430     pci_dev->config_write = config_write;
 431     bus->devices[devfn] = pci_dev;
 432     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 433     pci_dev->version_id = 2; /* Current pci device vmstate version */
 434     return pci_dev;
 435 }
 436
 437 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 438                                int instance_size, int devfn,
 439                                PCIConfigReadFunc *config_read,
 440                                PCIConfigWriteFunc *config_write)
 441 {
 442     PCIDevice *pci_dev;
 443
 444     pci_dev = qemu_mallocz(instance_size);
 445     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 446                                      config_read, config_write);
 447     return pci_dev;
 448 }
 449 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 450 {
 451     return addr + pci_mem_base;
 452 }
 453
 454 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 455 {
 456     PCIIORegion *r;
 457     int i;
 458
 459     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 460         r = &pci_dev->io_regions[i];
 461         if (!r->size || r->addr == -1)
 462             continue;
 463         if (r->type == PCI_ADDRESS_SPACE_IO) {
 464             isa_unassign_ioport(r->addr, r->size);
 465         } else {
 466             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 467                                                      r->size,
 468                                                      IO_MEM_UNASSIGNED);
 469         }
 470     }
 471 }
 472
 473 static int pci_unregister_device(DeviceState *dev)
 474 {
 475     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 476     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 477     int ret = 0;
 478
 479     if (info->exit)
 480         ret = info->exit(pci_dev);
 481     if (ret)
 482         return ret;
 483
 484     pci_unregister_io_regions(pci_dev);
 485
 486     qemu_free_irqs(pci_dev->irq);
 487     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 488     return 0;
 489 }
 490
 491 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 492                             uint32_t size, int type,
 493                             PCIMapIORegionFunc *map_func)
 494 {
 495     PCIIORegion *r;
 496     uint32_t addr;
 497     uint32_t wmask;
 498
 499     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 500         return;
 501
 502     if (size & (size-1)) {
 503         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 504                     "type=0x%x, size=0x%x\n", type, size);
 505         exit(1);
 506     }
 507
 508     r = &pci_dev->io_regions[region_num];
 509     r->addr = -1;
 510     r->size = size;
 511     r->type = type;
 512     r->map_func = map_func;
 513
 514     wmask = ~(size - 1);
 515     addr = pci_bar(region_num);
 516     if (region_num == PCI_ROM_SLOT) {
 517         /* ROM enable bit is writeable */
 518         wmask |= PCI_ROM_ADDRESS_ENABLE;
 519     }
 520     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 521     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 522     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 523 }
 524
 525 static void pci_update_mappings(PCIDevice *d)
 526 {
 527     PCIIORegion *r;
 528     int cmd, i;
 529     uint32_t last_addr, new_addr;
 530
 531     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 532     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 533         r = &d->io_regions[i];
 534         if (r->size != 0) {
 535             if (r->type & PCI_ADDRESS_SPACE_IO) {
 536                 if (cmd & PCI_COMMAND_IO) {
 537                     new_addr = pci_get_long(d->config + pci_bar(i));
 538                     new_addr = new_addr & ~(r->size - 1);
 539                     last_addr = new_addr + r->size - 1;
 540                     /* NOTE: we have only 64K ioports on PC */
 541                     if (last_addr <= new_addr || new_addr == 0 ||
 542                         last_addr >= 0x10000) {
 543                         new_addr = -1;
 544                     }
 545                 } else {
 546                     new_addr = -1;
 547                 }
 548             } else {
 549                 if (cmd & PCI_COMMAND_MEMORY) {
 550                     new_addr = pci_get_long(d->config + pci_bar(i));
 551                     /* the ROM slot has a specific enable bit */
 552                     if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))
 553                         goto no_mem_map;
 554                     new_addr = new_addr & ~(r->size - 1);
 555                     last_addr = new_addr + r->size - 1;
 556                     /* NOTE: we do not support wrapping */
 557                     /* XXX: as we cannot support really dynamic
 558                        mappings, we handle specific values as invalid
 559                        mappings. */
 560                     if (last_addr <= new_addr || new_addr == 0 ||
 561                         last_addr == -1) {
 562                         new_addr = -1;
 563                     }
 564                 } else {
 565                 no_mem_map:
 566                     new_addr = -1;
 567                 }
 568             }
 569             /* now do the real mapping */
 570             if (new_addr != r->addr) {
 571                 if (r->addr != -1) {
 572                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 573                         int class;
 574                         /* NOTE: specific hack for IDE in PC case:
 575                            only one byte must be mapped. */
 576                         class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 577                         if (class == 0x0101 && r->size == 4) {
 578                             isa_unassign_ioport(r->addr + 2, 1);
 579                         } else {
 580                             isa_unassign_ioport(r->addr, r->size);
 581                         }
 582                     } else {
 583                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 584                                                      r->size,
 585                                                      IO_MEM_UNASSIGNED);
 586                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 587                     }
 588                 }
 589                 r->addr = new_addr;
 590                 if (r->addr != -1) {
 591                     r->map_func(d, i, r->addr, r->size, r->type);
 592                 }
 593             }
 594         }
 595     }
 596 }
 597
 598 static uint32_t pci_read_config(PCIDevice *d,
 599                                 uint32_t address, int len)
 600 {
 601     uint32_t val;
 602
 603     switch(len) {
 604     default:
 605     case 4:
 606         if (address <= 0xfc) {
 607             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 608             break;
 609         }
 610         /* fall through */
 611     case 2:
 612         if (address <= 0xfe) {
 613             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 614             break;
 615         }
 616         /* fall through */
 617     case 1:
 618         val = d->config[address];
 619         break;
 620     }
 621     return val;
 622 }
 623
 624 static void pci_write_config(PCIDevice *pci_dev,
 625                              uint32_t address, uint32_t val, int len)
 626 {
 627     int i;
 628     for (i = 0; i < len; i++) {
 629         pci_dev->config[address + i] = val & 0xff;
 630         val >>= 8;
 631     }
 632 }
 633
 634 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len)
 635 {
 636     if (pci_dev->cap.supported && address >= pci_dev->cap.start &&
 637             (address + len) < pci_dev->cap.start + pci_dev->cap.length)
 638         return 1;
 639     return 0;
 640 }
 641
 642 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 643                                      uint32_t address, int len)
 644 {
 645     return pci_read_config(pci_dev, address, len);
 646 }
 647
 648 void pci_default_cap_write_config(PCIDevice *pci_dev,
 649                                   uint32_t address, uint32_t val, int len)
 650 {
 651     pci_write_config(pci_dev, address, val, len);
 652 }
 653
 654 uint32_t pci_default_read_config(PCIDevice *d,
 655                                  uint32_t address, int len)
 656 {
 657     if (pci_access_cap_config(d, address, len))
 658         return d->cap.config_read(d, address, len);
 659
 660     return pci_read_config(d, address, len);
 661 }
 662
 663 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 664 {
 665     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 666     int i;
 667
 668     if (pci_access_cap_config(d, addr, l)) {
 669         d->cap.config_write(d, addr, val, l);
 670         return;
 671     }
 672
 673     /* not efficient, but simple */
 674     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 675     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 676         uint8_t wmask = d->wmask[addr];
 677         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 678     }
 679
 680 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
 681     if (kvm_enabled() && kvm_irqchip_in_kernel() &&
 682         addr >= PIIX_CONFIG_IRQ_ROUTE &&
 683         addr < PIIX_CONFIG_IRQ_ROUTE + 4)
 684         assigned_dev_update_irqs();
 685 #endif /* CONFIG_KVM_DEVICE_ASSIGNMENT */
 686
 687     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 688         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 689             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 690         pci_update_mappings(d);
 691
 692 }
 693
 694 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 695 {
 696     PCIBus *s = opaque;
 697     PCIDevice *pci_dev;
 698     int config_addr, bus_num;
 699
 700 #if 0
 701     PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
 702                 addr, val, len);
 703 #endif
 704     bus_num = (addr >> 16) & 0xff;
 705     while (s && s->bus_num != bus_num)
 706         s = s->next;
 707     if (!s)
 708         return;
 709     pci_dev = s->devices[(addr >> 8) & 0xff];
 710     if (!pci_dev)
 711         return;
 712     config_addr = addr & 0xff;
 713     PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 714                 pci_dev->name, config_addr, val, len);
 715     pci_dev->config_write(pci_dev, config_addr, val, len);
 716 }
 717
 718 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 719 {
 720     PCIBus *s = opaque;
 721     PCIDevice *pci_dev;
 722     int config_addr, bus_num;
 723     uint32_t val;
 724
 725     bus_num = (addr >> 16) & 0xff;
 726     while (s && s->bus_num != bus_num)
 727         s= s->next;
 728     if (!s)
 729         goto fail;
 730     pci_dev = s->devices[(addr >> 8) & 0xff];
 731     if (!pci_dev) {
 732     fail:
 733         switch(len) {
 734         case 1:
 735             val = 0xff;
 736             break;
 737         case 2:
 738             val = 0xffff;
 739             break;
 740         default:
 741         case 4:
 742             val = 0xffffffff;
 743             break;
 744         }
 745         goto the_end;
 746     }
 747     config_addr = addr & 0xff;
 748     val = pci_dev->config_read(pci_dev, config_addr, len);
 749     PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 750                 pci_dev->name, config_addr, val, len);
 751  the_end:
 752 #if 0
 753     PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
 754                 addr, val, len);
 755 #endif
 756     return val;
 757 }
 758
 759 /***********************************************************/
 760 /* generic PCI irq support */
 761
 762 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 763 static void pci_set_irq(void *opaque, int irq_num, int level)
 764 {
 765     PCIDevice *pci_dev = opaque;
 766     PCIBus *bus;
 767     int change;
 768
 769     change = level - pci_dev->irq_state[irq_num];
 770     if (!change)
 771         return;
 772
 773     pci_dev->irq_state[irq_num] = level;
 774
 775 #if defined(TARGET_IA64)
 776     ioapic_set_irq(pci_dev, irq_num, level);
 777 #endif
 778
 779     for (;;) {
 780         bus = pci_dev->bus;
 781         irq_num = bus->map_irq(pci_dev, irq_num);
 782         if (bus->set_irq)
 783             break;
 784         pci_dev = bus->parent_dev;
 785     }
 786     bus->irq_count[irq_num] += change;
 787     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 788 }
 789
 790 int pci_map_irq(PCIDevice *pci_dev, int pin)
 791 {
 792     return pci_dev->bus->map_irq(pci_dev, pin);
 793 }
 794
 795 /***********************************************************/
 796 /* monitor info on PCI */
 797
 798 typedef struct {
 799     uint16_t class;
 800     const char *desc;
 801 } pci_class_desc;
 802
 803 static const pci_class_desc pci_class_descriptions[] =
 804 {
 805     { 0x0100, "SCSI controller"},
 806     { 0x0101, "IDE controller"},
 807     { 0x0102, "Floppy controller"},
 808     { 0x0103, "IPI controller"},
 809     { 0x0104, "RAID controller"},
 810     { 0x0106, "SATA controller"},
 811     { 0x0107, "SAS controller"},
 812     { 0x0180, "Storage controller"},
 813     { 0x0200, "Ethernet controller"},
 814     { 0x0201, "Token Ring controller"},
 815     { 0x0202, "FDDI controller"},
 816     { 0x0203, "ATM controller"},
 817     { 0x0280, "Network controller"},
 818     { 0x0300, "VGA controller"},
 819     { 0x0301, "XGA controller"},
 820     { 0x0302, "3D controller"},
 821     { 0x0380, "Display controller"},
 822     { 0x0400, "Video controller"},
 823     { 0x0401, "Audio controller"},
 824     { 0x0402, "Phone"},
 825     { 0x0480, "Multimedia controller"},
 826     { 0x0500, "RAM controller"},
 827     { 0x0501, "Flash controller"},
 828     { 0x0580, "Memory controller"},
 829     { 0x0600, "Host bridge"},
 830     { 0x0601, "ISA bridge"},
 831     { 0x0602, "EISA bridge"},
 832     { 0x0603, "MC bridge"},
 833     { 0x0604, "PCI bridge"},
 834     { 0x0605, "PCMCIA bridge"},
 835     { 0x0606, "NUBUS bridge"},
 836     { 0x0607, "CARDBUS bridge"},
 837     { 0x0608, "RACEWAY bridge"},
 838     { 0x0680, "Bridge"},
 839     { 0x0c03, "USB controller"},
 840     { 0, NULL}
 841 };
 842
 843 static void pci_info_device(PCIDevice *d)
 844 {
 845     Monitor *mon = cur_mon;
 846     int i, class;
 847     PCIIORegion *r;
 848     const pci_class_desc *desc;
 849
 850     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 851                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 852     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 853     monitor_printf(mon, "    ");
 854     desc = pci_class_descriptions;
 855     while (desc->desc && class != desc->class)
 856         desc++;
 857     if (desc->desc) {
 858         monitor_printf(mon, "%s", desc->desc);
 859     } else {
 860         monitor_printf(mon, "Class %04x", class);
 861     }
 862     monitor_printf(mon, ": PCI device %04x:%04x\n",
 863            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 864            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 865
 866     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 867         monitor_printf(mon, "      IRQ %d.\n",
 868                        d->config[PCI_INTERRUPT_LINE]);
 869     }
 870     if (class == 0x0604) {
 871         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 872     }
 873     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 874         r = &d->io_regions[i];
 875         if (r->size != 0) {
 876             monitor_printf(mon, "      BAR%d: ", i);
 877             if (r->type & PCI_ADDRESS_SPACE_IO) {
 878                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 879                                r->addr, r->addr + r->size - 1);
 880             } else {
 881                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 882                                r->addr, r->addr + r->size - 1);
 883             }
 884         }
 885     }
 886     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
 887     if (class == 0x0604 && d->config[0x19] != 0) {
 888         pci_for_each_device(d->config[0x19], pci_info_device);
 889     }
 890 }
 891
 892 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 893 {
 894     PCIBus *bus = first_bus;
 895     PCIDevice *d;
 896     int devfn;
 897
 898     while (bus && bus->bus_num != bus_num)
 899         bus = bus->next;
 900     if (bus) {
 901         for(devfn = 0; devfn < 256; devfn++) {
 902             d = bus->devices[devfn];
 903             if (d)
 904                 fn(d);
 905         }
 906     }
 907 }
 908
 909 void pci_info(Monitor *mon)
 910 {
 911     pci_for_each_device(0, pci_info_device);
 912 }
 913
 914 static const char * const pci_nic_models[] = {
 915     "ne2k_pci",
 916     "i82551",
 917     "i82557b",
 918     "i82559er",
 919     "rtl8139",
 920     "e1000",
 921     "pcnet",
 922     "virtio",
 923     NULL
 924 };
 925
 926 static const char * const pci_nic_names[] = {
 927     "ne2k_pci",
 928     "i82551",
 929     "i82557b",
 930     "i82559er",
 931     "rtl8139",
 932     "e1000",
 933     "pcnet",
 934     "virtio-net-pci",
 935     NULL
 936 };
 937
 938 /* Initialize a PCI NIC.  */
 939 /* FIXME callers should check for failure, but don't */
 940 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 941                         const char *default_devaddr)
 942 {
 943     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 944     PCIBus *bus;
 945     int devfn;
 946     PCIDevice *pci_dev;
 947     DeviceState *dev;
 948     int i;
 949
 950     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
 951     if (i < 0)
 952         return NULL;
 953
 954     bus = pci_get_bus_devfn(&devfn, devaddr);
 955     if (!bus) {
 956         qemu_error("Invalid PCI device address %s for device %s\n",
 957                    devaddr, pci_nic_names[i]);
 958         return NULL;
 959     }
 960
 961     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
 962     dev = &pci_dev->qdev;
 963     if (nd->name)
 964         dev->id = qemu_strdup(nd->name);
 965     qdev_set_nic_properties(dev, nd);
 966     if (qdev_init(dev) < 0)
 967         return NULL;
 968     return pci_dev;
 969 }
 970
 971 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 972                                const char *default_devaddr)
 973 {
 974     PCIDevice *res;
 975
 976     if (qemu_show_nic_models(nd->model, pci_nic_models))
 977         exit(0);
 978
 979     res = pci_nic_init(nd, default_model, default_devaddr);
 980     if (!res)
 981         exit(1);
 982     return res;
 983 }
 984
 985 typedef struct {
 986     PCIDevice dev;
 987     PCIBus bus;
 988     uint32_t vid;
 989     uint32_t did;
 990 } PCIBridge;
 991
 992 static void pci_bridge_write_config(PCIDevice *d,
 993                              uint32_t address, uint32_t val, int len)
 994 {
 995     PCIBridge *s = (PCIBridge *)d;
 996
 997     pci_default_write_config(d, address, val, len);
 998     s->bus.bus_num = d->config[PCI_SECONDARY_BUS];
 999 }
1000
1001 PCIBus *pci_find_bus(int bus_num)
1002 {
1003     PCIBus *bus = first_bus;
1004
1005     while (bus && bus->bus_num != bus_num)
1006         bus = bus->next;
1007
1008     return bus;
1009 }
1010
1011 PCIDevice *pci_find_device(int bus_num, int slot, int function)
1012 {
1013     PCIBus *bus = pci_find_bus(bus_num);
1014
1015     if (!bus)
1016         return NULL;
1017
1018     return bus->devices[PCI_DEVFN(slot, function)];
1019 }
1020
1021 static int pci_bridge_initfn(PCIDevice *dev)
1022 {
1023     PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1024
1025     pci_config_set_vendor_id(s->dev.config, s->vid);
1026     pci_config_set_device_id(s->dev.config, s->did);
1027
1028     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
1029     s->dev.config[0x05] = 0x00;
1030     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
1031     s->dev.config[0x07] = 0x00; // status = fast devsel
1032     s->dev.config[0x08] = 0x00; // revision
1033     s->dev.config[0x09] = 0x00; // programming i/f
1034     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
1035     s->dev.config[0x0D] = 0x10; // latency_timer
1036     s->dev.config[PCI_HEADER_TYPE] =
1037         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
1038     s->dev.config[0x1E] = 0xa0; // secondary status
1039     return 0;
1040 }
1041
1042 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1043                         pci_map_irq_fn map_irq, const char *name)
1044 {
1045     PCIDevice *dev;
1046     PCIBridge *s;
1047
1048     dev = pci_create(bus, devfn, "pci-bridge");
1049     qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1050     qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1051     qdev_init_nofail(&dev->qdev);
1052
1053     s = DO_UPCAST(PCIBridge, dev, dev);
1054     pci_register_secondary_bus(&s->bus, &s->dev, map_irq, name);
1055     return &s->bus;
1056 }
1057
1058 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1059 {
1060     PCIDevice *pci_dev = (PCIDevice *)qdev;
1061     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1062     PCIBus *bus;
1063     int devfn, rc;
1064
1065     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1066     devfn = pci_dev->devfn;
1067     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1068                                      info->config_read, info->config_write);
1069     assert(pci_dev);
1070     rc = info->init(pci_dev);
1071     if (rc != 0)
1072         return rc;
1073     if (qdev->hotplugged)
1074         bus->hotplug(pci_dev, 1);
1075     return 0;
1076 }
1077
1078 static int pci_unplug_device(DeviceState *qdev)
1079 {
1080     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1081
1082     dev->bus->hotplug(dev, 0);
1083     return 0;
1084 }
1085
1086 void pci_qdev_register(PCIDeviceInfo *info)
1087 {
1088     info->qdev.init = pci_qdev_init;
1089     info->qdev.unplug = pci_unplug_device;
1090     info->qdev.exit = pci_unregister_device;
1091     info->qdev.bus_info = &pci_bus_info;
1092     qdev_register(&info->qdev);
1093 }
1094
1095 void pci_qdev_register_many(PCIDeviceInfo *info)
1096 {
1097     while (info->qdev.name) {
1098         pci_qdev_register(info);
1099         info++;
1100     }
1101 }
1102
1103 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1104 {
1105     DeviceState *dev;
1106
1107     dev = qdev_create(&bus->qbus, name);
1108     qdev_prop_set_uint32(dev, "addr", devfn);
1109     return DO_UPCAST(PCIDevice, qdev, dev);
1110 }
1111
1112 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1113 {
1114     PCIDevice *dev = pci_create(bus, devfn, name);
1115     qdev_init_nofail(&dev->qdev);
1116     return dev;
1117 }
1118
1119 int pci_enable_capability_support(PCIDevice *pci_dev,
1120                                   uint32_t config_start,
1121                                   PCICapConfigReadFunc *config_read,
1122                                   PCICapConfigWriteFunc *config_write,
1123                                   PCICapConfigInitFunc *config_init)
1124 {
1125     if (!pci_dev)
1126         return -ENODEV;
1127
1128     pci_dev->config[0x06] |= 0x10; // status = capabilities
1129
1130     if (config_start == 0)
1131         pci_dev->cap.start = PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR;
1132     else if (config_start >= 0x40 && config_start < 0xff)
1133         pci_dev->cap.start = config_start;
1134     else
1135         return -EINVAL;
1136
1137     if (config_read)
1138         pci_dev->cap.config_read = config_read;
1139     else
1140         pci_dev->cap.config_read = pci_default_cap_read_config;
1141     if (config_write)
1142         pci_dev->cap.config_write = config_write;
1143     else
1144         pci_dev->cap.config_write = pci_default_cap_write_config;
1145     pci_dev->cap.supported = 1;
1146     pci_dev->config[PCI_CAPABILITY_LIST] = pci_dev->cap.start;
1147     return config_init(pci_dev);
1148 }
1149
1150 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1151 {
1152     int offset = PCI_CONFIG_HEADER_SIZE;
1153     int i;
1154     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
1155         if (pdev->used[i])
1156             offset = i + 1;
1157         else if (i - offset + 1 == size)
1158             return offset;
1159     return 0;
1160 }
1161
1162 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1163                                         uint8_t *prev_p)
1164 {
1165     uint8_t next, prev;
1166
1167     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1168         return 0;
1169
1170     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1171          prev = next + PCI_CAP_LIST_NEXT)
1172         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1173             break;
1174
1175     if (prev_p)
1176         *prev_p = prev;
1177     return next;
1178 }
1179
1180 /* Reserve space and add capability to the linked list in pci config space */
1181 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1182 {
1183     uint8_t offset = pci_find_space(pdev, size);
1184     uint8_t *config = pdev->config + offset;
1185     if (!offset)
1186         return -ENOSPC;
1187     config[PCI_CAP_LIST_ID] = cap_id;
1188     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1189     pdev->config[PCI_CAPABILITY_LIST] = offset;
1190     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1191     memset(pdev->used + offset, 0xFF, size);
1192     /* Make capability read-only by default */
1193     memset(pdev->wmask + offset, 0, size);
1194     /* Check capability by default */
1195     memset(pdev->cmask + offset, 0xFF, size);
1196     return offset;
1197 }
1198
1199 /* Unlink capability from the pci config space. */
1200 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1201 {
1202     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1203     if (!offset)
1204         return;
1205     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1206     /* Make capability writeable again */
1207     memset(pdev->wmask + offset, 0xff, size);
1208     /* Clear cmask as device-specific registers can't be checked */
1209     memset(pdev->cmask + offset, 0, size);
1210     memset(pdev->used + offset, 0, size);
1211
1212     if (!pdev->config[PCI_CAPABILITY_LIST])
1213         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1214 }
1215
1216 /* Reserve space for capability at a known offset (to call after load). */
1217 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1218 {
1219     memset(pdev->used + offset, 0xff, size);
1220 }
1221
1222 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1223 {
1224     return pci_find_capability_list(pdev, cap_id, NULL);
1225 }
1226
1227 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1228 {
1229     PCIDevice *d = (PCIDevice *)dev;
1230     const pci_class_desc *desc;
1231     char ctxt[64];
1232     PCIIORegion *r;
1233     int i, class;
1234
1235     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1236     desc = pci_class_descriptions;
1237     while (desc->desc && class != desc->class)
1238         desc++;
1239     if (desc->desc) {
1240         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1241     } else {
1242         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1243     }
1244
1245     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1246                    "pci id %04x:%04x (sub %04x:%04x)\n",
1247                    indent, "", ctxt,
1248                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
1249                    le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1250                    le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
1251                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
1252                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
1253     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1254         r = &d->io_regions[i];
1255         if (!r->size)
1256             continue;
1257         monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
1258                        i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
1259                        r->addr, r->addr + r->size - 1);
1260     }
1261 }
1262
1263 static PCIDeviceInfo bridge_info = {
1264     .qdev.name    = "pci-bridge",
1265     .qdev.size    = sizeof(PCIBridge),
1266     .init         = pci_bridge_initfn,
1267     .config_write = pci_bridge_write_config,
1268     .qdev.props   = (Property[]) {
1269         DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1270         DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1271         DEFINE_PROP_END_OF_LIST(),
1272     }
1273 };
1274
1275 static void pci_register_devices(void)
1276 {
1277     pci_qdev_register(&bridge_info);
1278 }
1279
1280 device_init(pci_register_devices)