hw/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "hw.h"
  24 #include "pc.h"
  25 #include "sysemu.h"
  26 #include "qemu-timer.h"
  27 #include "host-utils.h"
  28
  29 #include "qemu-kvm.h"
  30
  31 //#define DEBUG_IOAPIC
  32
  33 #define IOAPIC_NUM_PINS                 0x18
  34 #define IOAPIC_DEFAULT_BASE_ADDRESS  0xfec00000
  35 #define IOAPIC_LVT_MASKED               (1<<16)
  36
  37 #define IOAPIC_TRIGGER_EDGE             0
  38 #define IOAPIC_TRIGGER_LEVEL            1
  39
  40 /*io{apic,sapic} delivery mode*/
  41 #define IOAPIC_DM_FIXED                 0x0
  42 #define IOAPIC_DM_LOWEST_PRIORITY       0x1
  43 #define IOAPIC_DM_PMI                   0x2
  44 #define IOAPIC_DM_NMI                   0x4
  45 #define IOAPIC_DM_INIT                  0x5
  46 #define IOAPIC_DM_SIPI                  0x5
  47 #define IOAPIC_DM_EXTINT                0x7
  48
  49 struct IOAPICState {
  50     uint8_t id;
  51     uint8_t ioregsel;
  52     uint64_t base_address;
  53
  54     uint32_t irr;
  55     uint64_t ioredtbl[IOAPIC_NUM_PINS];
  56 };
  57
  58 static void ioapic_service(IOAPICState *s)
  59 {
  60     uint8_t i;
  61     uint8_t trig_mode;
  62     uint8_t vector;
  63     uint8_t delivery_mode;
  64     uint32_t mask;
  65     uint64_t entry;
  66     uint8_t dest;
  67     uint8_t dest_mode;
  68     uint8_t polarity;
  69
  70     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  71         mask = 1 << i;
  72         if (s->irr & mask) {
  73             entry = s->ioredtbl[i];
  74             if (!(entry & IOAPIC_LVT_MASKED)) {
  75                 trig_mode = ((entry >> 15) & 1);
  76                 dest = entry >> 56;
  77                 dest_mode = (entry >> 11) & 1;
  78                 delivery_mode = (entry >> 8) & 7;
  79                 polarity = (entry >> 13) & 1;
  80                 if (trig_mode == IOAPIC_TRIGGER_EDGE)
  81                     s->irr &= ~mask;
  82                 if (delivery_mode == IOAPIC_DM_EXTINT)
  83                     vector = pic_read_irq(isa_pic);
  84                 else
  85                     vector = entry & 0xff;
  86
  87                 apic_deliver_irq(dest, dest_mode, delivery_mode,
  88                                  vector, polarity, trig_mode);
  89             }
  90         }
  91     }
  92 }
  93
  94 void ioapic_set_irq(void *opaque, int vector, int level)
  95 {
  96     IOAPICState *s = opaque;
  97
  98     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
  99      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 100      * the cleanest way of doing it but it should work. */
 101
 102     if (vector == 0 && irq0override) {
 103         vector = 2;
 104     }
 105
 106     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 107         uint32_t mask = 1 << vector;
 108         uint64_t entry = s->ioredtbl[vector];
 109
 110         if ((entry >> 15) & 1) {
 111             /* level triggered */
 112             if (level) {
 113                 s->irr |= mask;
 114                 ioapic_service(s);
 115             } else {
 116                 s->irr &= ~mask;
 117             }
 118         } else {
 119             /* edge triggered */
 120             if (level) {
 121                 s->irr |= mask;
 122                 ioapic_service(s);
 123             }
 124         }
 125     }
 126 }
 127
 128 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
 129 {
 130     IOAPICState *s = opaque;
 131     int index;
 132     uint32_t val = 0;
 133
 134     addr &= 0xff;
 135     if (addr == 0x00) {
 136         val = s->ioregsel;
 137     } else if (addr == 0x10) {
 138         switch (s->ioregsel) {
 139             case 0x00:
 140                 val = s->id << 24;
 141                 break;
 142             case 0x01:
 143                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
 144                 break;
 145             case 0x02:
 146                 val = 0;
 147                 break;
 148             default:
 149                 index = (s->ioregsel - 0x10) >> 1;
 150                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 151                     if (s->ioregsel & 1)
 152                         val = s->ioredtbl[index] >> 32;
 153                     else
 154                         val = s->ioredtbl[index] & 0xffffffff;
 155                 }
 156         }
 157 #ifdef DEBUG_IOAPIC
 158         printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
 159 #endif
 160     }
 161     return val;
 162 }
 163
 164 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 165 {
 166     IOAPICState *s = opaque;
 167     int index;
 168
 169     addr &= 0xff;
 170     if (addr == 0x00)  {
 171         s->ioregsel = val;
 172         return;
 173     } else if (addr == 0x10) {
 174 #ifdef DEBUG_IOAPIC
 175         printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
 176 #endif
 177         switch (s->ioregsel) {
 178             case 0x00:
 179                 s->id = (val >> 24) & 0xff;
 180                 return;
 181             case 0x01:
 182             case 0x02:
 183                 return;
 184             default:
 185                 index = (s->ioregsel - 0x10) >> 1;
 186                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 187                     if (s->ioregsel & 1) {
 188                         s->ioredtbl[index] &= 0xffffffff;
 189                         s->ioredtbl[index] |= (uint64_t)val << 32;
 190                     } else {
 191                         s->ioredtbl[index] &= ~0xffffffffULL;
 192                         s->ioredtbl[index] |= val;
 193                     }
 194                     ioapic_service(s);
 195                 }
 196         }
 197     }
 198 }
 199
 200 static void kvm_kernel_ioapic_save_to_user(IOAPICState *s)
 201 {
 202 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 203     struct kvm_irqchip chip;
 204     struct kvm_ioapic_state *kioapic;
 205     int i;
 206
 207     chip.chip_id = KVM_IRQCHIP_IOAPIC;
 208     kvm_get_irqchip(kvm_context, &chip);
 209     kioapic = &chip.chip.ioapic;
 210
 211     s->id = kioapic->id;
 212     s->ioregsel = kioapic->ioregsel;
 213     s->base_address = kioapic->base_address;
 214     s->irr = kioapic->irr;
 215     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 216         s->ioredtbl[i] = kioapic->redirtbl[i].bits;
 217     }
 218 #endif
 219 }
 220
 221 static void kvm_kernel_ioapic_load_from_user(IOAPICState *s)
 222 {
 223 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 224     struct kvm_irqchip chip;
 225     struct kvm_ioapic_state *kioapic;
 226     int i;
 227
 228     chip.chip_id = KVM_IRQCHIP_IOAPIC;
 229     kioapic = &chip.chip.ioapic;
 230
 231     kioapic->id = s->id;
 232     kioapic->ioregsel = s->ioregsel;
 233     kioapic->base_address = s->base_address;
 234     kioapic->irr = s->irr;
 235     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 236         kioapic->redirtbl[i].bits = s->ioredtbl[i];
 237     }
 238
 239     kvm_set_irqchip(kvm_context, &chip);
 240 #endif
 241 }
 242
 243 static void ioapic_pre_save(void *opaque)
 244 {
 245     IOAPICState *s = (void *)opaque;
 246
 247     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 248         kvm_kernel_ioapic_save_to_user(s);
 249     }
 250 }
 251
 252 static int ioapic_pre_load(void *opaque)
 253 {
 254     IOAPICState *s = opaque;
 255
 256     /* in case we are doing version 1, we just set these to sane values */
 257     s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 258     s->irr = 0;
 259     return 0;
 260 }
 261
 262 static int ioapic_post_load(void *opaque, int version_id)
 263 {
 264     IOAPICState *s = opaque;
 265
 266     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 267         kvm_kernel_ioapic_load_from_user(s);
 268     }
 269     return 0;
 270 }
 271
 272 static const VMStateDescription vmstate_ioapic = {
 273     .name = "ioapic",
 274     .version_id = 2,
 275     .minimum_version_id = 1,
 276     .minimum_version_id_old = 1,
 277     .pre_load = ioapic_pre_load,
 278     .post_load = ioapic_post_load,
 279     .pre_save = ioapic_pre_save,
 280     .fields      = (VMStateField []) {
 281         VMSTATE_UINT8(id, IOAPICState),
 282         VMSTATE_UINT8(ioregsel, IOAPICState),
 283         VMSTATE_UINT64_V(base_address, IOAPICState, 2),
 284         VMSTATE_UINT32_V(irr, IOAPICState, 2),
 285         VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
 286         VMSTATE_END_OF_LIST()
 287     }
 288 };
 289
 290 static void ioapic_reset(void *opaque)
 291 {
 292     IOAPICState *s = opaque;
 293     int i;
 294
 295     memset(s, 0, sizeof(*s));
 296     s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 297     for(i = 0; i < IOAPIC_NUM_PINS; i++)
 298         s->ioredtbl[i] = 1 << 16; /* mask LVT */
 299 #ifdef KVM_CAP_IRQCHIP
 300     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 301         kvm_kernel_ioapic_load_from_user(s);
 302     }
 303 #endif
 304 }
 305
 306 static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
 307     ioapic_mem_readl,
 308     ioapic_mem_readl,
 309     ioapic_mem_readl,
 310 };
 311
 312 static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
 313     ioapic_mem_writel,
 314     ioapic_mem_writel,
 315     ioapic_mem_writel,
 316 };
 317
 318 qemu_irq *ioapic_init(void)
 319 {
 320     IOAPICState *s;
 321     qemu_irq *irq;
 322     int io_memory;
 323
 324     s = qemu_mallocz(sizeof(IOAPICState));
 325     ioapic_reset(s);
 326
 327     io_memory = cpu_register_io_memory(ioapic_mem_read,
 328                                        ioapic_mem_write, s);
 329     cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
 330
 331     vmstate_register(0, &vmstate_ioapic, s);
 332     qemu_register_reset(ioapic_reset, s);
 333     irq = qemu_allocate_irqs(ioapic_set_irq, s, IOAPIC_NUM_PINS);
 334
 335     return irq;
 336 }