hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "monitor.h"
  28 #include "qemu-timer.h"
  29
  30 #include "qemu-kvm.h"
  31
  32 /* debug PIC */
  33 //#define DEBUG_PIC
  34
  35 //#define DEBUG_IRQ_LATENCY
  36 //#define DEBUG_IRQ_COUNT
  37
  38 typedef struct PicState {
  39     uint8_t last_irr; /* edge detection */
  40     uint8_t irr; /* interrupt request register */
  41     uint8_t imr; /* interrupt mask register */
  42     uint8_t isr; /* interrupt service register */
  43     uint8_t priority_add; /* highest irq priority */
  44     uint8_t irq_base;
  45     uint8_t read_reg_select;
  46     uint8_t poll;
  47     uint8_t special_mask;
  48     uint8_t init_state;
  49     uint8_t auto_eoi;
  50     uint8_t rotate_on_auto_eoi;
  51     uint8_t special_fully_nested_mode;
  52     uint8_t init4; /* true if 4 byte init */
  53     uint8_t single_mode; /* true if slave pic is not initialized */
  54     uint8_t elcr; /* PIIX edge/trigger selection*/
  55     uint8_t elcr_mask;
  56     PicState2 *pics_state;
  57 } PicState;
  58
  59 struct PicState2 {
  60     /* 0 is master pic, 1 is slave pic */
  61     /* XXX: better separation between the two pics */
  62     PicState pics[2];
  63     qemu_irq parent_irq;
  64     void *irq_request_opaque;
  65 };
  66
  67 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  68 static int irq_level[16];
  69 #endif
  70 #ifdef DEBUG_IRQ_COUNT
  71 static uint64_t irq_count[16];
  72 #endif
  73
  74 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  75 static inline void pic_set_irq1(PicState *s, int irq, int level)
  76 {
  77     int mask;
  78     mask = 1 << irq;
  79     if (s->elcr & mask) {
  80         /* level triggered */
  81         if (level) {
  82             s->irr |= mask;
  83             s->last_irr |= mask;
  84         } else {
  85             s->irr &= ~mask;
  86             s->last_irr &= ~mask;
  87         }
  88     } else {
  89         /* edge triggered */
  90         if (level) {
  91             if ((s->last_irr & mask) == 0)
  92                 s->irr |= mask;
  93             s->last_irr |= mask;
  94         } else {
  95             s->last_irr &= ~mask;
  96         }
  97     }
  98 }
  99
 100 /* return the highest priority found in mask (highest = smallest
 101    number). Return 8 if no irq */
 102 static inline int get_priority(PicState *s, int mask)
 103 {
 104     int priority;
 105     if (mask == 0)
 106         return 8;
 107     priority = 0;
 108     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 109         priority++;
 110     return priority;
 111 }
 112
 113 /* return the pic wanted interrupt. return -1 if none */
 114 static int pic_get_irq(PicState *s)
 115 {
 116     int mask, cur_priority, priority;
 117
 118     mask = s->irr & ~s->imr;
 119     priority = get_priority(s, mask);
 120     if (priority == 8)
 121         return -1;
 122     /* compute current priority. If special fully nested mode on the
 123        master, the IRQ coming from the slave is not taken into account
 124        for the priority computation. */
 125     mask = s->isr;
 126     if (s->special_mask)
 127         mask &= ~s->imr;
 128     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 129         mask &= ~(1 << 2);
 130     cur_priority = get_priority(s, mask);
 131     if (priority < cur_priority) {
 132         /* higher priority found: an irq should be generated */
 133         return (priority + s->priority_add) & 7;
 134     } else {
 135         return -1;
 136     }
 137 }
 138
 139 /* raise irq to CPU if necessary. must be called every time the active
 140    irq may change */
 141 /* XXX: should not export it, but it is needed for an APIC kludge */
 142 void pic_update_irq(PicState2 *s)
 143 {
 144     int irq2, irq;
 145
 146     /* first look at slave pic */
 147     irq2 = pic_get_irq(&s->pics[1]);
 148     if (irq2 >= 0) {
 149         /* if irq request by slave pic, signal master PIC */
 150         pic_set_irq1(&s->pics[0], 2, 1);
 151         pic_set_irq1(&s->pics[0], 2, 0);
 152     }
 153     /* look at requested irq */
 154     irq = pic_get_irq(&s->pics[0]);
 155     if (irq >= 0) {
 156 #if defined(DEBUG_PIC)
 157         {
 158             int i;
 159             for(i = 0; i < 2; i++) {
 160                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 161                        i, s->pics[i].imr, s->pics[i].irr,
 162                        s->pics[i].priority_add);
 163
 164             }
 165         }
 166         printf("pic: cpu_interrupt\n");
 167 #endif
 168         qemu_irq_raise(s->parent_irq);
 169     }
 170
 171 /* all targets should do this rather than acking the IRQ in the cpu */
 172 #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)
 173     else {
 174         qemu_irq_lower(s->parent_irq);
 175     }
 176 #endif
 177 }
 178
 179 #ifdef DEBUG_IRQ_LATENCY
 180 int64_t irq_time[16];
 181 #endif
 182
 183 static void i8259_set_irq(void *opaque, int irq, int level)
 184 {
 185     PicState2 *s = opaque;
 186 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 187     if (level != irq_level[irq]) {
 188 #if defined(DEBUG_PIC)
 189         printf("i8259_set_irq: irq=%d level=%d\n", irq, level);
 190 #endif
 191         irq_level[irq] = level;
 192 #ifdef DEBUG_IRQ_COUNT
 193         if (level == 1)
 194             irq_count[irq]++;
 195 #endif
 196     }
 197 #endif
 198 #ifdef DEBUG_IRQ_LATENCY
 199     if (level) {
 200         irq_time[irq] = qemu_get_clock(vm_clock);
 201     }
 202 #endif
 203     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 204     pic_update_irq(s);
 205 }
 206
 207 /* acknowledge interrupt 'irq' */
 208 static inline void pic_intack(PicState *s, int irq)
 209 {
 210     if (s->auto_eoi) {
 211         if (s->rotate_on_auto_eoi)
 212             s->priority_add = (irq + 1) & 7;
 213     } else {
 214         s->isr |= (1 << irq);
 215     }
 216
 217     /* We don't clear a level sensitive interrupt here */
 218     if (!(s->elcr & (1 << irq)))
 219         s->irr &= ~(1 << irq);
 220
 221 }
 222
 223 extern int time_drift_fix;
 224
 225 int pic_read_irq(PicState2 *s)
 226 {
 227     int irq, irq2, intno;
 228
 229     irq = pic_get_irq(&s->pics[0]);
 230     if (irq >= 0) {
 231
 232         pic_intack(&s->pics[0], irq);
 233 #ifndef TARGET_IA64
 234         if (time_drift_fix && irq == 0) {
 235             extern int64_t timer_acks, timer_ints_to_push;
 236             timer_acks++;
 237             if (timer_ints_to_push > 0) {
 238                 timer_ints_to_push--;
 239                 /* simulate an edge irq0, like the one generated by i8254 */
 240                 pic_set_irq1(&s->pics[0], 0, 0);
 241                 pic_set_irq1(&s->pics[0], 0, 1);
 242             }
 243         }
 244 #endif
 245         if (irq == 2) {
 246             irq2 = pic_get_irq(&s->pics[1]);
 247             if (irq2 >= 0) {
 248                 pic_intack(&s->pics[1], irq2);
 249             } else {
 250                 /* spurious IRQ on slave controller */
 251                 irq2 = 7;
 252             }
 253             intno = s->pics[1].irq_base + irq2;
 254             irq = irq2 + 8;
 255         } else {
 256             intno = s->pics[0].irq_base + irq;
 257         }
 258     } else {
 259         /* spurious IRQ on host controller */
 260         irq = 7;
 261         intno = s->pics[0].irq_base + irq;
 262     }
 263     pic_update_irq(s);
 264
 265 #ifdef DEBUG_IRQ_LATENCY
 266     printf("IRQ%d latency=%0.3fus\n",
 267            irq,
 268            (double)(qemu_get_clock(vm_clock) -
 269                     irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
 270 #endif
 271 #if defined(DEBUG_PIC)
 272     printf("pic_interrupt: irq=%d\n", irq);
 273 #endif
 274     return intno;
 275 }
 276
 277 static void pic_reset(void *opaque)
 278 {
 279     PicState *s = opaque;
 280
 281     s->last_irr = 0;
 282     s->irr = 0;
 283     s->imr = 0;
 284     s->isr = 0;
 285     s->priority_add = 0;
 286     s->irq_base = 0;
 287     s->read_reg_select = 0;
 288     s->poll = 0;
 289     s->special_mask = 0;
 290     s->init_state = 0;
 291     s->auto_eoi = 0;
 292     s->rotate_on_auto_eoi = 0;
 293     s->special_fully_nested_mode = 0;
 294     s->init4 = 0;
 295     s->single_mode = 0;
 296     /* Note: ELCR is not reset */
 297 }
 298
 299 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 300 {
 301     PicState *s = opaque;
 302     int priority, cmd, irq;
 303
 304 #ifdef DEBUG_PIC
 305     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 306 #endif
 307     addr &= 1;
 308     if (addr == 0) {
 309         if (val & 0x10) {
 310             /* init */
 311             pic_reset(s);
 312             /* deassert a pending interrupt */
 313             qemu_irq_lower(s->pics_state->parent_irq);
 314             s->init_state = 1;
 315             s->init4 = val & 1;
 316             s->single_mode = val & 2;
 317             if (val & 0x08)
 318                 hw_error("level sensitive irq not supported");
 319         } else if (val & 0x08) {
 320             if (val & 0x04)
 321                 s->poll = 1;
 322             if (val & 0x02)
 323                 s->read_reg_select = val & 1;
 324             if (val & 0x40)
 325                 s->special_mask = (val >> 5) & 1;
 326         } else {
 327             cmd = val >> 5;
 328             switch(cmd) {
 329             case 0:
 330             case 4:
 331                 s->rotate_on_auto_eoi = cmd >> 2;
 332                 break;
 333             case 1: /* end of interrupt */
 334             case 5:
 335                 priority = get_priority(s, s->isr);
 336                 if (priority != 8) {
 337                     irq = (priority + s->priority_add) & 7;
 338                     s->isr &= ~(1 << irq);
 339                     if (cmd == 5)
 340                         s->priority_add = (irq + 1) & 7;
 341                     pic_update_irq(s->pics_state);
 342                 }
 343                 break;
 344             case 3:
 345                 irq = val & 7;
 346                 s->isr &= ~(1 << irq);
 347                 pic_update_irq(s->pics_state);
 348                 break;
 349             case 6:
 350                 s->priority_add = (val + 1) & 7;
 351                 pic_update_irq(s->pics_state);
 352                 break;
 353             case 7:
 354                 irq = val & 7;
 355                 s->isr &= ~(1 << irq);
 356                 s->priority_add = (irq + 1) & 7;
 357                 pic_update_irq(s->pics_state);
 358                 break;
 359             default:
 360                 /* no operation */
 361                 break;
 362             }
 363         }
 364     } else {
 365         switch(s->init_state) {
 366         case 0:
 367             /* normal mode */
 368             s->imr = val;
 369             pic_update_irq(s->pics_state);
 370             break;
 371         case 1:
 372             s->irq_base = val & 0xf8;
 373             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 374             break;
 375         case 2:
 376             if (s->init4) {
 377                 s->init_state = 3;
 378             } else {
 379                 s->init_state = 0;
 380             }
 381             break;
 382         case 3:
 383             s->special_fully_nested_mode = (val >> 4) & 1;
 384             s->auto_eoi = (val >> 1) & 1;
 385             s->init_state = 0;
 386             break;
 387         }
 388     }
 389 }
 390
 391 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 392 {
 393     int ret;
 394
 395     ret = pic_get_irq(s);
 396     if (ret >= 0) {
 397         if (addr1 >> 7) {
 398             s->pics_state->pics[0].isr &= ~(1 << 2);
 399             s->pics_state->pics[0].irr &= ~(1 << 2);
 400         }
 401         s->irr &= ~(1 << ret);
 402         s->isr &= ~(1 << ret);
 403         if (addr1 >> 7 || ret != 2)
 404             pic_update_irq(s->pics_state);
 405     } else {
 406         ret = 0x07;
 407         pic_update_irq(s->pics_state);
 408     }
 409
 410     return ret;
 411 }
 412
 413 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 414 {
 415     PicState *s = opaque;
 416     unsigned int addr;
 417     int ret;
 418
 419     addr = addr1;
 420     addr &= 1;
 421     if (s->poll) {
 422         ret = pic_poll_read(s, addr1);
 423         s->poll = 0;
 424     } else {
 425         if (addr == 0) {
 426             if (s->read_reg_select)
 427                 ret = s->isr;
 428             else
 429                 ret = s->irr;
 430         } else {
 431             ret = s->imr;
 432         }
 433     }
 434 #ifdef DEBUG_PIC
 435     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 436 #endif
 437     return ret;
 438 }
 439
 440 /* memory mapped interrupt status */
 441 /* XXX: may be the same than pic_read_irq() */
 442 uint32_t pic_intack_read(PicState2 *s)
 443 {
 444     int ret;
 445
 446     ret = pic_poll_read(&s->pics[0], 0x00);
 447     if (ret == 2)
 448         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 449     /* Prepare for ISR read */
 450     s->pics[0].read_reg_select = 1;
 451
 452     return ret;
 453 }
 454
 455 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 456 {
 457     PicState *s = opaque;
 458     s->elcr = val & s->elcr_mask;
 459 }
 460
 461 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 462 {
 463     PicState *s = opaque;
 464     return s->elcr;
 465 }
 466
 467 #ifdef KVM_CAP_IRQCHIP
 468 static void kvm_kernel_pic_save_to_user(void *opaque);
 469 static int kvm_kernel_pic_load_from_user(void *opaque, int version_id);
 470 #endif
 471
 472 static const VMStateDescription vmstate_pic = {
 473     .name = "i8259",
 474     .version_id = 1,
 475 #ifdef KVM_CAP_IRQCHIP
 476     .pre_save = kvm_kernel_pic_save_to_user,
 477     .post_load = kvm_kernel_pic_load_from_user,
 478 #endif
 479     .minimum_version_id = 1,
 480     .minimum_version_id_old = 1,
 481     .fields      = (VMStateField []) {
 482         VMSTATE_UINT8(last_irr, PicState),
 483         VMSTATE_UINT8(irr, PicState),
 484         VMSTATE_UINT8(imr, PicState),
 485         VMSTATE_UINT8(isr, PicState),
 486         VMSTATE_UINT8(priority_add, PicState),
 487         VMSTATE_UINT8(irq_base, PicState),
 488         VMSTATE_UINT8(read_reg_select, PicState),
 489         VMSTATE_UINT8(poll, PicState),
 490         VMSTATE_UINT8(special_mask, PicState),
 491         VMSTATE_UINT8(init_state, PicState),
 492         VMSTATE_UINT8(auto_eoi, PicState),
 493         VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
 494         VMSTATE_UINT8(special_fully_nested_mode, PicState),
 495         VMSTATE_UINT8(init4, PicState),
 496         VMSTATE_UINT8(single_mode, PicState),
 497         VMSTATE_UINT8(elcr, PicState),
 498         VMSTATE_END_OF_LIST()
 499     }
 500 };
 501
 502 /* XXX: add generic master/slave system */
 503 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 504 {
 505     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 506     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 507     if (elcr_addr >= 0) {
 508         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 509         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 510     }
 511     vmstate_register(io_addr, &vmstate_pic, s);
 512     qemu_register_reset(pic_reset, s);
 513 }
 514
 515 void pic_info(Monitor *mon)
 516 {
 517     int i;
 518     PicState *s;
 519
 520     if (!isa_pic)
 521         return;
 522
 523     for(i=0;i<2;i++) {
 524         s = &isa_pic->pics[i];
 525         monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
 526                        "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 527                        i, s->irr, s->imr, s->isr, s->priority_add,
 528                        s->irq_base, s->read_reg_select, s->elcr,
 529                        s->special_fully_nested_mode);
 530     }
 531 }
 532
 533 void irq_info(Monitor *mon)
 534 {
 535 #ifndef DEBUG_IRQ_COUNT
 536     monitor_printf(mon, "irq statistic code not compiled.\n");
 537 #else
 538     int i;
 539     int64_t count;
 540
 541     monitor_printf(mon, "IRQ statistics:\n");
 542     for (i = 0; i < 16; i++) {
 543         count = irq_count[i];
 544         if (count > 0)
 545             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 546     }
 547 #endif
 548 }
 549
 550 qemu_irq *i8259_init(qemu_irq parent_irq)
 551 {
 552     PicState2 *s;
 553
 554     s = qemu_mallocz(sizeof(PicState2));
 555     pic_init1(0x20, 0x4d0, &s->pics[0]);
 556     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 557     s->pics[0].elcr_mask = 0xf8;
 558     s->pics[1].elcr_mask = 0xde;
 559     s->parent_irq = parent_irq;
 560     s->pics[0].pics_state = s;
 561     s->pics[1].pics_state = s;
 562     isa_pic = s;
 563     return qemu_allocate_irqs(i8259_set_irq, s, 16);
 564 }
 565
 566 #ifdef KVM_CAP_IRQCHIP
 567 static void kvm_kernel_pic_save_to_user(void *opaque)
 568 {
 569 #if defined(TARGET_I386)
 570     PicState *s = (void *)opaque;
 571     struct kvm_irqchip chip;
 572     struct kvm_pic_state *kpic;
 573
 574     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 575                    KVM_IRQCHIP_PIC_MASTER :
 576                    KVM_IRQCHIP_PIC_SLAVE;
 577     kvm_get_irqchip(kvm_context, &chip);
 578     kpic = &chip.chip.pic;
 579
 580     s->last_irr = kpic->last_irr;
 581     s->irr = kpic->irr;
 582     s->imr = kpic->imr;
 583     s->isr = kpic->isr;
 584     s->priority_add = kpic->priority_add;
 585     s->irq_base = kpic->irq_base;
 586     s->read_reg_select = kpic->read_reg_select;
 587     s->poll = kpic->poll;
 588     s->special_mask = kpic->special_mask;
 589     s->init_state = kpic->init_state;
 590     s->auto_eoi = kpic->auto_eoi;
 591     s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
 592     s->special_fully_nested_mode = kpic->special_fully_nested_mode;
 593     s->init4 = kpic->init4;
 594     s->elcr = kpic->elcr;
 595     s->elcr_mask = kpic->elcr_mask;
 596 #endif
 597 }
 598
 599 static int kvm_kernel_pic_load_from_user(void *opaque, int version)
 600 {
 601 #if defined(TARGET_I386)
 602     PicState *s = (void *)opaque;
 603     struct kvm_irqchip chip;
 604     struct kvm_pic_state *kpic;
 605
 606     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 607                    KVM_IRQCHIP_PIC_MASTER :
 608                    KVM_IRQCHIP_PIC_SLAVE;
 609     kpic = &chip.chip.pic;
 610
 611     kpic->last_irr = s->last_irr;
 612     kpic->irr = s->irr;
 613     kpic->imr = s->imr;
 614     kpic->isr = s->isr;
 615     kpic->priority_add = s->priority_add;
 616     kpic->irq_base = s->irq_base;
 617     kpic->read_reg_select = s->read_reg_select;
 618     kpic->poll = s->poll;
 619     kpic->special_mask = s->special_mask;
 620     kpic->init_state = s->init_state;
 621     kpic->auto_eoi = s->auto_eoi;
 622     kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
 623     kpic->special_fully_nested_mode = s->special_fully_nested_mode;
 624     kpic->init4 = s->init4;
 625     kpic->elcr = s->elcr;
 626     kpic->elcr_mask = s->elcr_mask;
 627
 628     kvm_set_irqchip(kvm_context, &chip);
 629 #endif
 630     return 0;
 631 }
 632
 633 static void kvm_i8259_set_irq(void *opaque, int irq, int level)
 634 {
 635     int pic_ret;
 636     if (kvm_set_irq(irq, level, &pic_ret)) {
 637         if (pic_ret != 0)
 638             apic_set_irq_delivered();
 639         return;
 640     }
 641 }
 642
 643 static void kvm_pic_init1(int io_addr, PicState *s)
 644 {
 645     vmstate_register(io_addr, &vmstate_pic, s);
 646     qemu_register_reset(pic_reset, s);
 647 }
 648
 649 qemu_irq *kvm_i8259_init(qemu_irq parent_irq)
 650 {
 651     PicState2 *s;
 652
 653     s = qemu_mallocz(sizeof(PicState2));
 654
 655     kvm_pic_init1(0x20, &s->pics[0]);
 656     kvm_pic_init1(0xa0, &s->pics[1]);
 657     s->parent_irq = parent_irq;
 658     s->pics[0].pics_state = s;
 659     s->pics[1].pics_state = s;
 660     isa_pic = s;
 661     return qemu_allocate_irqs(kvm_i8259_set_irq, s, 24);
 662 }
 663 #endif
 664
 665
 666