hw/i8254.c

   1 /*
   2  * QEMU 8253/8254 interval timer emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "qemu-timer.h"
  28 #include "qemu-kvm.h"
  29 #include "i8254.h"
  30
  31 //#define DEBUG_PIT
  32
  33 static PITState pit_state;
  34
  35 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
  36
  37 static int pit_get_count(PITChannelState *s)
  38 {
  39     uint64_t d;
  40     int counter;
  41
  42     d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ,
  43                  get_ticks_per_sec());
  44     switch(s->mode) {
  45     case 0:
  46     case 1:
  47     case 4:
  48     case 5:
  49         counter = (s->count - d) & 0xffff;
  50         break;
  51     case 3:
  52         /* XXX: may be incorrect for odd counts */
  53         counter = s->count - ((2 * d) % s->count);
  54         break;
  55     default:
  56         counter = s->count - (d % s->count);
  57         break;
  58     }
  59     return counter;
  60 }
  61
  62 /* get pit output bit */
  63 static int pit_get_out1(PITChannelState *s, int64_t current_time)
  64 {
  65     uint64_t d;
  66     int out;
  67
  68     d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
  69                  get_ticks_per_sec());
  70     switch(s->mode) {
  71     default:
  72     case 0:
  73         out = (d >= s->count);
  74         break;
  75     case 1:
  76         out = (d < s->count);
  77         break;
  78     case 2:
  79         if ((d % s->count) == 0 && d != 0)
  80             out = 1;
  81         else
  82             out = 0;
  83         break;
  84     case 3:
  85         out = (d % s->count) < ((s->count + 1) >> 1);
  86         break;
  87     case 4:
  88     case 5:
  89         out = (d == s->count);
  90         break;
  91     }
  92     return out;
  93 }
  94
  95 int pit_get_out(PITState *pit, int channel, int64_t current_time)
  96 {
  97     PITChannelState *s = &pit->channels[channel];
  98     return pit_get_out1(s, current_time);
  99 }
 100
 101 /* return -1 if no transition will occur.  */
 102 static int64_t pit_get_next_transition_time(PITChannelState *s,
 103                                             int64_t current_time)
 104 {
 105     uint64_t d, next_time, base;
 106     int period2;
 107
 108     d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
 109                  get_ticks_per_sec());
 110     switch(s->mode) {
 111     default:
 112     case 0:
 113     case 1:
 114         if (d < s->count)
 115             next_time = s->count;
 116         else
 117             return -1;
 118         break;
 119     case 2:
 120         base = (d / s->count) * s->count;
 121         if ((d - base) == 0 && d != 0)
 122             next_time = base + s->count;
 123         else
 124             next_time = base + s->count + 1;
 125         break;
 126     case 3:
 127         base = (d / s->count) * s->count;
 128         period2 = ((s->count + 1) >> 1);
 129         if ((d - base) < period2)
 130             next_time = base + period2;
 131         else
 132             next_time = base + s->count;
 133         break;
 134     case 4:
 135     case 5:
 136         if (d < s->count)
 137             next_time = s->count;
 138         else if (d == s->count)
 139             next_time = s->count + 1;
 140         else
 141             return -1;
 142         break;
 143     }
 144     /* convert to timer units */
 145     next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(),
 146                                               PIT_FREQ);
 147     /* fix potential rounding problems */
 148     /* XXX: better solution: use a clock at PIT_FREQ Hz */
 149     if (next_time <= current_time)
 150         next_time = current_time + 1;
 151     return next_time;
 152 }
 153
 154 /* val must be 0 or 1 */
 155 void pit_set_gate(PITState *pit, int channel, int val)
 156 {
 157     PITChannelState *s = &pit->channels[channel];
 158
 159     switch(s->mode) {
 160     default:
 161     case 0:
 162     case 4:
 163         /* XXX: just disable/enable counting */
 164         break;
 165     case 1:
 166     case 5:
 167         if (s->gate < val) {
 168             /* restart counting on rising edge */
 169             s->count_load_time = qemu_get_clock(vm_clock);
 170             pit_irq_timer_update(s, s->count_load_time);
 171         }
 172         break;
 173     case 2:
 174     case 3:
 175         if (s->gate < val) {
 176             /* restart counting on rising edge */
 177             s->count_load_time = qemu_get_clock(vm_clock);
 178             pit_irq_timer_update(s, s->count_load_time);
 179         }
 180         /* XXX: disable/enable counting */
 181         break;
 182     }
 183     s->gate = val;
 184 }
 185
 186 int pit_get_gate(PITState *pit, int channel)
 187 {
 188     PITChannelState *s = &pit->channels[channel];
 189     return s->gate;
 190 }
 191
 192 int pit_get_initial_count(PITState *pit, int channel)
 193 {
 194     PITChannelState *s = &pit->channels[channel];
 195     return s->count;
 196 }
 197
 198 int pit_get_mode(PITState *pit, int channel)
 199 {
 200     PITChannelState *s = &pit->channels[channel];
 201     return s->mode;
 202 }
 203
 204 static inline void pit_load_count(PITState *s, int val, int chan)
 205 {
 206     if (val == 0)
 207         val = 0x10000;
 208     s->channels[chan].count_load_time = qemu_get_clock(vm_clock);
 209     s->channels[chan].count = val;
 210 #ifdef TARGET_I386
 211     if (chan == 0 && pit_state.flags & PIT_FLAGS_HPET_LEGACY) {
 212         return;
 213     }
 214 #endif
 215     pit_irq_timer_update(&s->channels[chan], s->channels[chan].count_load_time);
 216 }
 217
 218 /* if already latched, do not latch again */
 219 static void pit_latch_count(PITChannelState *s)
 220 {
 221     if (!s->count_latched) {
 222         s->latched_count = pit_get_count(s);
 223         s->count_latched = s->rw_mode;
 224     }
 225 }
 226
 227 static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 228 {
 229     PITState *pit = opaque;
 230     int channel, access;
 231     PITChannelState *s;
 232
 233     addr &= 3;
 234     if (addr == 3) {
 235         channel = val >> 6;
 236         if (channel == 3) {
 237             /* read back command */
 238             for(channel = 0; channel < 3; channel++) {
 239                 s = &pit->channels[channel];
 240                 if (val & (2 << channel)) {
 241                     if (!(val & 0x20)) {
 242                         pit_latch_count(s);
 243                     }
 244                     if (!(val & 0x10) && !s->status_latched) {
 245                         /* status latch */
 246                         /* XXX: add BCD and null count */
 247                         s->status =  (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) |
 248                             (s->rw_mode << 4) |
 249                             (s->mode << 1) |
 250                             s->bcd;
 251                         s->status_latched = 1;
 252                     }
 253                 }
 254             }
 255         } else {
 256             s = &pit->channels[channel];
 257             access = (val >> 4) & 3;
 258             if (access == 0) {
 259                 pit_latch_count(s);
 260             } else {
 261                 s->rw_mode = access;
 262                 s->read_state = access;
 263                 s->write_state = access;
 264
 265                 s->mode = (val >> 1) & 7;
 266                 s->bcd = val & 1;
 267                 /* XXX: update irq timer ? */
 268             }
 269         }
 270     } else {
 271         s = &pit->channels[addr];
 272         switch(s->write_state) {
 273         default:
 274         case RW_STATE_LSB:
 275             pit_load_count(pit, val, addr);
 276             break;
 277         case RW_STATE_MSB:
 278             pit_load_count(pit, val << 8, addr);
 279             break;
 280         case RW_STATE_WORD0:
 281             s->write_latch = val;
 282             s->write_state = RW_STATE_WORD1;
 283             break;
 284         case RW_STATE_WORD1:
 285             pit_load_count(pit, s->write_latch | (val << 8), addr);
 286             s->write_state = RW_STATE_WORD0;
 287             break;
 288         }
 289     }
 290 }
 291
 292 static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
 293 {
 294     PITState *pit = opaque;
 295     int ret, count;
 296     PITChannelState *s;
 297
 298     addr &= 3;
 299     s = &pit->channels[addr];
 300     if (s->status_latched) {
 301         s->status_latched = 0;
 302         ret = s->status;
 303     } else if (s->count_latched) {
 304         switch(s->count_latched) {
 305         default:
 306         case RW_STATE_LSB:
 307             ret = s->latched_count & 0xff;
 308             s->count_latched = 0;
 309             break;
 310         case RW_STATE_MSB:
 311             ret = s->latched_count >> 8;
 312             s->count_latched = 0;
 313             break;
 314         case RW_STATE_WORD0:
 315             ret = s->latched_count & 0xff;
 316             s->count_latched = RW_STATE_MSB;
 317             break;
 318         }
 319     } else {
 320         switch(s->read_state) {
 321         default:
 322         case RW_STATE_LSB:
 323             count = pit_get_count(s);
 324             ret = count & 0xff;
 325             break;
 326         case RW_STATE_MSB:
 327             count = pit_get_count(s);
 328             ret = (count >> 8) & 0xff;
 329             break;
 330         case RW_STATE_WORD0:
 331             count = pit_get_count(s);
 332             ret = count & 0xff;
 333             s->read_state = RW_STATE_WORD1;
 334             break;
 335         case RW_STATE_WORD1:
 336             count = pit_get_count(s);
 337             ret = (count >> 8) & 0xff;
 338             s->read_state = RW_STATE_WORD0;
 339             break;
 340         }
 341     }
 342     return ret;
 343 }
 344
 345 /* global counters for time-drift fix */
 346 int64_t timer_acks=0, timer_interrupts=0, timer_ints_to_push=0;
 347
 348 extern int time_drift_fix;
 349
 350 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
 351 {
 352     int64_t expire_time;
 353     int irq_level;
 354
 355     if (!s->irq_timer)
 356         return;
 357     expire_time = pit_get_next_transition_time(s, current_time);
 358     irq_level = pit_get_out1(s, current_time);
 359     qemu_set_irq(s->irq, irq_level);
 360     if (time_drift_fix && irq_level==1) {
 361         /* FIXME: fine tune timer_max_fix (max fix per tick).
 362          *        Should it be 1 (double time), 2 , 4, 10 ?
 363          *        Currently setting it to 5% of PIT-ticks-per-second (per PIT-tick)
 364          */
 365         const long pit_ticks_per_sec = (s->count>0) ? (PIT_FREQ/s->count) : 0;
 366         const long timer_max_fix = pit_ticks_per_sec/20;
 367         const long delta = timer_interrupts - timer_acks;
 368         const long max_delta = pit_ticks_per_sec * 60; /* one minute */
 369         if ((delta >  max_delta) && (pit_ticks_per_sec > 0)) {
 370             printf("time drift is too long, %ld seconds were lost\n", delta/pit_ticks_per_sec);
 371             timer_acks = timer_interrupts;
 372             timer_ints_to_push = 0;
 373         } else if (delta > 0) {
 374             timer_ints_to_push = MIN(delta, timer_max_fix);
 375         }
 376         timer_interrupts++;
 377     }
 378 #ifdef DEBUG_PIT
 379     printf("irq_level=%d next_delay=%f\n",
 380            irq_level,
 381            (double)(expire_time - current_time) / get_ticks_per_sec());
 382 #endif
 383     s->next_transition_time = expire_time;
 384     if (expire_time != -1) {
 385         qemu_mod_timer(s->irq_timer, expire_time);
 386     } else {
 387         qemu_del_timer(s->irq_timer);
 388     }
 389 }
 390
 391 static void pit_irq_timer(void *opaque)
 392 {
 393     PITChannelState *s = opaque;
 394
 395     pit_irq_timer_update(s, s->next_transition_time);
 396 }
 397
 398 static const VMStateDescription vmstate_pit_channel = {
 399     .name = "pit channel",
 400     .version_id = 2,
 401     .minimum_version_id = 2,
 402     .minimum_version_id_old = 2,
 403     .fields      = (VMStateField []) {
 404         VMSTATE_INT32(count, PITChannelState),
 405         VMSTATE_UINT16(latched_count, PITChannelState),
 406         VMSTATE_UINT8(count_latched, PITChannelState),
 407         VMSTATE_UINT8(status_latched, PITChannelState),
 408         VMSTATE_UINT8(status, PITChannelState),
 409         VMSTATE_UINT8(read_state, PITChannelState),
 410         VMSTATE_UINT8(write_state, PITChannelState),
 411         VMSTATE_UINT8(write_latch, PITChannelState),
 412         VMSTATE_UINT8(rw_mode, PITChannelState),
 413         VMSTATE_UINT8(mode, PITChannelState),
 414         VMSTATE_UINT8(bcd, PITChannelState),
 415         VMSTATE_UINT8(gate, PITChannelState),
 416         VMSTATE_INT64(count_load_time, PITChannelState),
 417         VMSTATE_INT64(next_transition_time, PITChannelState),
 418         VMSTATE_END_OF_LIST()
 419     }
 420 };
 421
 422 static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
 423 {
 424     PITState *pit = opaque;
 425     PITChannelState *s;
 426     int i;
 427
 428     if (version_id != PIT_SAVEVM_VERSION)
 429         return -EINVAL;
 430
 431     pit->flags = qemu_get_be32(f);
 432     for(i = 0; i < 3; i++) {
 433         s = &pit->channels[i];
 434         s->count=qemu_get_be32(f);
 435         qemu_get_be16s(f, &s->latched_count);
 436         qemu_get_8s(f, &s->count_latched);
 437         qemu_get_8s(f, &s->status_latched);
 438         qemu_get_8s(f, &s->status);
 439         qemu_get_8s(f, &s->read_state);
 440         qemu_get_8s(f, &s->write_state);
 441         qemu_get_8s(f, &s->write_latch);
 442         qemu_get_8s(f, &s->rw_mode);
 443         qemu_get_8s(f, &s->mode);
 444         qemu_get_8s(f, &s->bcd);
 445         qemu_get_8s(f, &s->gate);
 446         s->count_load_time=qemu_get_be64(f);
 447         if (s->irq_timer) {
 448             s->next_transition_time=qemu_get_be64(f);
 449             qemu_get_timer(f, s->irq_timer);
 450         }
 451     }
 452
 453     return 0;
 454 }
 455
 456 VMStateDescription vmstate_pit = {
 457     .name = "i8254",
 458     .version_id = 2,
 459     .minimum_version_id = 2,
 460     .minimum_version_id_old = 1,
 461     .load_state_old = pit_load_old,
 462     .fields      = (VMStateField []) {
 463         VMSTATE_UINT32(flags, PITState),
 464         VMSTATE_STRUCT_ARRAY(channels, PITState, 3, 2, vmstate_pit_channel, PITChannelState),
 465         VMSTATE_TIMER(channels[0].irq_timer, PITState),
 466         VMSTATE_END_OF_LIST()
 467     }
 468 };
 469
 470 void pit_reset(void *opaque)
 471 {
 472     PITState *pit = opaque;
 473     PITChannelState *s;
 474     int i;
 475
 476 #ifdef TARGET_I386
 477     pit->flags &= ~PIT_FLAGS_HPET_LEGACY;
 478 #endif
 479     for(i = 0;i < 3; i++) {
 480         s = &pit->channels[i];
 481         s->mode = 3;
 482         s->gate = (i != 2);
 483         pit_load_count(pit, 0, i);
 484     }
 485 }
 486
 487 #ifdef TARGET_I386
 488 /* When HPET is operating in legacy mode, i8254 timer0 is disabled */
 489
 490 void hpet_disable_pit(void)
 491 {
 492     PITChannelState *s = &pit_state.channels[0];
 493
 494     if (kvm_enabled() && qemu_kvm_pit_in_kernel()) {
 495         if (qemu_kvm_has_pit_state2()) {
 496             kvm_hpet_disable_kpit();
 497         } else {
 498              fprintf(stderr, "%s: kvm does not support pit_state2!\n", __FUNCTION__);
 499              exit(1);
 500         }
 501     } else {
 502         pit_state.flags |= PIT_FLAGS_HPET_LEGACY;
 503         if (s->irq_timer) {
 504             qemu_del_timer(s->irq_timer);
 505         }
 506     }
 507 }
 508
 509 /* When HPET is reset or leaving legacy mode, it must reenable i8254
 510  * timer 0
 511  */
 512
 513 void hpet_enable_pit(void)
 514 {
 515     PITState *pit = &pit_state;
 516     PITChannelState *s = &pit->channels[0];
 517
 518     if (kvm_enabled() && qemu_kvm_pit_in_kernel()) {
 519         if (qemu_kvm_has_pit_state2()) {
 520             kvm_hpet_enable_kpit();
 521         } else {
 522              fprintf(stderr, "%s: kvm does not support pit_state2!\n", __FUNCTION__);
 523              exit(1);
 524         }
 525     } else {
 526         pit_state.flags &= ~PIT_FLAGS_HPET_LEGACY;
 527         pit_load_count(pit, s->count, 0);
 528     }
 529 }
 530 #endif
 531
 532 PITState *pit_init(int base, qemu_irq irq)
 533 {
 534     PITState *pit = &pit_state;
 535     PITChannelState *s;
 536
 537     s = &pit->channels[0];
 538     /* the timer 0 is connected to an IRQ */
 539     s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
 540     s->irq = irq;
 541
 542     vmstate_register(base, &vmstate_pit, pit);
 543     qemu_register_reset(pit_reset, pit);
 544     register_ioport_write(base, 4, 1, pit_ioport_write, pit);
 545     register_ioport_read(base, 3, 1, pit_ioport_read, pit);
 546
 547     pit_reset(pit);
 548
 549     return pit;
 550 }