hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "pc.h"
  21 #include "pci.h"
  22 #include "msix.h"
  23 #include "qemu-timer.h"
  24 #include "host-utils.h"
  25 #include "kvm.h"
  26
  27 #include "qemu-kvm.h"
  28
  29 //#define DEBUG_APIC
  30
  31 /* APIC Local Vector Table */
  32 #define APIC_LVT_TIMER   0
  33 #define APIC_LVT_THERMAL 1
  34 #define APIC_LVT_PERFORM 2
  35 #define APIC_LVT_LINT0   3
  36 #define APIC_LVT_LINT1   4
  37 #define APIC_LVT_ERROR   5
  38 #define APIC_LVT_NB      6
  39
  40 /* APIC delivery modes */
  41 #define APIC_DM_FIXED   0
  42 #define APIC_DM_LOWPRI  1
  43 #define APIC_DM_SMI     2
  44 #define APIC_DM_NMI     4
  45 #define APIC_DM_INIT    5
  46 #define APIC_DM_SIPI    6
  47 #define APIC_DM_EXTINT  7
  48
  49 /* APIC destination mode */
  50 #define APIC_DESTMODE_FLAT      0xf
  51 #define APIC_DESTMODE_CLUSTER   1
  52
  53 #define APIC_TRIGGER_EDGE  0
  54 #define APIC_TRIGGER_LEVEL 1
  55
  56 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  57 #define APIC_LVT_MASKED                 (1<<16)
  58 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  59 #define APIC_LVT_REMOTE_IRR             (1<<14)
  60 #define APIC_INPUT_POLARITY             (1<<13)
  61 #define APIC_SEND_PENDING               (1<<12)
  62
  63 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  64
  65 #define APIC_SV_ENABLE (1 << 8)
  66
  67 #define MAX_APICS 255
  68 #define MAX_APIC_WORDS 8
  69
  70 /* Intel APIC constants: from include/asm/msidef.h */
  71 #define MSI_DATA_VECTOR_SHIFT           0
  72 #define MSI_DATA_VECTOR_MASK            0x000000ff
  73 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  74 #define MSI_DATA_TRIGGER_SHIFT          15
  75 #define MSI_DATA_LEVEL_SHIFT            14
  76 #define MSI_ADDR_DEST_MODE_SHIFT        2
  77 #define MSI_ADDR_DEST_ID_SHIFT          12
  78 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  79
  80 #define MSI_ADDR_BASE                   0xfee00000
  81 #define MSI_ADDR_SIZE                   0x100000
  82
  83 typedef struct APICState {
  84     CPUState *cpu_env;
  85     uint32_t apicbase;
  86     uint8_t id;
  87     uint8_t arb_id;
  88     uint8_t tpr;
  89     uint32_t spurious_vec;
  90     uint8_t log_dest;
  91     uint8_t dest_mode;
  92     uint32_t isr[8];  /* in service register */
  93     uint32_t tmr[8];  /* trigger mode register */
  94     uint32_t irr[8]; /* interrupt request register */
  95     uint32_t lvt[APIC_LVT_NB];
  96     uint32_t esr; /* error register */
  97     uint32_t icr[2];
  98
  99     uint32_t divide_conf;
 100     int count_shift;
 101     uint32_t initial_count;
 102     int64_t initial_count_load_time, next_time;
 103     uint32_t idx;
 104     QEMUTimer *timer;
 105     int sipi_vector;
 106     int wait_for_sipi;
 107 } APICState;
 108
 109 static int apic_io_memory;
 110 static APICState *local_apics[MAX_APICS + 1];
 111 static int last_apic_idx = 0;
 112 static int apic_irq_delivered;
 113
 114
 115 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 116 static void apic_update_irq(APICState *s);
 117 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 118                                       uint8_t dest, uint8_t dest_mode);
 119
 120 /* Find first bit starting from msb */
 121 static int fls_bit(uint32_t value)
 122 {
 123     return 31 - clz32(value);
 124 }
 125
 126 /* Find first bit starting from lsb */
 127 static int ffs_bit(uint32_t value)
 128 {
 129     return ctz32(value);
 130 }
 131
 132 static inline void set_bit(uint32_t *tab, int index)
 133 {
 134     int i, mask;
 135     i = index >> 5;
 136     mask = 1 << (index & 0x1f);
 137     tab[i] |= mask;
 138 }
 139
 140 static inline void reset_bit(uint32_t *tab, int index)
 141 {
 142     int i, mask;
 143     i = index >> 5;
 144     mask = 1 << (index & 0x1f);
 145     tab[i] &= ~mask;
 146 }
 147
 148 static inline int get_bit(uint32_t *tab, int index)
 149 {
 150     int i, mask;
 151     i = index >> 5;
 152     mask = 1 << (index & 0x1f);
 153     return !!(tab[i] & mask);
 154 }
 155
 156 static void apic_local_deliver(CPUState *env, int vector)
 157 {
 158     APICState *s = env->apic_state;
 159     uint32_t lvt = s->lvt[vector];
 160     int trigger_mode;
 161
 162     if (lvt & APIC_LVT_MASKED)
 163         return;
 164
 165     switch ((lvt >> 8) & 7) {
 166     case APIC_DM_SMI:
 167         cpu_interrupt(env, CPU_INTERRUPT_SMI);
 168         break;
 169
 170     case APIC_DM_NMI:
 171         cpu_interrupt(env, CPU_INTERRUPT_NMI);
 172         break;
 173
 174     case APIC_DM_EXTINT:
 175         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 176         break;
 177
 178     case APIC_DM_FIXED:
 179         trigger_mode = APIC_TRIGGER_EDGE;
 180         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 181             (lvt & APIC_LVT_LEVEL_TRIGGER))
 182             trigger_mode = APIC_TRIGGER_LEVEL;
 183         apic_set_irq(s, lvt & 0xff, trigger_mode);
 184     }
 185 }
 186
 187 void apic_deliver_pic_intr(CPUState *env, int level)
 188 {
 189     if (level)
 190         apic_local_deliver(env, APIC_LVT_LINT0);
 191     else {
 192         APICState *s = env->apic_state;
 193         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 194
 195         switch ((lvt >> 8) & 7) {
 196         case APIC_DM_FIXED:
 197             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 198                 break;
 199             reset_bit(s->irr, lvt & 0xff);
 200             /* fall through */
 201         case APIC_DM_EXTINT:
 202             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 203             break;
 204         }
 205     }
 206 }
 207
 208 #define foreach_apic(apic, deliver_bitmask, code) \
 209 {\
 210     int __i, __j, __mask;\
 211     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 212         __mask = deliver_bitmask[__i];\
 213         if (__mask) {\
 214             for(__j = 0; __j < 32; __j++) {\
 215                 if (__mask & (1 << __j)) {\
 216                     apic = local_apics[__i * 32 + __j];\
 217                     if (apic) {\
 218                         code;\
 219                     }\
 220                 }\
 221             }\
 222         }\
 223     }\
 224 }
 225
 226 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 227                              uint8_t delivery_mode,
 228                              uint8_t vector_num, uint8_t polarity,
 229                              uint8_t trigger_mode)
 230 {
 231     APICState *apic_iter;
 232
 233     switch (delivery_mode) {
 234         case APIC_DM_LOWPRI:
 235             /* XXX: search for focus processor, arbitration */
 236             {
 237                 int i, d;
 238                 d = -1;
 239                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 240                     if (deliver_bitmask[i]) {
 241                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 242                         break;
 243                     }
 244                 }
 245                 if (d >= 0) {
 246                     apic_iter = local_apics[d];
 247                     if (apic_iter) {
 248                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 249                     }
 250                 }
 251             }
 252             return;
 253
 254         case APIC_DM_FIXED:
 255             break;
 256
 257         case APIC_DM_SMI:
 258             foreach_apic(apic_iter, deliver_bitmask,
 259                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 260             return;
 261
 262         case APIC_DM_NMI:
 263             foreach_apic(apic_iter, deliver_bitmask,
 264                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 265             return;
 266
 267         case APIC_DM_INIT:
 268             /* normal INIT IPI sent to processors */
 269             foreach_apic(apic_iter, deliver_bitmask,
 270                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 271             return;
 272
 273         case APIC_DM_EXTINT:
 274             /* handled in I/O APIC code */
 275             break;
 276
 277         default:
 278             return;
 279     }
 280
 281     foreach_apic(apic_iter, deliver_bitmask,
 282                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 283 }
 284
 285 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 286                       uint8_t delivery_mode, uint8_t vector_num,
 287                       uint8_t polarity, uint8_t trigger_mode)
 288 {
 289     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 290
 291     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 292     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 293                      trigger_mode);
 294 }
 295
 296 void cpu_set_apic_base(CPUState *env, uint64_t val)
 297 {
 298     APICState *s = env->apic_state;
 299 #ifdef DEBUG_APIC
 300     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
 301 #endif
 302     if (!s)
 303         return;
 304     if (kvm_enabled() && kvm_irqchip_in_kernel())
 305         s->apicbase = val;
 306     else
 307         s->apicbase = (val & 0xfffff000) |
 308             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 309     /* if disabled, cannot be enabled again */
 310     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 311         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 312         env->cpuid_features &= ~CPUID_APIC;
 313         s->spurious_vec &= ~APIC_SV_ENABLE;
 314     }
 315 }
 316
 317 uint64_t cpu_get_apic_base(CPUState *env)
 318 {
 319     APICState *s = env->apic_state;
 320 #ifdef DEBUG_APIC
 321     printf("cpu_get_apic_base: %016" PRIx64 "\n",
 322            s ? (uint64_t)s->apicbase: 0);
 323 #endif
 324     return s ? s->apicbase : 0;
 325 }
 326
 327 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 328 {
 329     APICState *s = env->apic_state;
 330     if (!s)
 331         return;
 332     s->tpr = (val & 0x0f) << 4;
 333     apic_update_irq(s);
 334 }
 335
 336 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 337 {
 338     APICState *s = env->apic_state;
 339     return s ? s->tpr >> 4 : 0;
 340 }
 341
 342 /* return -1 if no bit is set */
 343 static int get_highest_priority_int(uint32_t *tab)
 344 {
 345     int i;
 346     for(i = 7; i >= 0; i--) {
 347         if (tab[i] != 0) {
 348             return i * 32 + fls_bit(tab[i]);
 349         }
 350     }
 351     return -1;
 352 }
 353
 354 static int apic_get_ppr(APICState *s)
 355 {
 356     int tpr, isrv, ppr;
 357
 358     tpr = (s->tpr >> 4);
 359     isrv = get_highest_priority_int(s->isr);
 360     if (isrv < 0)
 361         isrv = 0;
 362     isrv >>= 4;
 363     if (tpr >= isrv)
 364         ppr = s->tpr;
 365     else
 366         ppr = isrv << 4;
 367     return ppr;
 368 }
 369
 370 static int apic_get_arb_pri(APICState *s)
 371 {
 372     /* XXX: arbitration */
 373     return 0;
 374 }
 375
 376 /* signal the CPU if an irq is pending */
 377 static void apic_update_irq(APICState *s)
 378 {
 379     int irrv, ppr;
 380     if (!(s->spurious_vec & APIC_SV_ENABLE))
 381         return;
 382     irrv = get_highest_priority_int(s->irr);
 383     if (irrv < 0)
 384         return;
 385     ppr = apic_get_ppr(s);
 386     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 387         return;
 388     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 389 }
 390
 391 void apic_reset_irq_delivered(void)
 392 {
 393     apic_irq_delivered = 0;
 394 }
 395
 396 int apic_get_irq_delivered(void)
 397 {
 398     return apic_irq_delivered;
 399 }
 400
 401 void apic_set_irq_delivered(void)
 402 {
 403     apic_irq_delivered = 1;
 404 }
 405
 406 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 407 {
 408     apic_irq_delivered += !get_bit(s->irr, vector_num);
 409
 410     set_bit(s->irr, vector_num);
 411     if (trigger_mode)
 412         set_bit(s->tmr, vector_num);
 413     else
 414         reset_bit(s->tmr, vector_num);
 415     apic_update_irq(s);
 416 }
 417
 418 static void apic_eoi(APICState *s)
 419 {
 420     int isrv;
 421     isrv = get_highest_priority_int(s->isr);
 422     if (isrv < 0)
 423         return;
 424     reset_bit(s->isr, isrv);
 425     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 426             set the remote IRR bit for level triggered interrupts. */
 427     apic_update_irq(s);
 428 }
 429
 430 static int apic_find_dest(uint8_t dest)
 431 {
 432     APICState *apic = local_apics[dest];
 433     int i;
 434
 435     if (apic && apic->id == dest)
 436         return dest;  /* shortcut in case apic->id == apic->idx */
 437
 438     for (i = 0; i < MAX_APICS; i++) {
 439         apic = local_apics[i];
 440         if (apic && apic->id == dest)
 441             return i;
 442     }
 443
 444     return -1;
 445 }
 446
 447 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 448                                       uint8_t dest, uint8_t dest_mode)
 449 {
 450     APICState *apic_iter;
 451     int i;
 452
 453     if (dest_mode == 0) {
 454         if (dest == 0xff) {
 455             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 456         } else {
 457             int idx = apic_find_dest(dest);
 458             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 459             if (idx >= 0)
 460                 set_bit(deliver_bitmask, idx);
 461         }
 462     } else {
 463         /* XXX: cluster mode */
 464         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 465         for(i = 0; i < MAX_APICS; i++) {
 466             apic_iter = local_apics[i];
 467             if (apic_iter) {
 468                 if (apic_iter->dest_mode == 0xf) {
 469                     if (dest & apic_iter->log_dest)
 470                         set_bit(deliver_bitmask, i);
 471                 } else if (apic_iter->dest_mode == 0x0) {
 472                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 473                         (dest & apic_iter->log_dest & 0x0f)) {
 474                         set_bit(deliver_bitmask, i);
 475                     }
 476                 }
 477             }
 478         }
 479     }
 480 }
 481
 482
 483 void apic_init_reset(CPUState *env)
 484 {
 485     APICState *s = env->apic_state;
 486     int i;
 487
 488     if (!s)
 489         return;
 490
 491     cpu_synchronize_state(env);
 492     s->tpr = 0;
 493     s->spurious_vec = 0xff;
 494     s->log_dest = 0;
 495     s->dest_mode = 0xf;
 496     memset(s->isr, 0, sizeof(s->isr));
 497     memset(s->tmr, 0, sizeof(s->tmr));
 498     memset(s->irr, 0, sizeof(s->irr));
 499     for(i = 0; i < APIC_LVT_NB; i++)
 500         s->lvt[i] = 1 << 16; /* mask LVT */
 501     s->esr = 0;
 502     memset(s->icr, 0, sizeof(s->icr));
 503     s->divide_conf = 0;
 504     s->count_shift = 0;
 505     s->initial_count = 0;
 506     s->initial_count_load_time = 0;
 507     s->next_time = 0;
 508     s->wait_for_sipi = 1;
 509
 510     env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP);
 511 #ifdef KVM_CAP_MP_STATE
 512     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 513         env->mp_state
 514             = env->halted ? KVM_MP_STATE_UNINITIALIZED : KVM_MP_STATE_RUNNABLE;
 515         kvm_load_mpstate(env);
 516     }
 517 #endif
 518 }
 519
 520 static void apic_startup(APICState *s, int vector_num)
 521 {
 522     s->sipi_vector = vector_num;
 523     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 524 }
 525
 526 void apic_sipi(CPUState *env)
 527 {
 528     APICState *s = env->apic_state;
 529
 530     cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI);
 531
 532     if (!s->wait_for_sipi)
 533         return;
 534
 535     env->eip = 0;
 536     cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12,
 537                            env->segs[R_CS].limit, env->segs[R_CS].flags);
 538     env->halted = 0;
 539     s->wait_for_sipi = 0;
 540 }
 541
 542 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 543                          uint8_t delivery_mode, uint8_t vector_num,
 544                          uint8_t polarity, uint8_t trigger_mode)
 545 {
 546     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 547     int dest_shorthand = (s->icr[0] >> 18) & 3;
 548     APICState *apic_iter;
 549
 550     switch (dest_shorthand) {
 551     case 0:
 552         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 553         break;
 554     case 1:
 555         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 556         set_bit(deliver_bitmask, s->idx);
 557         break;
 558     case 2:
 559         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 560         break;
 561     case 3:
 562         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 563         reset_bit(deliver_bitmask, s->idx);
 564         break;
 565     }
 566
 567     switch (delivery_mode) {
 568         case APIC_DM_INIT:
 569             {
 570                 int trig_mode = (s->icr[0] >> 15) & 1;
 571                 int level = (s->icr[0] >> 14) & 1;
 572                 if (level == 0 && trig_mode == 1) {
 573                     foreach_apic(apic_iter, deliver_bitmask,
 574                                  apic_iter->arb_id = apic_iter->id );
 575                     return;
 576                 }
 577             }
 578             break;
 579
 580         case APIC_DM_SIPI:
 581             foreach_apic(apic_iter, deliver_bitmask,
 582                          apic_startup(apic_iter, vector_num) );
 583             return;
 584     }
 585
 586     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 587                      trigger_mode);
 588 }
 589
 590 int apic_get_interrupt(CPUState *env)
 591 {
 592     APICState *s = env->apic_state;
 593     int intno;
 594
 595     /* if the APIC is installed or enabled, we let the 8259 handle the
 596        IRQs */
 597     if (!s)
 598         return -1;
 599     if (!(s->spurious_vec & APIC_SV_ENABLE))
 600         return -1;
 601
 602     /* XXX: spurious IRQ handling */
 603     intno = get_highest_priority_int(s->irr);
 604     if (intno < 0)
 605         return -1;
 606     if (s->tpr && intno <= s->tpr)
 607         return s->spurious_vec & 0xff;
 608     reset_bit(s->irr, intno);
 609     set_bit(s->isr, intno);
 610     apic_update_irq(s);
 611     return intno;
 612 }
 613
 614 int apic_accept_pic_intr(CPUState *env)
 615 {
 616     APICState *s = env->apic_state;
 617     uint32_t lvt0;
 618
 619     if (!s)
 620         return -1;
 621
 622     lvt0 = s->lvt[APIC_LVT_LINT0];
 623
 624     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 625         (lvt0 & APIC_LVT_MASKED) == 0)
 626         return 1;
 627
 628     return 0;
 629 }
 630
 631 static uint32_t apic_get_current_count(APICState *s)
 632 {
 633     int64_t d;
 634     uint32_t val;
 635     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 636         s->count_shift;
 637     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 638         /* periodic */
 639         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 640     } else {
 641         if (d >= s->initial_count)
 642             val = 0;
 643         else
 644             val = s->initial_count - d;
 645     }
 646     return val;
 647 }
 648
 649 static void apic_timer_update(APICState *s, int64_t current_time)
 650 {
 651     int64_t next_time, d;
 652
 653     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 654         d = (current_time - s->initial_count_load_time) >>
 655             s->count_shift;
 656         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 657             if (!s->initial_count)
 658                 goto no_timer;
 659             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 660         } else {
 661             if (d >= s->initial_count)
 662                 goto no_timer;
 663             d = (uint64_t)s->initial_count + 1;
 664         }
 665         next_time = s->initial_count_load_time + (d << s->count_shift);
 666         qemu_mod_timer(s->timer, next_time);
 667         s->next_time = next_time;
 668     } else {
 669     no_timer:
 670         qemu_del_timer(s->timer);
 671     }
 672 }
 673
 674 static void apic_timer(void *opaque)
 675 {
 676     APICState *s = opaque;
 677
 678     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
 679     apic_timer_update(s, s->next_time);
 680 }
 681
 682 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 683 {
 684     return 0;
 685 }
 686
 687 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 688 {
 689     return 0;
 690 }
 691
 692 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 693 {
 694 }
 695
 696 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 697 {
 698 }
 699
 700 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 701 {
 702     CPUState *env;
 703     APICState *s;
 704     uint32_t val;
 705     int index;
 706
 707     env = cpu_single_env;
 708     if (!env)
 709         return 0;
 710     s = env->apic_state;
 711
 712     index = (addr >> 4) & 0xff;
 713     switch(index) {
 714     case 0x02: /* id */
 715         val = s->id << 24;
 716         break;
 717     case 0x03: /* version */
 718         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 719         break;
 720     case 0x08:
 721         val = s->tpr;
 722         break;
 723     case 0x09:
 724         val = apic_get_arb_pri(s);
 725         break;
 726     case 0x0a:
 727         /* ppr */
 728         val = apic_get_ppr(s);
 729         break;
 730     case 0x0b:
 731         val = 0;
 732         break;
 733     case 0x0d:
 734         val = s->log_dest << 24;
 735         break;
 736     case 0x0e:
 737         val = s->dest_mode << 28;
 738         break;
 739     case 0x0f:
 740         val = s->spurious_vec;
 741         break;
 742     case 0x10 ... 0x17:
 743         val = s->isr[index & 7];
 744         break;
 745     case 0x18 ... 0x1f:
 746         val = s->tmr[index & 7];
 747         break;
 748     case 0x20 ... 0x27:
 749         val = s->irr[index & 7];
 750         break;
 751     case 0x28:
 752         val = s->esr;
 753         break;
 754     case 0x30:
 755     case 0x31:
 756         val = s->icr[index & 1];
 757         break;
 758     case 0x32 ... 0x37:
 759         val = s->lvt[index - 0x32];
 760         break;
 761     case 0x38:
 762         val = s->initial_count;
 763         break;
 764     case 0x39:
 765         val = apic_get_current_count(s);
 766         break;
 767     case 0x3e:
 768         val = s->divide_conf;
 769         break;
 770     default:
 771         s->esr |= ESR_ILLEGAL_ADDRESS;
 772         val = 0;
 773         break;
 774     }
 775 #ifdef DEBUG_APIC
 776     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
 777 #endif
 778     return val;
 779 }
 780
 781 static void apic_send_msi(target_phys_addr_t addr, uint32 data)
 782 {
 783     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 784     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 785     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 786     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 787     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 788     /* XXX: Ignore redirection hint. */
 789     apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
 790 }
 791
 792 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 793 {
 794     CPUState *env;
 795     APICState *s;
 796     int index = (addr >> 4) & 0xff;
 797     if (addr > 0xfff || !index) {
 798         /* MSI and MMIO APIC are at the same memory location,
 799          * but actually not on the global bus: MSI is on PCI bus
 800          * APIC is connected directly to the CPU.
 801          * Mapping them on the global bus happens to work because
 802          * MSI registers are reserved in APIC MMIO and vice versa. */
 803         apic_send_msi(addr, val);
 804         return;
 805     }
 806
 807     env = cpu_single_env;
 808     if (!env)
 809         return;
 810     s = env->apic_state;
 811
 812 #ifdef DEBUG_APIC
 813     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 814 #endif
 815
 816     switch(index) {
 817     case 0x02:
 818         s->id = (val >> 24);
 819         break;
 820     case 0x03:
 821         break;
 822     case 0x08:
 823         s->tpr = val;
 824         apic_update_irq(s);
 825         break;
 826     case 0x09:
 827     case 0x0a:
 828         break;
 829     case 0x0b: /* EOI */
 830         apic_eoi(s);
 831         break;
 832     case 0x0d:
 833         s->log_dest = val >> 24;
 834         break;
 835     case 0x0e:
 836         s->dest_mode = val >> 28;
 837         break;
 838     case 0x0f:
 839         s->spurious_vec = val & 0x1ff;
 840         apic_update_irq(s);
 841         break;
 842     case 0x10 ... 0x17:
 843     case 0x18 ... 0x1f:
 844     case 0x20 ... 0x27:
 845     case 0x28:
 846         break;
 847     case 0x30:
 848         s->icr[0] = val;
 849         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 850                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 851                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 852         break;
 853     case 0x31:
 854         s->icr[1] = val;
 855         break;
 856     case 0x32 ... 0x37:
 857         {
 858             int n = index - 0x32;
 859             s->lvt[n] = val;
 860             if (n == APIC_LVT_TIMER)
 861                 apic_timer_update(s, qemu_get_clock(vm_clock));
 862         }
 863         break;
 864     case 0x38:
 865         s->initial_count = val;
 866         s->initial_count_load_time = qemu_get_clock(vm_clock);
 867         apic_timer_update(s, s->initial_count_load_time);
 868         break;
 869     case 0x39:
 870         break;
 871     case 0x3e:
 872         {
 873             int v;
 874             s->divide_conf = val & 0xb;
 875             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 876             s->count_shift = (v + 1) & 7;
 877         }
 878         break;
 879     default:
 880         s->esr |= ESR_ILLEGAL_ADDRESS;
 881         break;
 882     }
 883 }
 884
 885 #ifdef KVM_CAP_IRQCHIP
 886
 887 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 888 {
 889     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 890 }
 891
 892 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 893                                  int reg_id, uint32_t val)
 894 {
 895     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 896 }
 897
 898 static void kvm_kernel_lapic_save_to_user(APICState *s)
 899 {
 900     struct kvm_lapic_state apic;
 901     struct kvm_lapic_state *kapic = &apic;
 902     int i, v;
 903
 904     kvm_get_lapic(s->cpu_env, kapic);
 905
 906     s->id = kapic_reg(kapic, 0x2) >> 24;
 907     s->tpr = kapic_reg(kapic, 0x8);
 908     s->arb_id = kapic_reg(kapic, 0x9);
 909     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 910     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 911     s->spurious_vec = kapic_reg(kapic, 0xf);
 912     for (i = 0; i < 8; i++) {
 913         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 914         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 915         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 916     }
 917     s->esr = kapic_reg(kapic, 0x28);
 918     s->icr[0] = kapic_reg(kapic, 0x30);
 919     s->icr[1] = kapic_reg(kapic, 0x31);
 920     for (i = 0; i < APIC_LVT_NB; i++)
 921         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 922     s->initial_count = kapic_reg(kapic, 0x38);
 923     s->divide_conf = kapic_reg(kapic, 0x3e);
 924
 925     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 926     s->count_shift = (v + 1) & 7;
 927
 928     s->initial_count_load_time = qemu_get_clock(vm_clock);
 929     apic_timer_update(s, s->initial_count_load_time);
 930 }
 931
 932 static void kvm_kernel_lapic_load_from_user(APICState *s)
 933 {
 934     struct kvm_lapic_state apic;
 935     struct kvm_lapic_state *klapic = &apic;
 936     int i;
 937
 938     memset(klapic, 0, sizeof apic);
 939     kapic_set_reg(klapic, 0x2, s->id << 24);
 940     kapic_set_reg(klapic, 0x8, s->tpr);
 941     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 942     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 943     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 944     for (i = 0; i < 8; i++) {
 945         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 946         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 947         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 948     }
 949     kapic_set_reg(klapic, 0x28, s->esr);
 950     kapic_set_reg(klapic, 0x30, s->icr[0]);
 951     kapic_set_reg(klapic, 0x31, s->icr[1]);
 952     for (i = 0; i < APIC_LVT_NB; i++)
 953         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 954     kapic_set_reg(klapic, 0x38, s->initial_count);
 955     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 956
 957     kvm_set_lapic(s->cpu_env, klapic);
 958 }
 959
 960 #endif
 961
 962 void qemu_kvm_load_lapic(CPUState *env)
 963 {
 964 #ifdef KVM_CAP_IRQCHIP
 965     if (kvm_enabled() && kvm_vcpu_inited(env) && kvm_irqchip_in_kernel()) {
 966         kvm_kernel_lapic_load_from_user(env->apic_state);
 967     }
 968 #endif
 969 }
 970
 971 static void apic_pre_save(void *opaque)
 972 {
 973 #ifdef KVM_CAP_IRQCHIP
 974     APICState *s = (void *)opaque;
 975
 976     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 977         kvm_kernel_lapic_save_to_user(s);
 978     }
 979 #endif
 980 }
 981
 982 static int apic_post_load(void *opaque, int version_id)
 983 {
 984 #ifdef KVM_CAP_IRQCHIP
 985     APICState *s = opaque;
 986
 987     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 988         kvm_kernel_lapic_load_from_user(s);
 989     }
 990 #endif
 991     return 0;
 992 }
 993
 994 /* This function is only used for old state version 1 and 2 */
 995 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 996 {
 997     APICState *s = opaque;
 998     int i;
 999
1000     if (version_id > 2)
1001         return -EINVAL;
1002
1003     /* XXX: what if the base changes? (registered memory regions) */
1004     qemu_get_be32s(f, &s->apicbase);
1005     qemu_get_8s(f, &s->id);
1006     qemu_get_8s(f, &s->arb_id);
1007     qemu_get_8s(f, &s->tpr);
1008     qemu_get_be32s(f, &s->spurious_vec);
1009     qemu_get_8s(f, &s->log_dest);
1010     qemu_get_8s(f, &s->dest_mode);
1011     for (i = 0; i < 8; i++) {
1012         qemu_get_be32s(f, &s->isr[i]);
1013         qemu_get_be32s(f, &s->tmr[i]);
1014         qemu_get_be32s(f, &s->irr[i]);
1015     }
1016     for (i = 0; i < APIC_LVT_NB; i++) {
1017         qemu_get_be32s(f, &s->lvt[i]);
1018     }
1019     qemu_get_be32s(f, &s->esr);
1020     qemu_get_be32s(f, &s->icr[0]);
1021     qemu_get_be32s(f, &s->icr[1]);
1022     qemu_get_be32s(f, &s->divide_conf);
1023     s->count_shift=qemu_get_be32(f);
1024     qemu_get_be32s(f, &s->initial_count);
1025     s->initial_count_load_time=qemu_get_be64(f);
1026     s->next_time=qemu_get_be64(f);
1027
1028     if (version_id >= 2)
1029         qemu_get_timer(f, s->timer);
1030
1031     qemu_kvm_load_lapic(s->cpu_env);
1032
1033     return 0;
1034 }
1035
1036 static const VMStateDescription vmstate_apic = {
1037     .name = "apic",
1038     .version_id = 3,
1039     .minimum_version_id = 3,
1040     .minimum_version_id_old = 1,
1041     .load_state_old = apic_load_old,
1042     .fields      = (VMStateField []) {
1043         VMSTATE_UINT32(apicbase, APICState),
1044         VMSTATE_UINT8(id, APICState),
1045         VMSTATE_UINT8(arb_id, APICState),
1046         VMSTATE_UINT8(tpr, APICState),
1047         VMSTATE_UINT32(spurious_vec, APICState),
1048         VMSTATE_UINT8(log_dest, APICState),
1049         VMSTATE_UINT8(dest_mode, APICState),
1050         VMSTATE_UINT32_ARRAY(isr, APICState, 8),
1051         VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
1052         VMSTATE_UINT32_ARRAY(irr, APICState, 8),
1053         VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
1054         VMSTATE_UINT32(esr, APICState),
1055         VMSTATE_UINT32_ARRAY(icr, APICState, 2),
1056         VMSTATE_UINT32(divide_conf, APICState),
1057         VMSTATE_INT32(count_shift, APICState),
1058         VMSTATE_UINT32(initial_count, APICState),
1059         VMSTATE_INT64(initial_count_load_time, APICState),
1060         VMSTATE_INT64(next_time, APICState),
1061         VMSTATE_TIMER(timer, APICState),
1062         VMSTATE_END_OF_LIST()
1063     },
1064     .pre_save = apic_pre_save,
1065     .post_load = apic_post_load,
1066 };
1067
1068 static void apic_reset(void *opaque)
1069 {
1070     APICState *s = opaque;
1071     int bsp;
1072
1073     cpu_synchronize_state(s->cpu_env);
1074
1075     bsp = cpu_is_bsp(s->cpu_env);
1076     s->apicbase = 0xfee00000 |
1077         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
1078
1079     cpu_reset(s->cpu_env);
1080     apic_init_reset(s->cpu_env);
1081
1082     if (bsp) {
1083         /*
1084          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1085          * time typically by BIOS, so PIC interrupt can be delivered to the
1086          * processor when local APIC is enabled.
1087          */
1088         s->lvt[APIC_LVT_LINT0] = 0x700;
1089     }
1090     qemu_kvm_load_lapic(s->cpu_env);
1091 }
1092
1093 static CPUReadMemoryFunc * const apic_mem_read[3] = {
1094     apic_mem_readb,
1095     apic_mem_readw,
1096     apic_mem_readl,
1097 };
1098
1099 static CPUWriteMemoryFunc * const apic_mem_write[3] = {
1100     apic_mem_writeb,
1101     apic_mem_writew,
1102     apic_mem_writel,
1103 };
1104
1105 int apic_init(CPUState *env)
1106 {
1107     APICState *s;
1108
1109     if (last_apic_idx >= MAX_APICS)
1110         return -1;
1111     s = qemu_mallocz(sizeof(APICState));
1112     env->apic_state = s;
1113     s->idx = last_apic_idx++;
1114     s->id = env->cpuid_apic_id;
1115     s->cpu_env = env;
1116
1117     apic_reset(s);
1118     msix_supported = 1;
1119
1120     /* XXX: mapping more APICs at the same memory location */
1121     if (apic_io_memory == 0) {
1122         /* NOTE: the APIC is directly connected to the CPU - it is not
1123            on the global memory bus. */
1124         apic_io_memory = cpu_register_io_memory(apic_mem_read,
1125                                                 apic_mem_write, NULL);
1126         /* XXX: what if the base changes? */
1127         cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE,
1128                                      apic_io_memory);
1129     }
1130     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1131
1132     vmstate_register(s->idx, &vmstate_apic, s);
1133     qemu_register_reset(apic_reset, s);
1134
1135     local_apics[s->idx] = s;
1136     return 0;
1137 }