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Coalesced MMIO support (core)
[qemu-kvm/markmc.git] / hw / ne2000.c
blobddc59b53286e7431ff8393ef6cd613b23b0dbcce
1 /*
2 * QEMU NE2000 emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pc.h"
27 #include "net.h"
28
29 /* debug NE2000 card */
30 //#define DEBUG_NE2000
31
32 #define MAX_ETH_FRAME_SIZE 1514
33
34 #define E8390_CMD 0x00 /* The command register (for all pages) */
35 /* Page 0 register offsets. */
36 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
37 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
38 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
39 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
40 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
41 #define EN0_TSR 0x04 /* Transmit status reg RD */
42 #define EN0_TPSR 0x04 /* Transmit starting page WR */
43 #define EN0_NCR 0x05 /* Number of collision reg RD */
44 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
45 #define EN0_FIFO 0x06 /* FIFO RD */
46 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
47 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
48 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
49 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
50 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
51 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
52 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
53 #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
54 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
55 #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
56 #define EN0_RSR 0x0c /* rx status reg RD */
57 #define EN0_RXCR 0x0c /* RX configuration reg WR */
58 #define EN0_TXCR 0x0d /* TX configuration reg WR */
59 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
60 #define EN0_DCFG 0x0e /* Data configuration reg WR */
61 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
62 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
63 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
64
65 #define EN1_PHYS 0x11
66 #define EN1_CURPAG 0x17
67 #define EN1_MULT 0x18
68
69 #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
70 #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
71
72 #define EN3_CONFIG0 0x33
73 #define EN3_CONFIG1 0x34
74 #define EN3_CONFIG2 0x35
75 #define EN3_CONFIG3 0x36
76
77 /* Register accessed at EN_CMD, the 8390 base addr. */
78 #define E8390_STOP 0x01 /* Stop and reset the chip */
79 #define E8390_START 0x02 /* Start the chip, clear reset */
80 #define E8390_TRANS 0x04 /* Transmit a frame */
81 #define E8390_RREAD 0x08 /* Remote read */
82 #define E8390_RWRITE 0x10 /* Remote write */
83 #define E8390_NODMA 0x20 /* Remote DMA */
84 #define E8390_PAGE0 0x00 /* Select page chip registers */
85 #define E8390_PAGE1 0x40 /* using the two high-order bits */
86 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
87
88 /* Bits in EN0_ISR - Interrupt status register */
89 #define ENISR_RX 0x01 /* Receiver, no error */
90 #define ENISR_TX 0x02 /* Transmitter, no error */
91 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
92 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
93 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
94 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
95 #define ENISR_RDC 0x40 /* remote dma complete */
96 #define ENISR_RESET 0x80 /* Reset completed */
97 #define ENISR_ALL 0x3f /* Interrupts we will enable */
98
99 /* Bits in received packet status byte and EN0_RSR*/
100 #define ENRSR_RXOK 0x01 /* Received a good packet */
101 #define ENRSR_CRC 0x02 /* CRC error */
102 #define ENRSR_FAE 0x04 /* frame alignment error */
103 #define ENRSR_FO 0x08 /* FIFO overrun */
104 #define ENRSR_MPA 0x10 /* missed pkt */
105 #define ENRSR_PHY 0x20 /* physical/multicast address */
106 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
107 #define ENRSR_DEF 0x80 /* deferring */
108
109 /* Transmitted packet status, EN0_TSR. */
110 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
111 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
112 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
113 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
114 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
115 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
116 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
117 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
118
119 #define NE2000_PMEM_SIZE (32*1024)
120 #define NE2000_PMEM_START (16*1024)
121 #define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
122 #define NE2000_MEM_SIZE NE2000_PMEM_END
123
124 typedef struct NE2000State {
125 uint8_t cmd;
126 uint32_t start;
127 uint32_t stop;
128 uint8_t boundary;
129 uint8_t tsr;
130 uint8_t tpsr;
131 uint16_t tcnt;
132 uint16_t rcnt;
133 uint32_t rsar;
134 uint8_t rsr;
135 uint8_t rxcr;
136 uint8_t isr;
137 uint8_t dcfg;
138 uint8_t imr;
139 uint8_t phys[6]; /* mac address */
140 uint8_t curpag;
141 uint8_t mult[8]; /* multicast mask array */
142 qemu_irq irq;
143 PCIDevice *pci_dev;
144 VLANClientState *vc;
145 uint8_t macaddr[6];
146 uint8_t mem[NE2000_MEM_SIZE];
147 } NE2000State;
148
149 static int ne2000_id;
150
151 static void ne2000_reset(NE2000State *s)
152 {
153 int i;
154
155 s->isr = ENISR_RESET;
156 memcpy(s->mem, s->macaddr, 6);
157 s->mem[14] = 0x57;
158 s->mem[15] = 0x57;
159
160 /* duplicate prom data */
161 for(i = 15;i >= 0; i--) {
162 s->mem[2 * i] = s->mem[i];
163 s->mem[2 * i + 1] = s->mem[i];
164 }
165 }
166
167 static void ne2000_update_irq(NE2000State *s)
168 {
169 int isr;
170 isr = (s->isr & s->imr) & 0x7f;
171 #if defined(DEBUG_NE2000)
172 printf("NE2000: Set IRQ to %d (%02x %02x)\n",
173 isr ? 1 : 0, s->isr, s->imr);
174 #endif
175 qemu_set_irq(s->irq, (isr != 0));
176 }
177
178 #define POLYNOMIAL 0x04c11db6
179
180 /* From FreeBSD */
181 /* XXX: optimize */
182 static int compute_mcast_idx(const uint8_t *ep)
183 {
184 uint32_t crc;
185 int carry, i, j;
186 uint8_t b;
187
188 crc = 0xffffffff;
189 for (i = 0; i < 6; i++) {
190 b = *ep++;
191 for (j = 0; j < 8; j++) {
192 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
193 crc <<= 1;
194 b >>= 1;
195 if (carry)
196 crc = ((crc ^ POLYNOMIAL) | carry);
197 }
198 }
199 return (crc >> 26);
200 }
201
202 static int ne2000_buffer_full(NE2000State *s)
203 {
204 int avail, index, boundary;
205
206 index = s->curpag << 8;
207 boundary = s->boundary << 8;
208 if (index < boundary)
209 avail = boundary - index;
210 else
211 avail = (s->stop - s->start) - (index - boundary);
212 if (avail < (MAX_ETH_FRAME_SIZE + 4))
213 return 1;
214 return 0;
215 }
216
217 static int ne2000_can_receive(void *opaque)
218 {
219 NE2000State *s = opaque;
220
221 if (s->cmd & E8390_STOP)
222 return 1;
223 return !ne2000_buffer_full(s);
224 }
225
226 #define MIN_BUF_SIZE 60
227
228 static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
229 {
230 NE2000State *s = opaque;
231 uint8_t *p;
232 unsigned int total_len, next, avail, len, index, mcast_idx;
233 uint8_t buf1[60];
234 static const uint8_t broadcast_macaddr[6] =
235 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
236
237 #if defined(DEBUG_NE2000)
238 printf("NE2000: received len=%d\n", size);
239 #endif
240
241 if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
242 return;
243
244 /* XXX: check this */
245 if (s->rxcr & 0x10) {
246 /* promiscuous: receive all */
247 } else {
248 if (!memcmp(buf, broadcast_macaddr, 6)) {
249 /* broadcast address */
250 if (!(s->rxcr & 0x04))
251 return;
252 } else if (buf[0] & 0x01) {
253 /* multicast */
254 if (!(s->rxcr & 0x08))
255 return;
256 mcast_idx = compute_mcast_idx(buf);
257 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
258 return;
259 } else if (s->mem[0] == buf[0] &&
260 s->mem[2] == buf[1] &&
261 s->mem[4] == buf[2] &&
262 s->mem[6] == buf[3] &&
263 s->mem[8] == buf[4] &&
264 s->mem[10] == buf[5]) {
265 /* match */
266 } else {
267 return;
268 }
269 }
270
271
272 /* if too small buffer, then expand it */
273 if (size < MIN_BUF_SIZE) {
274 memcpy(buf1, buf, size);
275 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
276 buf = buf1;
277 size = MIN_BUF_SIZE;
278 }
279
280 index = s->curpag << 8;
281 /* 4 bytes for header */
282 total_len = size + 4;
283 /* address for next packet (4 bytes for CRC) */
284 next = index + ((total_len + 4 + 255) & ~0xff);
285 if (next >= s->stop)
286 next -= (s->stop - s->start);
287 /* prepare packet header */
288 p = s->mem + index;
289 s->rsr = ENRSR_RXOK; /* receive status */
290 /* XXX: check this */
291 if (buf[0] & 0x01)
292 s->rsr |= ENRSR_PHY;
293 p[0] = s->rsr;
294 p[1] = next >> 8;
295 p[2] = total_len;
296 p[3] = total_len >> 8;
297 index += 4;
298
299 /* write packet data */
300 while (size > 0) {
301 if (index <= s->stop)
302 avail = s->stop - index;
303 else
304 avail = 0;
305 len = size;
306 if (len > avail)
307 len = avail;
308 memcpy(s->mem + index, buf, len);
309 buf += len;
310 index += len;
311 if (index == s->stop)
312 index = s->start;
313 size -= len;
314 }
315 s->curpag = next >> 8;
316
317 /* now we can signal we have received something */
318 s->isr |= ENISR_RX;
319 ne2000_update_irq(s);
320 }
321
322 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
323 {
324 NE2000State *s = opaque;
325 int offset, page, index;
326
327 addr &= 0xf;
328 #ifdef DEBUG_NE2000
329 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
330 #endif
331 if (addr == E8390_CMD) {
332 /* control register */
333 s->cmd = val;
334 if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
335 s->isr &= ~ENISR_RESET;
336 /* test specific case: zero length transfer */
337 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
338 s->rcnt == 0) {
339 s->isr |= ENISR_RDC;
340 ne2000_update_irq(s);
341 }
342 if (val & E8390_TRANS) {
343 index = (s->tpsr << 8);
344 /* XXX: next 2 lines are a hack to make netware 3.11 work */
345 if (index >= NE2000_PMEM_END)
346 index -= NE2000_PMEM_SIZE;
347 /* fail safe: check range on the transmitted length */
348 if (index + s->tcnt <= NE2000_PMEM_END) {
349 qemu_send_packet(s->vc, s->mem + index, s->tcnt);
350 }
351 /* signal end of transfer */
352 s->tsr = ENTSR_PTX;
353 s->isr |= ENISR_TX;
354 s->cmd &= ~E8390_TRANS;
355 ne2000_update_irq(s);
356 }
357 }
358 } else {
359 page = s->cmd >> 6;
360 offset = addr | (page << 4);
361 switch(offset) {
362 case EN0_STARTPG:
363 s->start = val << 8;
364 break;
365 case EN0_STOPPG:
366 s->stop = val << 8;
367 break;
368 case EN0_BOUNDARY:
369 s->boundary = val;
370 break;
371 case EN0_IMR:
372 s->imr = val;
373 ne2000_update_irq(s);
374 break;
375 case EN0_TPSR:
376 s->tpsr = val;
377 break;
378 case EN0_TCNTLO:
379 s->tcnt = (s->tcnt & 0xff00) | val;
380 break;
381 case EN0_TCNTHI:
382 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
383 break;
384 case EN0_RSARLO:
385 s->rsar = (s->rsar & 0xff00) | val;
386 break;
387 case EN0_RSARHI:
388 s->rsar = (s->rsar & 0x00ff) | (val << 8);
389 break;
390 case EN0_RCNTLO:
391 s->rcnt = (s->rcnt & 0xff00) | val;
392 break;
393 case EN0_RCNTHI:
394 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
395 break;
396 case EN0_RXCR:
397 s->rxcr = val;
398 break;
399 case EN0_DCFG:
400 s->dcfg = val;
401 break;
402 case EN0_ISR:
403 s->isr &= ~(val & 0x7f);
404 ne2000_update_irq(s);
405 break;
406 case EN1_PHYS ... EN1_PHYS + 5:
407 s->phys[offset - EN1_PHYS] = val;
408 break;
409 case EN1_CURPAG:
410 s->curpag = val;
411 break;
412 case EN1_MULT ... EN1_MULT + 7:
413 s->mult[offset - EN1_MULT] = val;
414 break;
415 }
416 }
417 }
418
419 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
420 {
421 NE2000State *s = opaque;
422 int offset, page, ret;
423
424 addr &= 0xf;
425 if (addr == E8390_CMD) {
426 ret = s->cmd;
427 } else {
428 page = s->cmd >> 6;
429 offset = addr | (page << 4);
430 switch(offset) {
431 case EN0_TSR:
432 ret = s->tsr;
433 break;
434 case EN0_BOUNDARY:
435 ret = s->boundary;
436 break;
437 case EN0_ISR:
438 ret = s->isr;
439 break;
440 case EN0_RSARLO:
441 ret = s->rsar & 0x00ff;
442 break;
443 case EN0_RSARHI:
444 ret = s->rsar >> 8;
445 break;
446 case EN1_PHYS ... EN1_PHYS + 5:
447 ret = s->phys[offset - EN1_PHYS];
448 break;
449 case EN1_CURPAG:
450 ret = s->curpag;
451 break;
452 case EN1_MULT ... EN1_MULT + 7:
453 ret = s->mult[offset - EN1_MULT];
454 break;
455 case EN0_RSR:
456 ret = s->rsr;
457 break;
458 case EN2_STARTPG:
459 ret = s->start >> 8;
460 break;
461 case EN2_STOPPG:
462 ret = s->stop >> 8;
463 break;
464 case EN0_RTL8029ID0:
465 ret = 0x50;
466 break;
467 case EN0_RTL8029ID1:
468 ret = 0x43;
469 break;
470 case EN3_CONFIG0:
471 ret = 0; /* 10baseT media */
472 break;
473 case EN3_CONFIG2:
474 ret = 0x40; /* 10baseT active */
475 break;
476 case EN3_CONFIG3:
477 ret = 0x40; /* Full duplex */
478 break;
479 default:
480 ret = 0x00;
481 break;
482 }
483 }
484 #ifdef DEBUG_NE2000
485 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
486 #endif
487 return ret;
488 }
489
490 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
491 uint32_t val)
492 {
493 if (addr < 32 ||
494 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
495 s->mem[addr] = val;
496 }
497 }
498
499 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
500 uint32_t val)
501 {
502 addr &= ~1; /* XXX: check exact behaviour if not even */
503 if (addr < 32 ||
504 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
505 *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
506 }
507 }
508
509 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
510 uint32_t val)
511 {
512 addr &= ~1; /* XXX: check exact behaviour if not even */
513 if (addr < 32 ||
514 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
515 cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
516 }
517 }
518
519 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
520 {
521 if (addr < 32 ||
522 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
523 return s->mem[addr];
524 } else {
525 return 0xff;
526 }
527 }
528
529 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
530 {
531 addr &= ~1; /* XXX: check exact behaviour if not even */
532 if (addr < 32 ||
533 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
534 return le16_to_cpu(*(uint16_t *)(s->mem + addr));
535 } else {
536 return 0xffff;
537 }
538 }
539
540 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
541 {
542 addr &= ~1; /* XXX: check exact behaviour if not even */
543 if (addr < 32 ||
544 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
545 return le32_to_cpupu((uint32_t *)(s->mem + addr));
546 } else {
547 return 0xffffffff;
548 }
549 }
550
551 static inline void ne2000_dma_update(NE2000State *s, int len)
552 {
553 s->rsar += len;
554 /* wrap */
555 /* XXX: check what to do if rsar > stop */
556 if (s->rsar == s->stop)
557 s->rsar = s->start;
558
559 if (s->rcnt <= len) {
560 s->rcnt = 0;
561 /* signal end of transfer */
562 s->isr |= ENISR_RDC;
563 ne2000_update_irq(s);
564 } else {
565 s->rcnt -= len;
566 }
567 }
568
569 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
570 {
571 NE2000State *s = opaque;
572
573 #ifdef DEBUG_NE2000
574 printf("NE2000: asic write val=0x%04x\n", val);
575 #endif
576 if (s->rcnt == 0)
577 return;
578 if (s->dcfg & 0x01) {
579 /* 16 bit access */
580 ne2000_mem_writew(s, s->rsar, val);
581 ne2000_dma_update(s, 2);
582 } else {
583 /* 8 bit access */
584 ne2000_mem_writeb(s, s->rsar, val);
585 ne2000_dma_update(s, 1);
586 }
587 }
588
589 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
590 {
591 NE2000State *s = opaque;
592 int ret;
593
594 if (s->dcfg & 0x01) {
595 /* 16 bit access */
596 ret = ne2000_mem_readw(s, s->rsar);
597 ne2000_dma_update(s, 2);
598 } else {
599 /* 8 bit access */
600 ret = ne2000_mem_readb(s, s->rsar);
601 ne2000_dma_update(s, 1);
602 }
603 #ifdef DEBUG_NE2000
604 printf("NE2000: asic read val=0x%04x\n", ret);
605 #endif
606 return ret;
607 }
608
609 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
610 {
611 NE2000State *s = opaque;
612
613 #ifdef DEBUG_NE2000
614 printf("NE2000: asic writel val=0x%04x\n", val);
615 #endif
616 if (s->rcnt == 0)
617 return;
618 /* 32 bit access */
619 ne2000_mem_writel(s, s->rsar, val);
620 ne2000_dma_update(s, 4);
621 }
622
623 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
624 {
625 NE2000State *s = opaque;
626 int ret;
627
628 /* 32 bit access */
629 ret = ne2000_mem_readl(s, s->rsar);
630 ne2000_dma_update(s, 4);
631 #ifdef DEBUG_NE2000
632 printf("NE2000: asic readl val=0x%04x\n", ret);
633 #endif
634 return ret;
635 }
636
637 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
638 {
639 /* nothing to do (end of reset pulse) */
640 }
641
642 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
643 {
644 NE2000State *s = opaque;
645 ne2000_reset(s);
646 return 0;
647 }
648
649 static void ne2000_save(QEMUFile* f,void* opaque)
650 {
651 NE2000State* s=(NE2000State*)opaque;
652 uint32_t tmp;
653
654 if (s->pci_dev)
655 pci_device_save(s->pci_dev, f);
656
657 qemu_put_8s(f, &s->rxcr);
658
659 qemu_put_8s(f, &s->cmd);
660 qemu_put_be32s(f, &s->start);
661 qemu_put_be32s(f, &s->stop);
662 qemu_put_8s(f, &s->boundary);
663 qemu_put_8s(f, &s->tsr);
664 qemu_put_8s(f, &s->tpsr);
665 qemu_put_be16s(f, &s->tcnt);
666 qemu_put_be16s(f, &s->rcnt);
667 qemu_put_be32s(f, &s->rsar);
668 qemu_put_8s(f, &s->rsr);
669 qemu_put_8s(f, &s->isr);
670 qemu_put_8s(f, &s->dcfg);
671 qemu_put_8s(f, &s->imr);
672 qemu_put_buffer(f, s->phys, 6);
673 qemu_put_8s(f, &s->curpag);
674 qemu_put_buffer(f, s->mult, 8);
675 tmp = 0;
676 qemu_put_be32s(f, &tmp); /* ignored, was irq */
677 qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
678 }
679
680 static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
681 {
682 NE2000State* s=(NE2000State*)opaque;
683 int ret;
684 uint32_t tmp;
685
686 if (version_id > 3)
687 return -EINVAL;
688
689 if (s->pci_dev && version_id >= 3) {
690 ret = pci_device_load(s->pci_dev, f);
691 if (ret < 0)
692 return ret;
693 }
694
695 if (version_id >= 2) {
696 qemu_get_8s(f, &s->rxcr);
697 } else {
698 s->rxcr = 0x0c;
699 }
700
701 qemu_get_8s(f, &s->cmd);
702 qemu_get_be32s(f, &s->start);
703 qemu_get_be32s(f, &s->stop);
704 qemu_get_8s(f, &s->boundary);
705 qemu_get_8s(f, &s->tsr);
706 qemu_get_8s(f, &s->tpsr);
707 qemu_get_be16s(f, &s->tcnt);
708 qemu_get_be16s(f, &s->rcnt);
709 qemu_get_be32s(f, &s->rsar);
710 qemu_get_8s(f, &s->rsr);
711 qemu_get_8s(f, &s->isr);
712 qemu_get_8s(f, &s->dcfg);
713 qemu_get_8s(f, &s->imr);
714 qemu_get_buffer(f, s->phys, 6);
715 qemu_get_8s(f, &s->curpag);
716 qemu_get_buffer(f, s->mult, 8);
717 qemu_get_be32s(f, &tmp); /* ignored */
718 qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
719
720 return 0;
721 }
722
723 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd)
724 {
725 NE2000State *s;
726
727 s = qemu_mallocz(sizeof(NE2000State));
728 if (!s)
729 return;
730
731 register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
732 register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
733
734 register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
735 register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
736 register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
737 register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
738
739 register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
740 register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
741 s->irq = irq;
742 memcpy(s->macaddr, nd->macaddr, 6);
743
744 ne2000_reset(s);
745
746 s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive,
747 ne2000_can_receive, s);
748
749 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
750 "ne2000 macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
751 s->macaddr[0],
752 s->macaddr[1],
753 s->macaddr[2],
754 s->macaddr[3],
755 s->macaddr[4],
756 s->macaddr[5]);
757
758 register_savevm("ne2000", ne2000_id++, 2, ne2000_save, ne2000_load, s);
759 }
760
761 /***********************************************************/
762 /* PCI NE2000 definitions */
763
764 typedef struct PCINE2000State {
765 PCIDevice dev;
766 NE2000State ne2000;
767 } PCINE2000State;
768
769 static void ne2000_map(PCIDevice *pci_dev, int region_num,
770 uint32_t addr, uint32_t size, int type)
771 {
772 PCINE2000State *d = (PCINE2000State *)pci_dev;
773 NE2000State *s = &d->ne2000;
774
775 register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
776 register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
777
778 register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
779 register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
780 register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
781 register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
782 register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
783 register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
784
785 register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
786 register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
787 }
788
789 PCIDevice *pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn)
790 {
791 PCINE2000State *d;
792 NE2000State *s;
793 uint8_t *pci_conf;
794
795 d = (PCINE2000State *)pci_register_device(bus,
796 "NE2000", sizeof(PCINE2000State),
797 devfn,
798 NULL, NULL);
799 if (!d)
800 return NULL;
801
802 pci_conf = d->dev.config;
803 pci_conf[0x00] = 0xec; // Realtek 8029
804 pci_conf[0x01] = 0x10;
805 pci_conf[0x02] = 0x29;
806 pci_conf[0x03] = 0x80;
807 pci_conf[0x0a] = 0x00; // ethernet network controller
808 pci_conf[0x0b] = 0x02;
809 pci_conf[0x0e] = 0x00; // header_type
810 pci_conf[0x3d] = 1; // interrupt pin 0
811
812 pci_register_io_region(&d->dev, 0, 0x100,
813 PCI_ADDRESS_SPACE_IO, ne2000_map);
814 s = &d->ne2000;
815 s->irq = d->dev.irq[0];
816 s->pci_dev = (PCIDevice *)d;
817 memcpy(s->macaddr, nd->macaddr, 6);
818 ne2000_reset(s);
819 s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive,
820 ne2000_can_receive, s);
821
822 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
823 "ne2000 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
824 s->macaddr[0],
825 s->macaddr[1],
826 s->macaddr[2],
827 s->macaddr[3],
828 s->macaddr[4],
829 s->macaddr[5]);
830
831 /* XXX: instance number ? */
832 register_savevm("ne2000", ne2000_id++, 3, ne2000_save, ne2000_load, s);
833
834 return (PCIDevice *)d;
835 }
Mark McLoughlin's queue for qemu-kvm.git