hw/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc405.h"
  27 #include "nvram.h"
  28 #include "flash.h"
  29 #include "sysemu.h"
  30 #include "block.h"
  31 #include "boards.h"
  32 #include "qemu-log.h"
  33 #include "loader.h"
  34
  35 #define BIOS_FILENAME "ppc405_rom.bin"
  36 #define BIOS_SIZE (2048 * 1024)
  37
  38 #define KERNEL_LOAD_ADDR 0x00000000
  39 #define INITRD_LOAD_ADDR 0x01800000
  40
  41 #define USE_FLASH_BIOS
  42
  43 #define DEBUG_BOARD_INIT
  44
  45 /*****************************************************************************/
  46 /* PPC405EP reference board (IBM) */
  47 /* Standalone board with:
  48  * - PowerPC 405EP CPU
  49  * - SDRAM (0x00000000)
  50  * - Flash (0xFFF80000)
  51  * - SRAM  (0xFFF00000)
  52  * - NVRAM (0xF0000000)
  53  * - FPGA  (0xF0300000)
  54  */
  55 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  56 struct ref405ep_fpga_t {
  57     uint8_t reg0;
  58     uint8_t reg1;
  59 };
  60
  61 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
  62 {
  63     ref405ep_fpga_t *fpga;
  64     uint32_t ret;
  65
  66     fpga = opaque;
  67     switch (addr) {
  68     case 0x0:
  69         ret = fpga->reg0;
  70         break;
  71     case 0x1:
  72         ret = fpga->reg1;
  73         break;
  74     default:
  75         ret = 0;
  76         break;
  77     }
  78
  79     return ret;
  80 }
  81
  82 static void ref405ep_fpga_writeb (void *opaque,
  83                                   target_phys_addr_t addr, uint32_t value)
  84 {
  85     ref405ep_fpga_t *fpga;
  86
  87     fpga = opaque;
  88     switch (addr) {
  89     case 0x0:
  90         /* Read only */
  91         break;
  92     case 0x1:
  93         fpga->reg1 = value;
  94         break;
  95     default:
  96         break;
  97     }
  98 }
  99
 100 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
 101 {
 102     uint32_t ret;
 103
 104     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 105     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 106
 107     return ret;
 108 }
 109
 110 static void ref405ep_fpga_writew (void *opaque,
 111                                   target_phys_addr_t addr, uint32_t value)
 112 {
 113     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 114     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 115 }
 116
 117 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 118 {
 119     uint32_t ret;
 120
 121     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 122     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 123     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 124     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 125
 126     return ret;
 127 }
 128
 129 static void ref405ep_fpga_writel (void *opaque,
 130                                   target_phys_addr_t addr, uint32_t value)
 131 {
 132     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 133     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 134     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 135     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 136 }
 137
 138 static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
 139     &ref405ep_fpga_readb,
 140     &ref405ep_fpga_readw,
 141     &ref405ep_fpga_readl,
 142 };
 143
 144 static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
 145     &ref405ep_fpga_writeb,
 146     &ref405ep_fpga_writew,
 147     &ref405ep_fpga_writel,
 148 };
 149
 150 static void ref405ep_fpga_reset (void *opaque)
 151 {
 152     ref405ep_fpga_t *fpga;
 153
 154     fpga = opaque;
 155     fpga->reg0 = 0x00;
 156     fpga->reg1 = 0x0F;
 157 }
 158
 159 static void ref405ep_fpga_init (uint32_t base)
 160 {
 161     ref405ep_fpga_t *fpga;
 162     int fpga_memory;
 163
 164     fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
 165     fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
 166                                          ref405ep_fpga_write, fpga);
 167     cpu_register_physical_memory(base, 0x00000100, fpga_memory);
 168     ref405ep_fpga_reset(fpga);
 169     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 170 }
 171
 172 static void ref405ep_init (ram_addr_t ram_size,
 173                            const char *boot_device,
 174                            const char *kernel_filename,
 175                            const char *kernel_cmdline,
 176                            const char *initrd_filename,
 177                            const char *cpu_model)
 178 {
 179     char *filename;
 180     ppc4xx_bd_info_t bd;
 181     CPUPPCState *env;
 182     qemu_irq *pic;
 183     ram_addr_t sram_offset, bios_offset, bdloc;
 184     target_phys_addr_t ram_bases[2], ram_sizes[2];
 185     target_ulong sram_size, bios_size;
 186     //int phy_addr = 0;
 187     //static int phy_addr = 1;
 188     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 189     int linux_boot;
 190     int fl_idx, fl_sectors, len;
 191     int ppc_boot_device = boot_device[0];
 192     DriveInfo *dinfo;
 193
 194     /* XXX: fix this */
 195     ram_bases[0] = qemu_ram_alloc(0x08000000);
 196     ram_sizes[0] = 0x08000000;
 197     ram_bases[1] = 0x00000000;
 198     ram_sizes[1] = 0x00000000;
 199     ram_size = 128 * 1024 * 1024;
 200 #ifdef DEBUG_BOARD_INIT
 201     printf("%s: register cpu\n", __func__);
 202 #endif
 203     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 204                         kernel_filename == NULL ? 0 : 1);
 205     /* allocate SRAM */
 206     sram_size = 512 * 1024;
 207     sram_offset = qemu_ram_alloc(sram_size);
 208 #ifdef DEBUG_BOARD_INIT
 209     printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
 210 #endif
 211     cpu_register_physical_memory(0xFFF00000, sram_size,
 212                                  sram_offset | IO_MEM_RAM);
 213     /* allocate and load BIOS */
 214 #ifdef DEBUG_BOARD_INIT
 215     printf("%s: register BIOS\n", __func__);
 216 #endif
 217     fl_idx = 0;
 218 #ifdef USE_FLASH_BIOS
 219     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 220     if (dinfo) {
 221         bios_size = bdrv_getlength(dinfo->bdrv);
 222         bios_offset = qemu_ram_alloc(bios_size);
 223         fl_sectors = (bios_size + 65535) >> 16;
 224 #ifdef DEBUG_BOARD_INIT
 225         printf("Register parallel flash %d size " TARGET_FMT_lx
 226                " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
 227                fl_idx, bios_size, bios_offset, -bios_size,
 228                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 229 #endif
 230         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 231                               dinfo->bdrv, 65536, fl_sectors, 1,
 232                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 233         fl_idx++;
 234     } else
 235 #endif
 236     {
 237 #ifdef DEBUG_BOARD_INIT
 238         printf("Load BIOS from file\n");
 239 #endif
 240         bios_offset = qemu_ram_alloc(BIOS_SIZE);
 241         if (bios_name == NULL)
 242             bios_name = BIOS_FILENAME;
 243         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 244         if (filename) {
 245             bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
 246             qemu_free(filename);
 247         } else {
 248             bios_size = -1;
 249         }
 250         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 251             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 252                     bios_name);
 253             exit(1);
 254         }
 255         bios_size = (bios_size + 0xfff) & ~0xfff;
 256         cpu_register_physical_memory((uint32_t)(-bios_size),
 257                                      bios_size, bios_offset | IO_MEM_ROM);
 258     }
 259     /* Register FPGA */
 260 #ifdef DEBUG_BOARD_INIT
 261     printf("%s: register FPGA\n", __func__);
 262 #endif
 263     ref405ep_fpga_init(0xF0300000);
 264     /* Register NVRAM */
 265 #ifdef DEBUG_BOARD_INIT
 266     printf("%s: register NVRAM\n", __func__);
 267 #endif
 268     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 269     /* Load kernel */
 270     linux_boot = (kernel_filename != NULL);
 271     if (linux_boot) {
 272 #ifdef DEBUG_BOARD_INIT
 273         printf("%s: load kernel\n", __func__);
 274 #endif
 275         memset(&bd, 0, sizeof(bd));
 276         bd.bi_memstart = 0x00000000;
 277         bd.bi_memsize = ram_size;
 278         bd.bi_flashstart = -bios_size;
 279         bd.bi_flashsize = -bios_size;
 280         bd.bi_flashoffset = 0;
 281         bd.bi_sramstart = 0xFFF00000;
 282         bd.bi_sramsize = sram_size;
 283         bd.bi_bootflags = 0;
 284         bd.bi_intfreq = 133333333;
 285         bd.bi_busfreq = 33333333;
 286         bd.bi_baudrate = 115200;
 287         bd.bi_s_version[0] = 'Q';
 288         bd.bi_s_version[1] = 'M';
 289         bd.bi_s_version[2] = 'U';
 290         bd.bi_s_version[3] = '\0';
 291         bd.bi_r_version[0] = 'Q';
 292         bd.bi_r_version[1] = 'E';
 293         bd.bi_r_version[2] = 'M';
 294         bd.bi_r_version[3] = 'U';
 295         bd.bi_r_version[4] = '\0';
 296         bd.bi_procfreq = 133333333;
 297         bd.bi_plb_busfreq = 33333333;
 298         bd.bi_pci_busfreq = 33333333;
 299         bd.bi_opbfreq = 33333333;
 300         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 301         env->gpr[3] = bdloc;
 302         kernel_base = KERNEL_LOAD_ADDR;
 303         /* now we can load the kernel */
 304         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 305                                           ram_size - kernel_base);
 306         if (kernel_size < 0) {
 307             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 308                     kernel_filename);
 309             exit(1);
 310         }
 311         printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx,
 312                kernel_size, kernel_base);
 313         /* load initrd */
 314         if (initrd_filename) {
 315             initrd_base = INITRD_LOAD_ADDR;
 316             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 317                                               ram_size - initrd_base);
 318             if (initrd_size < 0) {
 319                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 320                         initrd_filename);
 321                 exit(1);
 322             }
 323         } else {
 324             initrd_base = 0;
 325             initrd_size = 0;
 326         }
 327         env->gpr[4] = initrd_base;
 328         env->gpr[5] = initrd_size;
 329         ppc_boot_device = 'm';
 330         if (kernel_cmdline != NULL) {
 331             len = strlen(kernel_cmdline);
 332             bdloc -= ((len + 255) & ~255);
 333             cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
 334             env->gpr[6] = bdloc;
 335             env->gpr[7] = bdloc + len;
 336         } else {
 337             env->gpr[6] = 0;
 338             env->gpr[7] = 0;
 339         }
 340         env->nip = KERNEL_LOAD_ADDR;
 341     } else {
 342         kernel_base = 0;
 343         kernel_size = 0;
 344         initrd_base = 0;
 345         initrd_size = 0;
 346         bdloc = 0;
 347     }
 348 #ifdef DEBUG_BOARD_INIT
 349     printf("%s: Done\n", __func__);
 350 #endif
 351     printf("bdloc %016lx\n", (unsigned long)bdloc);
 352 }
 353
 354 static QEMUMachine ref405ep_machine = {
 355     .name = "ref405ep",
 356     .desc = "ref405ep",
 357     .init = ref405ep_init,
 358 };
 359
 360 /*****************************************************************************/
 361 /* AMCC Taihu evaluation board */
 362 /* - PowerPC 405EP processor
 363  * - SDRAM               128 MB at 0x00000000
 364  * - Boot flash          2 MB   at 0xFFE00000
 365  * - Application flash   32 MB  at 0xFC000000
 366  * - 2 serial ports
 367  * - 2 ethernet PHY
 368  * - 1 USB 1.1 device    0x50000000
 369  * - 1 LCD display       0x50100000
 370  * - 1 CPLD              0x50100000
 371  * - 1 I2C EEPROM
 372  * - 1 I2C thermal sensor
 373  * - a set of LEDs
 374  * - bit-bang SPI port using GPIOs
 375  * - 1 EBC interface connector 0 0x50200000
 376  * - 1 cardbus controller + expansion slot.
 377  * - 1 PCI expansion slot.
 378  */
 379 typedef struct taihu_cpld_t taihu_cpld_t;
 380 struct taihu_cpld_t {
 381     uint8_t reg0;
 382     uint8_t reg1;
 383 };
 384
 385 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
 386 {
 387     taihu_cpld_t *cpld;
 388     uint32_t ret;
 389
 390     cpld = opaque;
 391     switch (addr) {
 392     case 0x0:
 393         ret = cpld->reg0;
 394         break;
 395     case 0x1:
 396         ret = cpld->reg1;
 397         break;
 398     default:
 399         ret = 0;
 400         break;
 401     }
 402
 403     return ret;
 404 }
 405
 406 static void taihu_cpld_writeb (void *opaque,
 407                                target_phys_addr_t addr, uint32_t value)
 408 {
 409     taihu_cpld_t *cpld;
 410
 411     cpld = opaque;
 412     switch (addr) {
 413     case 0x0:
 414         /* Read only */
 415         break;
 416     case 0x1:
 417         cpld->reg1 = value;
 418         break;
 419     default:
 420         break;
 421     }
 422 }
 423
 424 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
 425 {
 426     uint32_t ret;
 427
 428     ret = taihu_cpld_readb(opaque, addr) << 8;
 429     ret |= taihu_cpld_readb(opaque, addr + 1);
 430
 431     return ret;
 432 }
 433
 434 static void taihu_cpld_writew (void *opaque,
 435                                target_phys_addr_t addr, uint32_t value)
 436 {
 437     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 438     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 439 }
 440
 441 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
 442 {
 443     uint32_t ret;
 444
 445     ret = taihu_cpld_readb(opaque, addr) << 24;
 446     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 447     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 448     ret |= taihu_cpld_readb(opaque, addr + 3);
 449
 450     return ret;
 451 }
 452
 453 static void taihu_cpld_writel (void *opaque,
 454                                target_phys_addr_t addr, uint32_t value)
 455 {
 456     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 457     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 458     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 459     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 460 }
 461
 462 static CPUReadMemoryFunc * const taihu_cpld_read[] = {
 463     &taihu_cpld_readb,
 464     &taihu_cpld_readw,
 465     &taihu_cpld_readl,
 466 };
 467
 468 static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
 469     &taihu_cpld_writeb,
 470     &taihu_cpld_writew,
 471     &taihu_cpld_writel,
 472 };
 473
 474 static void taihu_cpld_reset (void *opaque)
 475 {
 476     taihu_cpld_t *cpld;
 477
 478     cpld = opaque;
 479     cpld->reg0 = 0x01;
 480     cpld->reg1 = 0x80;
 481 }
 482
 483 static void taihu_cpld_init (uint32_t base)
 484 {
 485     taihu_cpld_t *cpld;
 486     int cpld_memory;
 487
 488     cpld = qemu_mallocz(sizeof(taihu_cpld_t));
 489     cpld_memory = cpu_register_io_memory(taihu_cpld_read,
 490                                          taihu_cpld_write, cpld);
 491     cpu_register_physical_memory(base, 0x00000100, cpld_memory);
 492     taihu_cpld_reset(cpld);
 493     qemu_register_reset(&taihu_cpld_reset, cpld);
 494 }
 495
 496 static void taihu_405ep_init(ram_addr_t ram_size,
 497                              const char *boot_device,
 498                              const char *kernel_filename,
 499                              const char *kernel_cmdline,
 500                              const char *initrd_filename,
 501                              const char *cpu_model)
 502 {
 503     char *filename;
 504     CPUPPCState *env;
 505     qemu_irq *pic;
 506     ram_addr_t bios_offset;
 507     target_phys_addr_t ram_bases[2], ram_sizes[2];
 508     target_ulong bios_size;
 509     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 510     int linux_boot;
 511     int fl_idx, fl_sectors;
 512     int ppc_boot_device = boot_device[0];
 513     DriveInfo *dinfo;
 514
 515     /* RAM is soldered to the board so the size cannot be changed */
 516     ram_bases[0] = qemu_ram_alloc(0x04000000);
 517     ram_sizes[0] = 0x04000000;
 518     ram_bases[1] = qemu_ram_alloc(0x04000000);
 519     ram_sizes[1] = 0x04000000;
 520     ram_size = 0x08000000;
 521 #ifdef DEBUG_BOARD_INIT
 522     printf("%s: register cpu\n", __func__);
 523 #endif
 524     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 525                         kernel_filename == NULL ? 0 : 1);
 526     /* allocate and load BIOS */
 527 #ifdef DEBUG_BOARD_INIT
 528     printf("%s: register BIOS\n", __func__);
 529 #endif
 530     fl_idx = 0;
 531 #if defined(USE_FLASH_BIOS)
 532     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 533     if (dinfo) {
 534         bios_size = bdrv_getlength(dinfo->bdrv);
 535         /* XXX: should check that size is 2MB */
 536         //        bios_size = 2 * 1024 * 1024;
 537         fl_sectors = (bios_size + 65535) >> 16;
 538         bios_offset = qemu_ram_alloc(bios_size);
 539 #ifdef DEBUG_BOARD_INIT
 540         printf("Register parallel flash %d size " TARGET_FMT_lx
 541                " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
 542                fl_idx, bios_size, bios_offset, -bios_size,
 543                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 544 #endif
 545         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 546                               dinfo->bdrv, 65536, fl_sectors, 1,
 547                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 548         fl_idx++;
 549     } else
 550 #endif
 551     {
 552 #ifdef DEBUG_BOARD_INIT
 553         printf("Load BIOS from file\n");
 554 #endif
 555         if (bios_name == NULL)
 556             bios_name = BIOS_FILENAME;
 557         bios_offset = qemu_ram_alloc(BIOS_SIZE);
 558         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 559         if (filename) {
 560             bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
 561         } else {
 562             bios_size = -1;
 563         }
 564         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 565             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 566                     bios_name);
 567             exit(1);
 568         }
 569         bios_size = (bios_size + 0xfff) & ~0xfff;
 570         cpu_register_physical_memory((uint32_t)(-bios_size),
 571                                      bios_size, bios_offset | IO_MEM_ROM);
 572     }
 573     /* Register Linux flash */
 574     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 575     if (dinfo) {
 576         bios_size = bdrv_getlength(dinfo->bdrv);
 577         /* XXX: should check that size is 32MB */
 578         bios_size = 32 * 1024 * 1024;
 579         fl_sectors = (bios_size + 65535) >> 16;
 580 #ifdef DEBUG_BOARD_INIT
 581         printf("Register parallel flash %d size " TARGET_FMT_lx
 582                " at offset %08lx  addr " TARGET_FMT_lx " '%s'\n",
 583                fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
 584                bdrv_get_device_name(dinfo->bdrv));
 585 #endif
 586         bios_offset = qemu_ram_alloc(bios_size);
 587         pflash_cfi02_register(0xfc000000, bios_offset,
 588                               dinfo->bdrv, 65536, fl_sectors, 1,
 589                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 590         fl_idx++;
 591     }
 592     /* Register CLPD & LCD display */
 593 #ifdef DEBUG_BOARD_INIT
 594     printf("%s: register CPLD\n", __func__);
 595 #endif
 596     taihu_cpld_init(0x50100000);
 597     /* Load kernel */
 598     linux_boot = (kernel_filename != NULL);
 599     if (linux_boot) {
 600 #ifdef DEBUG_BOARD_INIT
 601         printf("%s: load kernel\n", __func__);
 602 #endif
 603         kernel_base = KERNEL_LOAD_ADDR;
 604         /* now we can load the kernel */
 605         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 606                                           ram_size - kernel_base);
 607         if (kernel_size < 0) {
 608             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 609                     kernel_filename);
 610             exit(1);
 611         }
 612         /* load initrd */
 613         if (initrd_filename) {
 614             initrd_base = INITRD_LOAD_ADDR;
 615             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 616                                               ram_size - initrd_base);
 617             if (initrd_size < 0) {
 618                 fprintf(stderr,
 619                         "qemu: could not load initial ram disk '%s'\n",
 620                         initrd_filename);
 621                 exit(1);
 622             }
 623         } else {
 624             initrd_base = 0;
 625             initrd_size = 0;
 626         }
 627         ppc_boot_device = 'm';
 628     } else {
 629         kernel_base = 0;
 630         kernel_size = 0;
 631         initrd_base = 0;
 632         initrd_size = 0;
 633     }
 634 #ifdef DEBUG_BOARD_INIT
 635     printf("%s: Done\n", __func__);
 636 #endif
 637 }
 638
 639 static QEMUMachine taihu_machine = {
 640     .name = "taihu",
 641     .desc = "taihu",
 642     .init = taihu_405ep_init,
 643 };
 644
 645 static void ppc405_machine_init(void)
 646 {
 647     qemu_register_machine(&ref405ep_machine);
 648     qemu_register_machine(&taihu_machine);
 649 }
 650
 651 machine_init(ppc405_machine_init);