hw/pci_host.h

   1 /*
   2  * QEMU Common PCI Host bridge configuration data space access routines.
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 /* Worker routines for a PCI host controller that uses an {address,data}
  26    register pair to access PCI configuration space.  */
  27
  28 /* debug PCI */
  29 //#define DEBUG_PCI
  30
  31 #include "sysbus.h"
  32
  33 #ifdef DEBUG_PCI
  34 #define PCI_DPRINTF(fmt, ...) \
  35 do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
  36 #else
  37 #define PCI_DPRINTF(fmt, ...)
  38 #endif
  39
  40 typedef struct {
  41     SysBusDevice busdev;
  42     uint32_t config_reg;
  43     PCIBus *bus;
  44 } PCIHostState;
  45
  46 static void pci_host_data_writeb(void* opaque, pci_addr_t addr, uint32_t val)
  47 {
  48     PCIHostState *s = opaque;
  49
  50     PCI_DPRINTF("writeb addr " TARGET_FMT_plx " val %x\n",
  51                 (target_phys_addr_t)addr, val);
  52     if (s->config_reg & (1u << 31))
  53         pci_data_write(s->bus, s->config_reg | (addr & 3), val, 1);
  54 }
  55
  56 static void pci_host_data_writew(void* opaque, pci_addr_t addr, uint32_t val)
  57 {
  58     PCIHostState *s = opaque;
  59 #ifdef TARGET_WORDS_BIGENDIAN
  60     val = bswap16(val);
  61 #endif
  62     PCI_DPRINTF("writew addr " TARGET_FMT_plx " val %x\n",
  63                 (target_phys_addr_t)addr, val);
  64     if (s->config_reg & (1u << 31))
  65         pci_data_write(s->bus, s->config_reg | (addr & 3), val, 2);
  66 }
  67
  68 static void pci_host_data_writel(void* opaque, pci_addr_t addr, uint32_t val)
  69 {
  70     PCIHostState *s = opaque;
  71 #ifdef TARGET_WORDS_BIGENDIAN
  72     val = bswap32(val);
  73 #endif
  74     PCI_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n",
  75                 (target_phys_addr_t)addr, val);
  76     if (s->config_reg & (1u << 31))
  77         pci_data_write(s->bus, s->config_reg, val, 4);
  78 }
  79
  80 static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr)
  81 {
  82     PCIHostState *s = opaque;
  83     uint32_t val;
  84
  85     if (!(s->config_reg & (1 << 31)))
  86         return 0xff;
  87     val = pci_data_read(s->bus, s->config_reg | (addr & 3), 1);
  88     PCI_DPRINTF("readb addr " TARGET_FMT_plx " val %x\n",
  89                 (target_phys_addr_t)addr, val);
  90     return val;
  91 }
  92
  93 static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr)
  94 {
  95     PCIHostState *s = opaque;
  96     uint32_t val;
  97     if (!(s->config_reg & (1 << 31)))
  98         return 0xffff;
  99     val = pci_data_read(s->bus, s->config_reg | (addr & 3), 2);
 100     PCI_DPRINTF("readw addr " TARGET_FMT_plx " val %x\n",
 101                 (target_phys_addr_t)addr, val);
 102 #ifdef TARGET_WORDS_BIGENDIAN
 103     val = bswap16(val);
 104 #endif
 105     return val;
 106 }
 107
 108 static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr)
 109 {
 110     PCIHostState *s = opaque;
 111     uint32_t val;
 112     if (!(s->config_reg & (1 << 31)))
 113         return 0xffffffff;
 114     val = pci_data_read(s->bus, s->config_reg | (addr & 3), 4);
 115     PCI_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n",
 116                 (target_phys_addr_t)addr, val);
 117 #ifdef TARGET_WORDS_BIGENDIAN
 118     val = bswap32(val);
 119 #endif
 120     return val;
 121 }