target-mips/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3
   4 #include "exec-all.h"
   5
   6 static void save_tc(QEMUFile *f, TCState *tc)
   7 {
   8     int i;
   9
  10     /* Save active TC */
  11     for(i = 0; i < 32; i++)
  12         qemu_put_betls(f, &tc->gpr[i]);
  13     qemu_put_betls(f, &tc->PC);
  14     for(i = 0; i < MIPS_DSP_ACC; i++)
  15         qemu_put_betls(f, &tc->HI[i]);
  16     for(i = 0; i < MIPS_DSP_ACC; i++)
  17         qemu_put_betls(f, &tc->LO[i]);
  18     for(i = 0; i < MIPS_DSP_ACC; i++)
  19         qemu_put_betls(f, &tc->ACX[i]);
  20     qemu_put_betls(f, &tc->DSPControl);
  21     qemu_put_sbe32s(f, &tc->CP0_TCStatus);
  22     qemu_put_sbe32s(f, &tc->CP0_TCBind);
  23     qemu_put_betls(f, &tc->CP0_TCHalt);
  24     qemu_put_betls(f, &tc->CP0_TCContext);
  25     qemu_put_betls(f, &tc->CP0_TCSchedule);
  26     qemu_put_betls(f, &tc->CP0_TCScheFBack);
  27     qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
  28 }
  29
  30 static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
  31 {
  32     int i;
  33
  34     for(i = 0; i < 32; i++)
  35         qemu_put_be64s(f, &fpu->fpr[i].d);
  36     qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess);
  37     qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode);
  38     qemu_put_s8s(f, &fpu->fp_status.float_exception_flags);
  39     qemu_put_be32s(f, &fpu->fcr0);
  40     qemu_put_be32s(f, &fpu->fcr31);
  41 }
  42
  43 void cpu_save(QEMUFile *f, void *opaque)
  44 {
  45     CPUState *env = opaque;
  46     int i;
  47
  48     /* Save active TC */
  49     save_tc(f, &env->active_tc);
  50
  51     /* Save active FPU */
  52     save_fpu(f, &env->active_fpu);
  53
  54     /* Save MVP */
  55     qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
  56     qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
  57     qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
  58
  59     /* Save TLB */
  60     qemu_put_be32s(f, &env->tlb->nb_tlb);
  61     qemu_put_be32s(f, &env->tlb->tlb_in_use);
  62     for(i = 0; i < MIPS_TLB_MAX; i++) {
  63         uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].G << 10) |
  64                           (env->tlb->mmu.r4k.tlb[i].C0 << 7) |
  65                           (env->tlb->mmu.r4k.tlb[i].C1 << 4) |
  66                           (env->tlb->mmu.r4k.tlb[i].V0 << 3) |
  67                           (env->tlb->mmu.r4k.tlb[i].V1 << 2) |
  68                           (env->tlb->mmu.r4k.tlb[i].D0 << 1) |
  69                           (env->tlb->mmu.r4k.tlb[i].D1 << 0));
  70
  71         qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
  72         qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
  73         qemu_put_8s(f, &env->tlb->mmu.r4k.tlb[i].ASID);
  74         qemu_put_be16s(f, &flags);
  75         qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
  76         qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
  77     }
  78
  79     /* Save CPU metastate */
  80     qemu_put_be32s(f, &env->current_tc);
  81     qemu_put_be32s(f, &env->current_fpu);
  82     qemu_put_sbe32s(f, &env->error_code);
  83     qemu_put_be32s(f, &env->hflags);
  84     qemu_put_betls(f, &env->btarget);
  85     i = env->bcond;
  86     qemu_put_sbe32s(f, &i);
  87
  88     /* Save remaining CP1 registers */
  89     qemu_put_sbe32s(f, &env->CP0_Index);
  90     qemu_put_sbe32s(f, &env->CP0_Random);
  91     qemu_put_sbe32s(f, &env->CP0_VPEControl);
  92     qemu_put_sbe32s(f, &env->CP0_VPEConf0);
  93     qemu_put_sbe32s(f, &env->CP0_VPEConf1);
  94     qemu_put_betls(f, &env->CP0_YQMask);
  95     qemu_put_betls(f, &env->CP0_VPESchedule);
  96     qemu_put_betls(f, &env->CP0_VPEScheFBack);
  97     qemu_put_sbe32s(f, &env->CP0_VPEOpt);
  98     qemu_put_betls(f, &env->CP0_EntryLo0);
  99     qemu_put_betls(f, &env->CP0_EntryLo1);
 100     qemu_put_betls(f, &env->CP0_Context);
 101     qemu_put_sbe32s(f, &env->CP0_PageMask);
 102     qemu_put_sbe32s(f, &env->CP0_PageGrain);
 103     qemu_put_sbe32s(f, &env->CP0_Wired);
 104     qemu_put_sbe32s(f, &env->CP0_SRSConf0);
 105     qemu_put_sbe32s(f, &env->CP0_SRSConf1);
 106     qemu_put_sbe32s(f, &env->CP0_SRSConf2);
 107     qemu_put_sbe32s(f, &env->CP0_SRSConf3);
 108     qemu_put_sbe32s(f, &env->CP0_SRSConf4);
 109     qemu_put_sbe32s(f, &env->CP0_HWREna);
 110     qemu_put_betls(f, &env->CP0_BadVAddr);
 111     qemu_put_sbe32s(f, &env->CP0_Count);
 112     qemu_put_betls(f, &env->CP0_EntryHi);
 113     qemu_put_sbe32s(f, &env->CP0_Compare);
 114     qemu_put_sbe32s(f, &env->CP0_Status);
 115     qemu_put_sbe32s(f, &env->CP0_IntCtl);
 116     qemu_put_sbe32s(f, &env->CP0_SRSCtl);
 117     qemu_put_sbe32s(f, &env->CP0_SRSMap);
 118     qemu_put_sbe32s(f, &env->CP0_Cause);
 119     qemu_put_betls(f, &env->CP0_EPC);
 120     qemu_put_sbe32s(f, &env->CP0_PRid);
 121     qemu_put_sbe32s(f, &env->CP0_EBase);
 122     qemu_put_sbe32s(f, &env->CP0_Config0);
 123     qemu_put_sbe32s(f, &env->CP0_Config1);
 124     qemu_put_sbe32s(f, &env->CP0_Config2);
 125     qemu_put_sbe32s(f, &env->CP0_Config3);
 126     qemu_put_sbe32s(f, &env->CP0_Config6);
 127     qemu_put_sbe32s(f, &env->CP0_Config7);
 128     qemu_put_betls(f, &env->CP0_LLAddr);
 129     for(i = 0; i < 8; i++)
 130         qemu_put_betls(f, &env->CP0_WatchLo[i]);
 131     for(i = 0; i < 8; i++)
 132         qemu_put_sbe32s(f, &env->CP0_WatchHi[i]);
 133     qemu_put_betls(f, &env->CP0_XContext);
 134     qemu_put_sbe32s(f, &env->CP0_Framemask);
 135     qemu_put_sbe32s(f, &env->CP0_Debug);
 136     qemu_put_betls(f, &env->CP0_DEPC);
 137     qemu_put_sbe32s(f, &env->CP0_Performance0);
 138     qemu_put_sbe32s(f, &env->CP0_TagLo);
 139     qemu_put_sbe32s(f, &env->CP0_DataLo);
 140     qemu_put_sbe32s(f, &env->CP0_TagHi);
 141     qemu_put_sbe32s(f, &env->CP0_DataHi);
 142     qemu_put_betls(f, &env->CP0_ErrorEPC);
 143     qemu_put_sbe32s(f, &env->CP0_DESAVE);
 144
 145     /* Save inactive TC state */
 146     for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
 147         save_tc(f, &env->tcs[i]);
 148     for (i = 0; i < MIPS_FPU_MAX; i++)
 149         save_fpu(f, &env->fpus[i]);
 150 }
 151
 152 static void load_tc(QEMUFile *f, TCState *tc)
 153 {
 154     int i;
 155
 156     /* Save active TC */
 157     for(i = 0; i < 32; i++)
 158         qemu_get_betls(f, &tc->gpr[i]);
 159     qemu_get_betls(f, &tc->PC);
 160     for(i = 0; i < MIPS_DSP_ACC; i++)
 161         qemu_get_betls(f, &tc->HI[i]);
 162     for(i = 0; i < MIPS_DSP_ACC; i++)
 163         qemu_get_betls(f, &tc->LO[i]);
 164     for(i = 0; i < MIPS_DSP_ACC; i++)
 165         qemu_get_betls(f, &tc->ACX[i]);
 166     qemu_get_betls(f, &tc->DSPControl);
 167     qemu_get_sbe32s(f, &tc->CP0_TCStatus);
 168     qemu_get_sbe32s(f, &tc->CP0_TCBind);
 169     qemu_get_betls(f, &tc->CP0_TCHalt);
 170     qemu_get_betls(f, &tc->CP0_TCContext);
 171     qemu_get_betls(f, &tc->CP0_TCSchedule);
 172     qemu_get_betls(f, &tc->CP0_TCScheFBack);
 173     qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
 174 }
 175
 176 static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
 177 {
 178     int i;
 179
 180     for(i = 0; i < 32; i++)
 181         qemu_get_be64s(f, &fpu->fpr[i].d);
 182     qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess);
 183     qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode);
 184     qemu_get_s8s(f, &fpu->fp_status.float_exception_flags);
 185     qemu_get_be32s(f, &fpu->fcr0);
 186     qemu_get_be32s(f, &fpu->fcr31);
 187 }
 188
 189 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 190 {
 191     CPUState *env = opaque;
 192     int i;
 193
 194     if (version_id != 3)
 195         return -EINVAL;
 196
 197     /* Load active TC */
 198     load_tc(f, &env->active_tc);
 199
 200     /* Load active FPU */
 201     load_fpu(f, &env->active_fpu);
 202
 203     /* Load MVP */
 204     qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl);
 205     qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0);
 206     qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);
 207
 208     /* Load TLB */
 209     qemu_get_be32s(f, &env->tlb->nb_tlb);
 210     qemu_get_be32s(f, &env->tlb->tlb_in_use);
 211     for(i = 0; i < MIPS_TLB_MAX; i++) {
 212         uint16_t flags;
 213
 214         qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
 215         qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
 216         qemu_get_8s(f, &env->tlb->mmu.r4k.tlb[i].ASID);
 217         qemu_get_be16s(f, &flags);
 218         env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1;
 219         env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
 220         env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
 221         env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
 222         env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
 223         env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
 224         env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
 225         qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
 226         qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
 227     }
 228
 229     /* Load CPU metastate */
 230     qemu_get_be32s(f, &env->current_tc);
 231     qemu_get_be32s(f, &env->current_fpu);
 232     qemu_get_sbe32s(f, &env->error_code);
 233     qemu_get_be32s(f, &env->hflags);
 234     qemu_get_betls(f, &env->btarget);
 235     qemu_get_sbe32s(f, &i);
 236     env->bcond = i;
 237
 238     /* Load remaining CP1 registers */
 239     qemu_get_sbe32s(f, &env->CP0_Index);
 240     qemu_get_sbe32s(f, &env->CP0_Random);
 241     qemu_get_sbe32s(f, &env->CP0_VPEControl);
 242     qemu_get_sbe32s(f, &env->CP0_VPEConf0);
 243     qemu_get_sbe32s(f, &env->CP0_VPEConf1);
 244     qemu_get_betls(f, &env->CP0_YQMask);
 245     qemu_get_betls(f, &env->CP0_VPESchedule);
 246     qemu_get_betls(f, &env->CP0_VPEScheFBack);
 247     qemu_get_sbe32s(f, &env->CP0_VPEOpt);
 248     qemu_get_betls(f, &env->CP0_EntryLo0);
 249     qemu_get_betls(f, &env->CP0_EntryLo1);
 250     qemu_get_betls(f, &env->CP0_Context);
 251     qemu_get_sbe32s(f, &env->CP0_PageMask);
 252     qemu_get_sbe32s(f, &env->CP0_PageGrain);
 253     qemu_get_sbe32s(f, &env->CP0_Wired);
 254     qemu_get_sbe32s(f, &env->CP0_SRSConf0);
 255     qemu_get_sbe32s(f, &env->CP0_SRSConf1);
 256     qemu_get_sbe32s(f, &env->CP0_SRSConf2);
 257     qemu_get_sbe32s(f, &env->CP0_SRSConf3);
 258     qemu_get_sbe32s(f, &env->CP0_SRSConf4);
 259     qemu_get_sbe32s(f, &env->CP0_HWREna);
 260     qemu_get_betls(f, &env->CP0_BadVAddr);
 261     qemu_get_sbe32s(f, &env->CP0_Count);
 262     qemu_get_betls(f, &env->CP0_EntryHi);
 263     qemu_get_sbe32s(f, &env->CP0_Compare);
 264     qemu_get_sbe32s(f, &env->CP0_Status);
 265     qemu_get_sbe32s(f, &env->CP0_IntCtl);
 266     qemu_get_sbe32s(f, &env->CP0_SRSCtl);
 267     qemu_get_sbe32s(f, &env->CP0_SRSMap);
 268     qemu_get_sbe32s(f, &env->CP0_Cause);
 269     qemu_get_betls(f, &env->CP0_EPC);
 270     qemu_get_sbe32s(f, &env->CP0_PRid);
 271     qemu_get_sbe32s(f, &env->CP0_EBase);
 272     qemu_get_sbe32s(f, &env->CP0_Config0);
 273     qemu_get_sbe32s(f, &env->CP0_Config1);
 274     qemu_get_sbe32s(f, &env->CP0_Config2);
 275     qemu_get_sbe32s(f, &env->CP0_Config3);
 276     qemu_get_sbe32s(f, &env->CP0_Config6);
 277     qemu_get_sbe32s(f, &env->CP0_Config7);
 278     qemu_get_betls(f, &env->CP0_LLAddr);
 279     for(i = 0; i < 8; i++)
 280         qemu_get_betls(f, &env->CP0_WatchLo[i]);
 281     for(i = 0; i < 8; i++)
 282         qemu_get_sbe32s(f, &env->CP0_WatchHi[i]);
 283     qemu_get_betls(f, &env->CP0_XContext);
 284     qemu_get_sbe32s(f, &env->CP0_Framemask);
 285     qemu_get_sbe32s(f, &env->CP0_Debug);
 286     qemu_get_betls(f, &env->CP0_DEPC);
 287     qemu_get_sbe32s(f, &env->CP0_Performance0);
 288     qemu_get_sbe32s(f, &env->CP0_TagLo);
 289     qemu_get_sbe32s(f, &env->CP0_DataLo);
 290     qemu_get_sbe32s(f, &env->CP0_TagHi);
 291     qemu_get_sbe32s(f, &env->CP0_DataHi);
 292     qemu_get_betls(f, &env->CP0_ErrorEPC);
 293     qemu_get_sbe32s(f, &env->CP0_DESAVE);
 294
 295     /* Load inactive TC state */
 296     for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
 297         load_tc(f, &env->tcs[i]);
 298     for (i = 0; i < MIPS_FPU_MAX; i++)
 299         load_fpu(f, &env->fpus[i]);
 300
 301     /* XXX: ensure compatiblity for halted bit ? */
 302     tlb_flush(env, 1);
 303     return 0;
 304 }