hw/ppc4xx_devs.c

   1 /*
   2  * QEMU PowerPC 4xx embedded processors shared devices emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc4xx.h"
  27 #include "sysemu.h"
  28 #include "qemu-log.h"
  29
  30 //#define DEBUG_MMIO
  31 //#define DEBUG_UNASSIGNED
  32 #define DEBUG_UIC
  33
  34
  35 #ifdef DEBUG_UIC
  36 #  define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
  37 #else
  38 #  define LOG_UIC(...) do { } while (0)
  39 #endif
  40
  41 /*****************************************************************************/
  42 /* Generic PowerPC 4xx processor instanciation */
  43 CPUState *ppc4xx_init (const char *cpu_model,
  44                        clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
  45                        uint32_t sysclk)
  46 {
  47     CPUState *env;
  48
  49     /* init CPUs */
  50     env = cpu_init(cpu_model);
  51     if (!env) {
  52         fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
  53                 cpu_model);
  54         exit(1);
  55     }
  56     cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
  57     cpu_clk->opaque = env;
  58     /* Set time-base frequency to sysclk */
  59     tb_clk->cb = ppc_emb_timers_init(env, sysclk);
  60     tb_clk->opaque = env;
  61     ppc_dcr_init(env, NULL, NULL);
  62     /* Register qemu callbacks */
  63     qemu_register_reset(&cpu_ppc_reset, env);
  64
  65     return env;
  66 }
  67
  68 /*****************************************************************************/
  69 /* "Universal" Interrupt controller */
  70 enum {
  71     DCR_UICSR  = 0x000,
  72     DCR_UICSRS = 0x001,
  73     DCR_UICER  = 0x002,
  74     DCR_UICCR  = 0x003,
  75     DCR_UICPR  = 0x004,
  76     DCR_UICTR  = 0x005,
  77     DCR_UICMSR = 0x006,
  78     DCR_UICVR  = 0x007,
  79     DCR_UICVCR = 0x008,
  80     DCR_UICMAX = 0x009,
  81 };
  82
  83 #define UIC_MAX_IRQ 32
  84 typedef struct ppcuic_t ppcuic_t;
  85 struct ppcuic_t {
  86     uint32_t dcr_base;
  87     int use_vectors;
  88     uint32_t level;  /* Remembers the state of level-triggered interrupts. */
  89     uint32_t uicsr;  /* Status register */
  90     uint32_t uicer;  /* Enable register */
  91     uint32_t uiccr;  /* Critical register */
  92     uint32_t uicpr;  /* Polarity register */
  93     uint32_t uictr;  /* Triggering register */
  94     uint32_t uicvcr; /* Vector configuration register */
  95     uint32_t uicvr;
  96     qemu_irq *irqs;
  97 };
  98
  99 static void ppcuic_trigger_irq (ppcuic_t *uic)
 100 {
 101     uint32_t ir, cr;
 102     int start, end, inc, i;
 103
 104     /* Trigger interrupt if any is pending */
 105     ir = uic->uicsr & uic->uicer & (~uic->uiccr);
 106     cr = uic->uicsr & uic->uicer & uic->uiccr;
 107     LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
 108                 " uiccr %08" PRIx32 "\n"
 109                 "   %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
 110                 __func__, uic->uicsr, uic->uicer, uic->uiccr,
 111                 uic->uicsr & uic->uicer, ir, cr);
 112     if (ir != 0x0000000) {
 113         LOG_UIC("Raise UIC interrupt\n");
 114         qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
 115     } else {
 116         LOG_UIC("Lower UIC interrupt\n");
 117         qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
 118     }
 119     /* Trigger critical interrupt if any is pending and update vector */
 120     if (cr != 0x0000000) {
 121         qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
 122         if (uic->use_vectors) {
 123             /* Compute critical IRQ vector */
 124             if (uic->uicvcr & 1) {
 125                 start = 31;
 126                 end = 0;
 127                 inc = -1;
 128             } else {
 129                 start = 0;
 130                 end = 31;
 131                 inc = 1;
 132             }
 133             uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
 134             for (i = start; i <= end; i += inc) {
 135                 if (cr & (1 << i)) {
 136                     uic->uicvr += (i - start) * 512 * inc;
 137                     break;
 138                 }
 139             }
 140         }
 141         LOG_UIC("Raise UIC critical interrupt - "
 142                     "vector %08" PRIx32 "\n", uic->uicvr);
 143     } else {
 144         LOG_UIC("Lower UIC critical interrupt\n");
 145         qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
 146         uic->uicvr = 0x00000000;
 147     }
 148 }
 149
 150 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
 151 {
 152     ppcuic_t *uic;
 153     uint32_t mask, sr;
 154
 155     uic = opaque;
 156     mask = 1 << (31-irq_num);
 157     LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
 158                 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
 159                 __func__, irq_num, level,
 160                 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
 161     if (irq_num < 0 || irq_num > 31)
 162         return;
 163     sr = uic->uicsr;
 164
 165     /* Update status register */
 166     if (uic->uictr & mask) {
 167         /* Edge sensitive interrupt */
 168         if (level == 1)
 169             uic->uicsr |= mask;
 170     } else {
 171         /* Level sensitive interrupt */
 172         if (level == 1) {
 173             uic->uicsr |= mask;
 174             uic->level |= mask;
 175         } else {
 176             uic->uicsr &= ~mask;
 177             uic->level &= ~mask;
 178         }
 179     }
 180     LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
 181                 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
 182     if (sr != uic->uicsr)
 183         ppcuic_trigger_irq(uic);
 184 }
 185
 186 static target_ulong dcr_read_uic (void *opaque, int dcrn)
 187 {
 188     ppcuic_t *uic;
 189     target_ulong ret;
 190
 191     uic = opaque;
 192     dcrn -= uic->dcr_base;
 193     switch (dcrn) {
 194     case DCR_UICSR:
 195     case DCR_UICSRS:
 196         ret = uic->uicsr;
 197         break;
 198     case DCR_UICER:
 199         ret = uic->uicer;
 200         break;
 201     case DCR_UICCR:
 202         ret = uic->uiccr;
 203         break;
 204     case DCR_UICPR:
 205         ret = uic->uicpr;
 206         break;
 207     case DCR_UICTR:
 208         ret = uic->uictr;
 209         break;
 210     case DCR_UICMSR:
 211         ret = uic->uicsr & uic->uicer;
 212         break;
 213     case DCR_UICVR:
 214         if (!uic->use_vectors)
 215             goto no_read;
 216         ret = uic->uicvr;
 217         break;
 218     case DCR_UICVCR:
 219         if (!uic->use_vectors)
 220             goto no_read;
 221         ret = uic->uicvcr;
 222         break;
 223     default:
 224     no_read:
 225         ret = 0x00000000;
 226         break;
 227     }
 228
 229     return ret;
 230 }
 231
 232 static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
 233 {
 234     ppcuic_t *uic;
 235
 236     uic = opaque;
 237     dcrn -= uic->dcr_base;
 238     LOG_UIC("%s: dcr %d val " TARGET_FMT_lx "\n", __func__, dcrn, val);
 239     switch (dcrn) {
 240     case DCR_UICSR:
 241         uic->uicsr &= ~val;
 242         uic->uicsr |= uic->level;
 243         ppcuic_trigger_irq(uic);
 244         break;
 245     case DCR_UICSRS:
 246         uic->uicsr |= val;
 247         ppcuic_trigger_irq(uic);
 248         break;
 249     case DCR_UICER:
 250         uic->uicer = val;
 251         ppcuic_trigger_irq(uic);
 252         break;
 253     case DCR_UICCR:
 254         uic->uiccr = val;
 255         ppcuic_trigger_irq(uic);
 256         break;
 257     case DCR_UICPR:
 258         uic->uicpr = val;
 259         break;
 260     case DCR_UICTR:
 261         uic->uictr = val;
 262         ppcuic_trigger_irq(uic);
 263         break;
 264     case DCR_UICMSR:
 265         break;
 266     case DCR_UICVR:
 267         break;
 268     case DCR_UICVCR:
 269         uic->uicvcr = val & 0xFFFFFFFD;
 270         ppcuic_trigger_irq(uic);
 271         break;
 272     }
 273 }
 274
 275 static void ppcuic_reset (void *opaque)
 276 {
 277     ppcuic_t *uic;
 278
 279     uic = opaque;
 280     uic->uiccr = 0x00000000;
 281     uic->uicer = 0x00000000;
 282     uic->uicpr = 0x00000000;
 283     uic->uicsr = 0x00000000;
 284     uic->uictr = 0x00000000;
 285     if (uic->use_vectors) {
 286         uic->uicvcr = 0x00000000;
 287         uic->uicvr = 0x0000000;
 288     }
 289 }
 290
 291 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
 292                        uint32_t dcr_base, int has_ssr, int has_vr)
 293 {
 294     ppcuic_t *uic;
 295     int i;
 296
 297     uic = qemu_mallocz(sizeof(ppcuic_t));
 298     uic->dcr_base = dcr_base;
 299     uic->irqs = irqs;
 300     if (has_vr)
 301         uic->use_vectors = 1;
 302     for (i = 0; i < DCR_UICMAX; i++) {
 303         ppc_dcr_register(env, dcr_base + i, uic,
 304                          &dcr_read_uic, &dcr_write_uic);
 305     }
 306     qemu_register_reset(ppcuic_reset, uic);
 307     ppcuic_reset(uic);
 308
 309     return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
 310 }
 311
 312 /*****************************************************************************/
 313 /* SDRAM controller */
 314 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
 315 struct ppc4xx_sdram_t {
 316     uint32_t addr;
 317     int nbanks;
 318     target_phys_addr_t ram_bases[4];
 319     target_phys_addr_t ram_sizes[4];
 320     uint32_t besr0;
 321     uint32_t besr1;
 322     uint32_t bear;
 323     uint32_t cfg;
 324     uint32_t status;
 325     uint32_t rtr;
 326     uint32_t pmit;
 327     uint32_t bcr[4];
 328     uint32_t tr;
 329     uint32_t ecccfg;
 330     uint32_t eccesr;
 331     qemu_irq irq;
 332 };
 333
 334 enum {
 335     SDRAM0_CFGADDR = 0x010,
 336     SDRAM0_CFGDATA = 0x011,
 337 };
 338
 339 /* XXX: TOFIX: some patches have made this code become inconsistent:
 340  *      there are type inconsistencies, mixing target_phys_addr_t, target_ulong
 341  *      and uint32_t
 342  */
 343 static uint32_t sdram_bcr (target_phys_addr_t ram_base,
 344                            target_phys_addr_t ram_size)
 345 {
 346     uint32_t bcr;
 347
 348     switch (ram_size) {
 349     case (4 * 1024 * 1024):
 350         bcr = 0x00000000;
 351         break;
 352     case (8 * 1024 * 1024):
 353         bcr = 0x00020000;
 354         break;
 355     case (16 * 1024 * 1024):
 356         bcr = 0x00040000;
 357         break;
 358     case (32 * 1024 * 1024):
 359         bcr = 0x00060000;
 360         break;
 361     case (64 * 1024 * 1024):
 362         bcr = 0x00080000;
 363         break;
 364     case (128 * 1024 * 1024):
 365         bcr = 0x000A0000;
 366         break;
 367     case (256 * 1024 * 1024):
 368         bcr = 0x000C0000;
 369         break;
 370     default:
 371         printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
 372                ram_size);
 373         return 0x00000000;
 374     }
 375     bcr |= ram_base & 0xFF800000;
 376     bcr |= 1;
 377
 378     return bcr;
 379 }
 380
 381 static inline target_phys_addr_t sdram_base(uint32_t bcr)
 382 {
 383     return bcr & 0xFF800000;
 384 }
 385
 386 static target_ulong sdram_size (uint32_t bcr)
 387 {
 388     target_ulong size;
 389     int sh;
 390
 391     sh = (bcr >> 17) & 0x7;
 392     if (sh == 7)
 393         size = -1;
 394     else
 395         size = (4 * 1024 * 1024) << sh;
 396
 397     return size;
 398 }
 399
 400 static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
 401 {
 402     if (*bcrp & 0x00000001) {
 403         /* Unmap RAM */
 404 #ifdef DEBUG_SDRAM
 405         printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
 406                __func__, sdram_base(*bcrp), sdram_size(*bcrp));
 407 #endif
 408         cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
 409                                      IO_MEM_UNASSIGNED);
 410     }
 411     *bcrp = bcr & 0xFFDEE001;
 412     if (enabled && (bcr & 0x00000001)) {
 413 #ifdef DEBUG_SDRAM
 414         printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
 415                __func__, sdram_base(bcr), sdram_size(bcr));
 416 #endif
 417         cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
 418                                      sdram_base(bcr) | IO_MEM_RAM);
 419     }
 420 }
 421
 422 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
 423 {
 424     int i;
 425
 426     for (i = 0; i < sdram->nbanks; i++) {
 427         if (sdram->ram_sizes[i] != 0) {
 428             sdram_set_bcr(&sdram->bcr[i],
 429                           sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
 430                           1);
 431         } else {
 432             sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
 433         }
 434     }
 435 }
 436
 437 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
 438 {
 439     int i;
 440
 441     for (i = 0; i < sdram->nbanks; i++) {
 442 #ifdef DEBUG_SDRAM
 443         printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
 444                __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
 445 #endif
 446         cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
 447                                      sdram_size(sdram->bcr[i]),
 448                                      IO_MEM_UNASSIGNED);
 449     }
 450 }
 451
 452 static target_ulong dcr_read_sdram (void *opaque, int dcrn)
 453 {
 454     ppc4xx_sdram_t *sdram;
 455     target_ulong ret;
 456
 457     sdram = opaque;
 458     switch (dcrn) {
 459     case SDRAM0_CFGADDR:
 460         ret = sdram->addr;
 461         break;
 462     case SDRAM0_CFGDATA:
 463         switch (sdram->addr) {
 464         case 0x00: /* SDRAM_BESR0 */
 465             ret = sdram->besr0;
 466             break;
 467         case 0x08: /* SDRAM_BESR1 */
 468             ret = sdram->besr1;
 469             break;
 470         case 0x10: /* SDRAM_BEAR */
 471             ret = sdram->bear;
 472             break;
 473         case 0x20: /* SDRAM_CFG */
 474             ret = sdram->cfg;
 475             break;
 476         case 0x24: /* SDRAM_STATUS */
 477             ret = sdram->status;
 478             break;
 479         case 0x30: /* SDRAM_RTR */
 480             ret = sdram->rtr;
 481             break;
 482         case 0x34: /* SDRAM_PMIT */
 483             ret = sdram->pmit;
 484             break;
 485         case 0x40: /* SDRAM_B0CR */
 486             ret = sdram->bcr[0];
 487             break;
 488         case 0x44: /* SDRAM_B1CR */
 489             ret = sdram->bcr[1];
 490             break;
 491         case 0x48: /* SDRAM_B2CR */
 492             ret = sdram->bcr[2];
 493             break;
 494         case 0x4C: /* SDRAM_B3CR */
 495             ret = sdram->bcr[3];
 496             break;
 497         case 0x80: /* SDRAM_TR */
 498             ret = -1; /* ? */
 499             break;
 500         case 0x94: /* SDRAM_ECCCFG */
 501             ret = sdram->ecccfg;
 502             break;
 503         case 0x98: /* SDRAM_ECCESR */
 504             ret = sdram->eccesr;
 505             break;
 506         default: /* Error */
 507             ret = -1;
 508             break;
 509         }
 510         break;
 511     default:
 512         /* Avoid gcc warning */
 513         ret = 0x00000000;
 514         break;
 515     }
 516
 517     return ret;
 518 }
 519
 520 static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
 521 {
 522     ppc4xx_sdram_t *sdram;
 523
 524     sdram = opaque;
 525     switch (dcrn) {
 526     case SDRAM0_CFGADDR:
 527         sdram->addr = val;
 528         break;
 529     case SDRAM0_CFGDATA:
 530         switch (sdram->addr) {
 531         case 0x00: /* SDRAM_BESR0 */
 532             sdram->besr0 &= ~val;
 533             break;
 534         case 0x08: /* SDRAM_BESR1 */
 535             sdram->besr1 &= ~val;
 536             break;
 537         case 0x10: /* SDRAM_BEAR */
 538             sdram->bear = val;
 539             break;
 540         case 0x20: /* SDRAM_CFG */
 541             val &= 0xFFE00000;
 542             if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
 543 #ifdef DEBUG_SDRAM
 544                 printf("%s: enable SDRAM controller\n", __func__);
 545 #endif
 546                 /* validate all RAM mappings */
 547                 sdram_map_bcr(sdram);
 548                 sdram->status &= ~0x80000000;
 549             } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
 550 #ifdef DEBUG_SDRAM
 551                 printf("%s: disable SDRAM controller\n", __func__);
 552 #endif
 553                 /* invalidate all RAM mappings */
 554                 sdram_unmap_bcr(sdram);
 555                 sdram->status |= 0x80000000;
 556             }
 557             if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
 558                 sdram->status |= 0x40000000;
 559             else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
 560                 sdram->status &= ~0x40000000;
 561             sdram->cfg = val;
 562             break;
 563         case 0x24: /* SDRAM_STATUS */
 564             /* Read-only register */
 565             break;
 566         case 0x30: /* SDRAM_RTR */
 567             sdram->rtr = val & 0x3FF80000;
 568             break;
 569         case 0x34: /* SDRAM_PMIT */
 570             sdram->pmit = (val & 0xF8000000) | 0x07C00000;
 571             break;
 572         case 0x40: /* SDRAM_B0CR */
 573             sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
 574             break;
 575         case 0x44: /* SDRAM_B1CR */
 576             sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
 577             break;
 578         case 0x48: /* SDRAM_B2CR */
 579             sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
 580             break;
 581         case 0x4C: /* SDRAM_B3CR */
 582             sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
 583             break;
 584         case 0x80: /* SDRAM_TR */
 585             sdram->tr = val & 0x018FC01F;
 586             break;
 587         case 0x94: /* SDRAM_ECCCFG */
 588             sdram->ecccfg = val & 0x00F00000;
 589             break;
 590         case 0x98: /* SDRAM_ECCESR */
 591             val &= 0xFFF0F000;
 592             if (sdram->eccesr == 0 && val != 0)
 593                 qemu_irq_raise(sdram->irq);
 594             else if (sdram->eccesr != 0 && val == 0)
 595                 qemu_irq_lower(sdram->irq);
 596             sdram->eccesr = val;
 597             break;
 598         default: /* Error */
 599             break;
 600         }
 601         break;
 602     }
 603 }
 604
 605 static void sdram_reset (void *opaque)
 606 {
 607     ppc4xx_sdram_t *sdram;
 608
 609     sdram = opaque;
 610     sdram->addr = 0x00000000;
 611     sdram->bear = 0x00000000;
 612     sdram->besr0 = 0x00000000; /* No error */
 613     sdram->besr1 = 0x00000000; /* No error */
 614     sdram->cfg = 0x00000000;
 615     sdram->ecccfg = 0x00000000; /* No ECC */
 616     sdram->eccesr = 0x00000000; /* No error */
 617     sdram->pmit = 0x07C00000;
 618     sdram->rtr = 0x05F00000;
 619     sdram->tr = 0x00854009;
 620     /* We pre-initialize RAM banks */
 621     sdram->status = 0x00000000;
 622     sdram->cfg = 0x00800000;
 623     sdram_unmap_bcr(sdram);
 624 }
 625
 626 void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
 627                         target_phys_addr_t *ram_bases,
 628                         target_phys_addr_t *ram_sizes,
 629                         int do_init)
 630 {
 631     ppc4xx_sdram_t *sdram;
 632
 633     sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
 634     sdram->irq = irq;
 635     sdram->nbanks = nbanks;
 636     memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
 637     memcpy(sdram->ram_bases, ram_bases,
 638            nbanks * sizeof(target_phys_addr_t));
 639     memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
 640     memcpy(sdram->ram_sizes, ram_sizes,
 641            nbanks * sizeof(target_phys_addr_t));
 642     sdram_reset(sdram);
 643     qemu_register_reset(&sdram_reset, sdram);
 644     ppc_dcr_register(env, SDRAM0_CFGADDR,
 645                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 646     ppc_dcr_register(env, SDRAM0_CFGDATA,
 647                      sdram, &dcr_read_sdram, &dcr_write_sdram);
 648     if (do_init)
 649         sdram_map_bcr(sdram);
 650 }
 651
 652 /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
 653  *
 654  * sdram_bank_sizes[] must be 0-terminated.
 655  *
 656  * The 4xx SDRAM controller supports a small number of banks, and each bank
 657  * must be one of a small set of sizes. The number of banks and the supported
 658  * sizes varies by SoC. */
 659 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
 660                                target_phys_addr_t ram_bases[],
 661                                target_phys_addr_t ram_sizes[],
 662                                const unsigned int sdram_bank_sizes[])
 663 {
 664     ram_addr_t size_left = ram_size;
 665     int i;
 666     int j;
 667
 668     for (i = 0; i < nr_banks; i++) {
 669         for (j = 0; sdram_bank_sizes[j] != 0; j++) {
 670             unsigned int bank_size = sdram_bank_sizes[j];
 671
 672             if (bank_size <= size_left) {
 673                 ram_bases[i] = qemu_ram_alloc(bank_size);
 674                 ram_sizes[i] = bank_size;
 675                 size_left -= bank_size;
 676                 break;
 677             }
 678         }
 679
 680         if (!size_left) {
 681             /* No need to use the remaining banks. */
 682             break;
 683         }
 684     }
 685
 686     ram_size -= size_left;
 687     if (ram_size)
 688         printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
 689                (int)(ram_size >> 20));
 690
 691     return ram_size;
 692 }