hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31 #include "kvm.h"
  32
  33 /*
  34  * I440FX chipset data sheet.
  35  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  36  */
  37
  38 typedef PCIHostState I440FXState;
  39
  40 typedef struct PIIX3State {
  41     PCIDevice dev;
  42     int pci_irq_levels[4];
  43     qemu_irq *pic;
  44 } PIIX3State;
  45
  46 struct PCII440FXState {
  47     PCIDevice dev;
  48     target_phys_addr_t isa_page_descs[384 / 4];
  49     uint8_t smm_enabled;
  50     PIIX3State *piix3;
  51 };
  52
  53
  54 #define I440FX_PAM      0x59
  55 #define I440FX_PAM_SIZE 7
  56 #define I440FX_SMRAM    0x72
  57
  58 static void piix3_set_irq(void *opaque, int irq_num, int level);
  59
  60 /* return the global irq number corresponding to a given device irq
  61    pin. We could also use the bus number to have a more precise
  62    mapping. */
  63 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
  64 {
  65     int slot_addend;
  66     slot_addend = (pci_dev->devfn >> 3) - 1;
  67     return (irq_num + slot_addend) & 3;
  68 }
  69
  70 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
  71 {
  72     uint32_t addr;
  73
  74     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
  75     switch(r) {
  76     case 3:
  77         /* RAM */
  78         cpu_register_physical_memory(start, end - start,
  79                                      start);
  80         break;
  81     case 1:
  82         /* ROM (XXX: not quite correct) */
  83         cpu_register_physical_memory(start, end - start,
  84                                      start | IO_MEM_ROM);
  85         break;
  86     case 2:
  87     case 0:
  88         /* XXX: should distinguish read/write cases */
  89         for(addr = start; addr < end; addr += 4096) {
  90             cpu_register_physical_memory(addr, 4096,
  91                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
  92         }
  93         break;
  94     }
  95 }
  96
  97 static void i440fx_update_memory_mappings(PCII440FXState *d)
  98 {
  99     int i, r;
 100     uint32_t smram, addr;
 101
 102     if (kvm_enabled()) {
 103         /* FIXME: Support remappings and protection changes. */
 104         return;
 105     }
 106     update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
 107     for(i = 0; i < 12; i++) {
 108         r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
 109         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
 110     }
 111     smram = d->dev.config[I440FX_SMRAM];
 112     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 113         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
 114     } else {
 115         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 116             cpu_register_physical_memory(addr, 4096,
 117                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 118         }
 119     }
 120 }
 121
 122 static void i440fx_set_smm(int val, void *arg)
 123 {
 124     PCII440FXState *d = arg;
 125
 126     val = (val != 0);
 127     if (d->smm_enabled != val) {
 128         d->smm_enabled = val;
 129         i440fx_update_memory_mappings(d);
 130     }
 131 }
 132
 133
 134 /* XXX: suppress when better memory API. We make the assumption that
 135    no device (in particular the VGA) changes the memory mappings in
 136    the 0xa0000-0x100000 range */
 137 void i440fx_init_memory_mappings(PCII440FXState *d)
 138 {
 139     int i;
 140     for(i = 0; i < 96; i++) {
 141         d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 142     }
 143 }
 144
 145 static void i440fx_write_config(PCIDevice *dev,
 146                                 uint32_t address, uint32_t val, int len)
 147 {
 148     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 149
 150     /* XXX: implement SMRAM.D_LOCK */
 151     pci_default_write_config(dev, address, val, len);
 152     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 153         range_covers_byte(address, len, I440FX_SMRAM)) {
 154         i440fx_update_memory_mappings(d);
 155     }
 156 }
 157
 158 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 159 {
 160     PCII440FXState *d = opaque;
 161     int ret, i;
 162
 163     ret = pci_device_load(&d->dev, f);
 164     if (ret < 0)
 165         return ret;
 166     i440fx_update_memory_mappings(d);
 167     qemu_get_8s(f, &d->smm_enabled);
 168
 169     if (version_id == 2)
 170         for (i = 0; i < 4; i++)
 171             d->piix3->pci_irq_levels[i] = qemu_get_be32(f);
 172
 173     return 0;
 174 }
 175
 176 static int i440fx_post_load(void *opaque, int version_id)
 177 {
 178     PCII440FXState *d = opaque;
 179
 180     i440fx_update_memory_mappings(d);
 181     return 0;
 182 }
 183
 184 static const VMStateDescription vmstate_i440fx = {
 185     .name = "I440FX",
 186     .version_id = 3,
 187     .minimum_version_id = 3,
 188     .minimum_version_id_old = 1,
 189     .load_state_old = i440fx_load_old,
 190     .post_load = i440fx_post_load,
 191     .fields      = (VMStateField []) {
 192         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 193         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 194         VMSTATE_END_OF_LIST()
 195     }
 196 };
 197
 198 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 199 {
 200     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 201
 202     pci_host_conf_register_ioport(0xcf8, s);
 203
 204     pci_host_data_register_ioport(0xcfc, s);
 205     return 0;
 206 }
 207
 208 static int i440fx_initfn(PCIDevice *dev)
 209 {
 210     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 211
 212     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
 213     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
 214     d->dev.config[0x08] = 0x02; // revision
 215     pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
 216     d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 217
 218     d->dev.config[I440FX_SMRAM] = 0x02;
 219
 220     cpu_smm_register(&i440fx_set_smm, d);
 221     return 0;
 222 }
 223
 224 static PIIX3State *piix3_dev;
 225
 226 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic, ram_addr_t ram_size)
 227 {
 228     DeviceState *dev;
 229     PCIBus *b;
 230     PCIDevice *d;
 231     I440FXState *s;
 232     PIIX3State *piix3;
 233
 234     dev = qdev_create(NULL, "i440FX-pcihost");
 235     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 236     b = pci_bus_new(&s->busdev.qdev, NULL, 0);
 237     s->bus = b;
 238     qdev_init_nofail(dev);
 239
 240     d = pci_create_simple(b, 0, "i440FX");
 241     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 242
 243     piix3 = DO_UPCAST(PIIX3State, dev,
 244                                  pci_create_simple(b, -1, "PIIX3"));
 245     piix3->pic = pic;
 246     pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4);
 247     (*pi440fx_state)->piix3 = piix3;
 248
 249     *piix3_devfn = piix3->dev.devfn;
 250
 251     ram_size = ram_size / 8 / 1024 / 1024;
 252     if (ram_size > 255)
 253         ram_size = 255;
 254     (*pi440fx_state)->dev.config[0x57]=ram_size;
 255
 256     piix3_dev = piix3;
 257
 258     return b;
 259 }
 260
 261 /* PIIX3 PCI to ISA bridge */
 262
 263 static void piix3_set_irq(void *opaque, int irq_num, int level)
 264 {
 265     int i, pic_irq, pic_level;
 266     PIIX3State *piix3 = opaque;
 267
 268     piix3->pci_irq_levels[irq_num] = level;
 269
 270     /* now we change the pic irq level according to the piix irq mappings */
 271     /* XXX: optimize */
 272     pic_irq = piix3->dev.config[0x60 + irq_num];
 273     if (pic_irq < 16) {
 274         /* The pic level is the logical OR of all the PCI irqs mapped
 275            to it */
 276         pic_level = 0;
 277         for (i = 0; i < 4; i++) {
 278             if (pic_irq == piix3->dev.config[0x60 + i])
 279                 pic_level |= piix3->pci_irq_levels[i];
 280         }
 281         qemu_set_irq(piix3->pic[pic_irq], pic_level);
 282     }
 283 }
 284
 285 int piix_get_irq(int pin)
 286 {
 287     if (piix3_dev)
 288         return piix3_dev->dev.config[0x60+pin];
 289     return 0;
 290 }
 291
 292 static void piix3_reset(void *opaque)
 293 {
 294     PIIX3State *d = opaque;
 295     uint8_t *pci_conf = d->dev.config;
 296
 297     pci_conf[0x04] = 0x07; // master, memory and I/O
 298     pci_conf[0x05] = 0x00;
 299     pci_conf[0x06] = 0x00;
 300     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 301     pci_conf[0x4c] = 0x4d;
 302     pci_conf[0x4e] = 0x03;
 303     pci_conf[0x4f] = 0x00;
 304     pci_conf[0x60] = 0x80;
 305     pci_conf[0x61] = 0x80;
 306     pci_conf[0x62] = 0x80;
 307     pci_conf[0x63] = 0x80;
 308     pci_conf[0x69] = 0x02;
 309     pci_conf[0x70] = 0x80;
 310     pci_conf[0x76] = 0x0c;
 311     pci_conf[0x77] = 0x0c;
 312     pci_conf[0x78] = 0x02;
 313     pci_conf[0x79] = 0x00;
 314     pci_conf[0x80] = 0x00;
 315     pci_conf[0x82] = 0x00;
 316     pci_conf[0xa0] = 0x08;
 317     pci_conf[0xa2] = 0x00;
 318     pci_conf[0xa3] = 0x00;
 319     pci_conf[0xa4] = 0x00;
 320     pci_conf[0xa5] = 0x00;
 321     pci_conf[0xa6] = 0x00;
 322     pci_conf[0xa7] = 0x00;
 323     pci_conf[0xa8] = 0x0f;
 324     pci_conf[0xaa] = 0x00;
 325     pci_conf[0xab] = 0x00;
 326     pci_conf[0xac] = 0x00;
 327     pci_conf[0xae] = 0x00;
 328
 329     memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
 330 }
 331
 332 static const VMStateDescription vmstate_piix3 = {
 333     .name = "PIIX3",
 334     .version_id = 3,
 335     .minimum_version_id = 2,
 336     .minimum_version_id_old = 2,
 337     .fields      = (VMStateField []) {
 338         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 339         VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3),
 340         VMSTATE_END_OF_LIST()
 341     }
 342 };
 343
 344 static int piix3_initfn(PCIDevice *dev)
 345 {
 346     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 347     uint8_t *pci_conf;
 348
 349     isa_bus_new(&d->dev.qdev);
 350
 351     pci_conf = d->dev.config;
 352     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 353     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 354     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 355     pci_conf[PCI_HEADER_TYPE] =
 356         PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
 357
 358     qemu_register_reset(piix3_reset, d);
 359     return 0;
 360 }
 361
 362 static PCIDeviceInfo i440fx_info[] = {
 363     {
 364         .qdev.name    = "i440FX",
 365         .qdev.desc    = "Host bridge",
 366         .qdev.size    = sizeof(PCII440FXState),
 367         .qdev.vmsd    = &vmstate_i440fx,
 368         .qdev.no_user = 1,
 369         .init         = i440fx_initfn,
 370         .config_write = i440fx_write_config,
 371     },{
 372         .qdev.name    = "PIIX3",
 373         .qdev.desc    = "ISA bridge",
 374         .qdev.size    = sizeof(PIIX3State),
 375         .qdev.vmsd    = &vmstate_piix3,
 376         .qdev.no_user = 1,
 377         .init         = piix3_initfn,
 378     },{
 379         /* end of list */
 380     }
 381 };
 382
 383 static SysBusDeviceInfo i440fx_pcihost_info = {
 384     .init         = i440fx_pcihost_initfn,
 385     .qdev.name    = "i440FX-pcihost",
 386     .qdev.size    = sizeof(I440FXState),
 387     .qdev.no_user = 1,
 388 };
 389
 390 static void i440fx_register(void)
 391 {
 392     sysbus_register_withprop(&i440fx_pcihost_info);
 393     pci_qdev_register_many(i440fx_info);
 394 }
 395 device_init(i440fx_register);