target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27
  28 #ifdef KVM_UPSTREAM
  29
  30 #ifdef CONFIG_KVM_PARA
  31 #include <linux/kvm_para.h>
  32 #endif
  33 //
  34 //#define DEBUG_KVM
  35
  36 #ifdef DEBUG_KVM
  37 #define dprintf(fmt, ...) \
  38     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  39 #else
  40 #define dprintf(fmt, ...) \
  41     do { } while (0)
  42 #endif
  43
  44 #define MSR_KVM_WALL_CLOCK  0x11
  45 #define MSR_KVM_SYSTEM_TIME 0x12
  46
  47 #ifdef KVM_CAP_EXT_CPUID
  48
  49 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  50 {
  51     struct kvm_cpuid2 *cpuid;
  52     int r, size;
  53
  54     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  55     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  56     cpuid->nent = max;
  57     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  58     if (r == 0 && cpuid->nent >= max) {
  59         r = -E2BIG;
  60     }
  61     if (r < 0) {
  62         if (r == -E2BIG) {
  63             qemu_free(cpuid);
  64             return NULL;
  65         } else {
  66             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  67                     strerror(-r));
  68             exit(1);
  69         }
  70     }
  71     return cpuid;
  72 }
  73
  74 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  75 {
  76     struct kvm_cpuid2 *cpuid;
  77     int i, max;
  78     uint32_t ret = 0;
  79     uint32_t cpuid_1_edx;
  80
  81     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  82         return -1U;
  83     }
  84
  85     max = 1;
  86     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  87         max *= 2;
  88     }
  89
  90     for (i = 0; i < cpuid->nent; ++i) {
  91         if (cpuid->entries[i].function == function) {
  92             switch (reg) {
  93             case R_EAX:
  94                 ret = cpuid->entries[i].eax;
  95                 break;
  96             case R_EBX:
  97                 ret = cpuid->entries[i].ebx;
  98                 break;
  99             case R_ECX:
 100                 ret = cpuid->entries[i].ecx;
 101                 break;
 102             case R_EDX:
 103                 ret = cpuid->entries[i].edx;
 104                 switch (function) {
 105                 case 1:
 106                     /* KVM before 2.6.30 misreports the following features */
 107                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 108                     break;
 109                 case 0x80000001:
 110                     /* On Intel, kvm returns cpuid according to the Intel spec,
 111                      * so add missing bits according to the AMD spec:
 112                      */
 113                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
 114                     ret |= cpuid_1_edx & 0xdfeff7ff;
 115                     break;
 116                 }
 117                 break;
 118             }
 119         }
 120     }
 121
 122     qemu_free(cpuid);
 123
 124     return ret;
 125 }
 126
 127 #else
 128
 129 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 130 {
 131     return -1U;
 132 }
 133
 134 #endif
 135
 136 static void kvm_trim_features(uint32_t *features, uint32_t supported)
 137 {
 138     int i;
 139     uint32_t mask;
 140
 141     for (i = 0; i < 32; ++i) {
 142         mask = 1U << i;
 143         if ((*features & mask) && !(supported & mask)) {
 144             *features &= ~mask;
 145         }
 146     }
 147 }
 148
 149 #ifdef CONFIG_KVM_PARA
 150 struct kvm_para_features {
 151         int cap;
 152         int feature;
 153 } para_features[] = {
 154 #ifdef KVM_CAP_CLOCKSOURCE
 155         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 156 #endif
 157 #ifdef KVM_CAP_NOP_IO_DELAY
 158         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 159 #endif
 160 #ifdef KVM_CAP_PV_MMU
 161         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 162 #endif
 163         { -1, -1 }
 164 };
 165
 166 static int get_para_features(CPUState *env)
 167 {
 168         int i, features = 0;
 169
 170         for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 171                 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
 172                         features |= (1 << para_features[i].feature);
 173         }
 174
 175         return features;
 176 }
 177 #endif
 178
 179 int kvm_arch_init_vcpu(CPUState *env)
 180 {
 181     struct {
 182         struct kvm_cpuid2 cpuid;
 183         struct kvm_cpuid_entry2 entries[100];
 184     } __attribute__((packed)) cpuid_data;
 185     uint32_t limit, i, j, cpuid_i;
 186     uint32_t unused;
 187     struct kvm_cpuid_entry2 *c;
 188 #ifdef KVM_CPUID_SIGNATURE
 189     uint32_t signature[3];
 190 #endif
 191
 192     env->mp_state = KVM_MP_STATE_RUNNABLE;
 193
 194     kvm_trim_features(&env->cpuid_features,
 195         kvm_arch_get_supported_cpuid(env, 1, R_EDX));
 196
 197     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 198     kvm_trim_features(&env->cpuid_ext_features,
 199         kvm_arch_get_supported_cpuid(env, 1, R_ECX));
 200     env->cpuid_ext_features |= i;
 201
 202     kvm_trim_features(&env->cpuid_ext2_features,
 203         kvm_arch_get_supported_cpuid(env, 0x80000001, R_EDX));
 204     kvm_trim_features(&env->cpuid_ext3_features,
 205         kvm_arch_get_supported_cpuid(env, 0x80000001, R_ECX));
 206
 207     cpuid_i = 0;
 208
 209 #ifdef CONFIG_KVM_PARA
 210     /* Paravirtualization CPUIDs */
 211     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 212     c = &cpuid_data.entries[cpuid_i++];
 213     memset(c, 0, sizeof(*c));
 214     c->function = KVM_CPUID_SIGNATURE;
 215     c->eax = 0;
 216     c->ebx = signature[0];
 217     c->ecx = signature[1];
 218     c->edx = signature[2];
 219
 220     c = &cpuid_data.entries[cpuid_i++];
 221     memset(c, 0, sizeof(*c));
 222     c->function = KVM_CPUID_FEATURES;
 223     c->eax = env->cpuid_kvm_features & get_para_features(env);
 224 #endif
 225
 226     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 227
 228     for (i = 0; i <= limit; i++) {
 229         c = &cpuid_data.entries[cpuid_i++];
 230
 231         switch (i) {
 232         case 2: {
 233             /* Keep reading function 2 till all the input is received */
 234             int times;
 235
 236             c->function = i;
 237             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 238                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 239             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 240             times = c->eax & 0xff;
 241
 242             for (j = 1; j < times; ++j) {
 243                 c = &cpuid_data.entries[cpuid_i++];
 244                 c->function = i;
 245                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 246                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 247             }
 248             break;
 249         }
 250         case 4:
 251         case 0xb:
 252         case 0xd:
 253             for (j = 0; ; j++) {
 254                 c->function = i;
 255                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 256                 c->index = j;
 257                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 258
 259                 if (i == 4 && c->eax == 0)
 260                     break;
 261                 if (i == 0xb && !(c->ecx & 0xff00))
 262                     break;
 263                 if (i == 0xd && c->eax == 0)
 264                     break;
 265
 266                 c = &cpuid_data.entries[cpuid_i++];
 267             }
 268             break;
 269         default:
 270             c->function = i;
 271             c->flags = 0;
 272             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 273             break;
 274         }
 275     }
 276     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 277
 278     for (i = 0x80000000; i <= limit; i++) {
 279         c = &cpuid_data.entries[cpuid_i++];
 280
 281         c->function = i;
 282         c->flags = 0;
 283         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 284     }
 285
 286     cpuid_data.cpuid.nent = cpuid_i;
 287
 288     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 289 }
 290
 291 #endif
 292 void kvm_arch_reset_vcpu(CPUState *env)
 293 {
 294     env->exception_injected = -1;
 295     env->interrupt_injected = -1;
 296     env->nmi_injected = 0;
 297     env->nmi_pending = 0;
 298 }
 299 #ifdef KVM_UPSTREAM
 300
 301 static int kvm_has_msr_star(CPUState *env)
 302 {
 303     static int has_msr_star;
 304     int ret;
 305
 306     /* first time */
 307     if (has_msr_star == 0) {
 308         struct kvm_msr_list msr_list, *kvm_msr_list;
 309
 310         has_msr_star = -1;
 311
 312         /* Obtain MSR list from KVM.  These are the MSRs that we must
 313          * save/restore */
 314         msr_list.nmsrs = 0;
 315         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 316         if (ret < 0 && ret != -E2BIG) {
 317             return 0;
 318         }
 319         /* Old kernel modules had a bug and could write beyond the provided
 320            memory. Allocate at least a safe amount of 1K. */
 321         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 322                                               msr_list.nmsrs *
 323                                               sizeof(msr_list.indices[0])));
 324
 325         kvm_msr_list->nmsrs = msr_list.nmsrs;
 326         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 327         if (ret >= 0) {
 328             int i;
 329
 330             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 331                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 332                     has_msr_star = 1;
 333                     break;
 334                 }
 335             }
 336         }
 337
 338         free(kvm_msr_list);
 339     }
 340
 341     if (has_msr_star == 1)
 342         return 1;
 343     return 0;
 344 }
 345
 346 int kvm_arch_init(KVMState *s, int smp_cpus)
 347 {
 348     int ret;
 349
 350     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 351      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 352      * must be part of guest physical memory, we need to allocate it.  Older
 353      * versions of KVM just assumed that it would be at the end of physical
 354      * memory but that doesn't work with more than 4GB of memory.  We simply
 355      * refuse to work with those older versions of KVM. */
 356     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 357     if (ret <= 0) {
 358         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 359         return ret;
 360     }
 361
 362     /* this address is 3 pages before the bios, and the bios should present
 363      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 364      * this?
 365      */
 366     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 367 }
 368
 369 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 370 {
 371     lhs->selector = rhs->selector;
 372     lhs->base = rhs->base;
 373     lhs->limit = rhs->limit;
 374     lhs->type = 3;
 375     lhs->present = 1;
 376     lhs->dpl = 3;
 377     lhs->db = 0;
 378     lhs->s = 1;
 379     lhs->l = 0;
 380     lhs->g = 0;
 381     lhs->avl = 0;
 382     lhs->unusable = 0;
 383 }
 384
 385 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 386 {
 387     unsigned flags = rhs->flags;
 388     lhs->selector = rhs->selector;
 389     lhs->base = rhs->base;
 390     lhs->limit = rhs->limit;
 391     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 392     lhs->present = (flags & DESC_P_MASK) != 0;
 393     lhs->dpl = rhs->selector & 3;
 394     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 395     lhs->s = (flags & DESC_S_MASK) != 0;
 396     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 397     lhs->g = (flags & DESC_G_MASK) != 0;
 398     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 399     lhs->unusable = 0;
 400 }
 401
 402 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 403 {
 404     lhs->selector = rhs->selector;
 405     lhs->base = rhs->base;
 406     lhs->limit = rhs->limit;
 407     lhs->flags =
 408         (rhs->type << DESC_TYPE_SHIFT)
 409         | (rhs->present * DESC_P_MASK)
 410         | (rhs->dpl << DESC_DPL_SHIFT)
 411         | (rhs->db << DESC_B_SHIFT)
 412         | (rhs->s * DESC_S_MASK)
 413         | (rhs->l << DESC_L_SHIFT)
 414         | (rhs->g * DESC_G_MASK)
 415         | (rhs->avl * DESC_AVL_MASK);
 416 }
 417
 418 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 419 {
 420     if (set)
 421         *kvm_reg = *qemu_reg;
 422     else
 423         *qemu_reg = *kvm_reg;
 424 }
 425
 426 static int kvm_getput_regs(CPUState *env, int set)
 427 {
 428     struct kvm_regs regs;
 429     int ret = 0;
 430
 431     if (!set) {
 432         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 433         if (ret < 0)
 434             return ret;
 435     }
 436
 437     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 438     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 439     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 440     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 441     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 442     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 443     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 444     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 445 #ifdef TARGET_X86_64
 446     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 447     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 448     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 449     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 450     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 451     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 452     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 453     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 454 #endif
 455
 456     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 457     kvm_getput_reg(&regs.rip, &env->eip, set);
 458
 459     if (set)
 460         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 461
 462     return ret;
 463 }
 464
 465 static int kvm_put_fpu(CPUState *env)
 466 {
 467     struct kvm_fpu fpu;
 468     int i;
 469
 470     memset(&fpu, 0, sizeof fpu);
 471     fpu.fsw = env->fpus & ~(7 << 11);
 472     fpu.fsw |= (env->fpstt & 7) << 11;
 473     fpu.fcw = env->fpuc;
 474     for (i = 0; i < 8; ++i)
 475         fpu.ftwx |= (!env->fptags[i]) << i;
 476     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 477     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 478     fpu.mxcsr = env->mxcsr;
 479
 480     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 481 }
 482
 483 static int kvm_put_sregs(CPUState *env)
 484 {
 485     struct kvm_sregs sregs;
 486
 487     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 488     if (env->interrupt_injected >= 0) {
 489         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 490                 (uint64_t)1 << (env->interrupt_injected % 64);
 491     }
 492
 493     if ((env->eflags & VM_MASK)) {
 494             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 495             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 496             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 497             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 498             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 499             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 500     } else {
 501             set_seg(&sregs.cs, &env->segs[R_CS]);
 502             set_seg(&sregs.ds, &env->segs[R_DS]);
 503             set_seg(&sregs.es, &env->segs[R_ES]);
 504             set_seg(&sregs.fs, &env->segs[R_FS]);
 505             set_seg(&sregs.gs, &env->segs[R_GS]);
 506             set_seg(&sregs.ss, &env->segs[R_SS]);
 507
 508             if (env->cr[0] & CR0_PE_MASK) {
 509                 /* force ss cpl to cs cpl */
 510                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 511                         (sregs.cs.selector & 3);
 512                 sregs.ss.dpl = sregs.ss.selector & 3;
 513             }
 514     }
 515
 516     set_seg(&sregs.tr, &env->tr);
 517     set_seg(&sregs.ldt, &env->ldt);
 518
 519     sregs.idt.limit = env->idt.limit;
 520     sregs.idt.base = env->idt.base;
 521     sregs.gdt.limit = env->gdt.limit;
 522     sregs.gdt.base = env->gdt.base;
 523
 524     sregs.cr0 = env->cr[0];
 525     sregs.cr2 = env->cr[2];
 526     sregs.cr3 = env->cr[3];
 527     sregs.cr4 = env->cr[4];
 528
 529     sregs.cr8 = cpu_get_apic_tpr(env);
 530     sregs.apic_base = cpu_get_apic_base(env);
 531
 532     sregs.efer = env->efer;
 533
 534     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 535 }
 536
 537 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 538                               uint32_t index, uint64_t value)
 539 {
 540     entry->index = index;
 541     entry->data = value;
 542 }
 543
 544 static int kvm_put_msrs(CPUState *env)
 545 {
 546     struct {
 547         struct kvm_msrs info;
 548         struct kvm_msr_entry entries[100];
 549     } msr_data;
 550     struct kvm_msr_entry *msrs = msr_data.entries;
 551     int n = 0;
 552
 553     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 554     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 555     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 556     if (kvm_has_msr_star(env))
 557         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 558     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 559     kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 560 #ifdef TARGET_X86_64
 561     /* FIXME if lm capable */
 562     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 563     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 564     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 565     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 566 #endif
 567     kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,  env->system_time_msr);
 568     kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK,  env->wall_clock_msr);
 569
 570     msr_data.info.nmsrs = n;
 571
 572     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 573
 574 }
 575
 576
 577 static int kvm_get_fpu(CPUState *env)
 578 {
 579     struct kvm_fpu fpu;
 580     int i, ret;
 581
 582     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 583     if (ret < 0)
 584         return ret;
 585
 586     env->fpstt = (fpu.fsw >> 11) & 7;
 587     env->fpus = fpu.fsw;
 588     env->fpuc = fpu.fcw;
 589     for (i = 0; i < 8; ++i)
 590         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 591     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 592     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 593     env->mxcsr = fpu.mxcsr;
 594
 595     return 0;
 596 }
 597
 598 static int kvm_get_sregs(CPUState *env)
 599 {
 600     struct kvm_sregs sregs;
 601     uint32_t hflags;
 602     int bit, i, ret;
 603
 604     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 605     if (ret < 0)
 606         return ret;
 607
 608     /* There can only be one pending IRQ set in the bitmap at a time, so try
 609        to find it and save its number instead (-1 for none). */
 610     env->interrupt_injected = -1;
 611     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 612         if (sregs.interrupt_bitmap[i]) {
 613             bit = ctz64(sregs.interrupt_bitmap[i]);
 614             env->interrupt_injected = i * 64 + bit;
 615             break;
 616         }
 617     }
 618
 619     get_seg(&env->segs[R_CS], &sregs.cs);
 620     get_seg(&env->segs[R_DS], &sregs.ds);
 621     get_seg(&env->segs[R_ES], &sregs.es);
 622     get_seg(&env->segs[R_FS], &sregs.fs);
 623     get_seg(&env->segs[R_GS], &sregs.gs);
 624     get_seg(&env->segs[R_SS], &sregs.ss);
 625
 626     get_seg(&env->tr, &sregs.tr);
 627     get_seg(&env->ldt, &sregs.ldt);
 628
 629     env->idt.limit = sregs.idt.limit;
 630     env->idt.base = sregs.idt.base;
 631     env->gdt.limit = sregs.gdt.limit;
 632     env->gdt.base = sregs.gdt.base;
 633
 634     env->cr[0] = sregs.cr0;
 635     env->cr[2] = sregs.cr2;
 636     env->cr[3] = sregs.cr3;
 637     env->cr[4] = sregs.cr4;
 638
 639     cpu_set_apic_base(env, sregs.apic_base);
 640
 641     env->efer = sregs.efer;
 642     //cpu_set_apic_tpr(env, sregs.cr8);
 643
 644 #define HFLAG_COPY_MASK ~( \
 645                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 646                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 647                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 648                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 649
 650
 651
 652     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 653     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 654     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 655             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 656     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 657     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 658             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 659
 660     if (env->efer & MSR_EFER_LMA) {
 661         hflags |= HF_LMA_MASK;
 662     }
 663
 664     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 665         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 666     } else {
 667         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 668                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 669         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 670                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 671         if (!(env->cr[0] & CR0_PE_MASK) ||
 672                    (env->eflags & VM_MASK) ||
 673                    !(hflags & HF_CS32_MASK)) {
 674                 hflags |= HF_ADDSEG_MASK;
 675             } else {
 676                 hflags |= ((env->segs[R_DS].base |
 677                                 env->segs[R_ES].base |
 678                                 env->segs[R_SS].base) != 0) <<
 679                     HF_ADDSEG_SHIFT;
 680             }
 681     }
 682     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 683
 684     return 0;
 685 }
 686
 687 static int kvm_get_msrs(CPUState *env)
 688 {
 689     struct {
 690         struct kvm_msrs info;
 691         struct kvm_msr_entry entries[100];
 692     } msr_data;
 693     struct kvm_msr_entry *msrs = msr_data.entries;
 694     int ret, i, n;
 695
 696     n = 0;
 697     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 698     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 699     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 700     if (kvm_has_msr_star(env))
 701         msrs[n++].index = MSR_STAR;
 702     msrs[n++].index = MSR_IA32_TSC;
 703     msrs[n++].index = MSR_VM_HSAVE_PA;
 704 #ifdef TARGET_X86_64
 705     /* FIXME lm_capable_kernel */
 706     msrs[n++].index = MSR_CSTAR;
 707     msrs[n++].index = MSR_KERNELGSBASE;
 708     msrs[n++].index = MSR_FMASK;
 709     msrs[n++].index = MSR_LSTAR;
 710 #endif
 711     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
 712     msrs[n++].index = MSR_KVM_WALL_CLOCK;
 713
 714     msr_data.info.nmsrs = n;
 715     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 716     if (ret < 0)
 717         return ret;
 718
 719     for (i = 0; i < ret; i++) {
 720         switch (msrs[i].index) {
 721         case MSR_IA32_SYSENTER_CS:
 722             env->sysenter_cs = msrs[i].data;
 723             break;
 724         case MSR_IA32_SYSENTER_ESP:
 725             env->sysenter_esp = msrs[i].data;
 726             break;
 727         case MSR_IA32_SYSENTER_EIP:
 728             env->sysenter_eip = msrs[i].data;
 729             break;
 730         case MSR_STAR:
 731             env->star = msrs[i].data;
 732             break;
 733 #ifdef TARGET_X86_64
 734         case MSR_CSTAR:
 735             env->cstar = msrs[i].data;
 736             break;
 737         case MSR_KERNELGSBASE:
 738             env->kernelgsbase = msrs[i].data;
 739             break;
 740         case MSR_FMASK:
 741             env->fmask = msrs[i].data;
 742             break;
 743         case MSR_LSTAR:
 744             env->lstar = msrs[i].data;
 745             break;
 746 #endif
 747         case MSR_IA32_TSC:
 748             env->tsc = msrs[i].data;
 749             break;
 750         case MSR_KVM_SYSTEM_TIME:
 751             env->system_time_msr = msrs[i].data;
 752             break;
 753         case MSR_KVM_WALL_CLOCK:
 754             env->wall_clock_msr = msrs[i].data;
 755             break;
 756         case MSR_VM_HSAVE_PA:
 757             env->vm_hsave = msrs[i].data;
 758             break;
 759         }
 760     }
 761
 762     return 0;
 763 }
 764
 765 static int kvm_put_mp_state(CPUState *env)
 766 {
 767     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 768
 769     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
 770 }
 771
 772 static int kvm_get_mp_state(CPUState *env)
 773 {
 774     struct kvm_mp_state mp_state;
 775     int ret;
 776
 777     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
 778     if (ret < 0) {
 779         return ret;
 780     }
 781     env->mp_state = mp_state.mp_state;
 782     return 0;
 783 }
 784 #endif
 785
 786 int kvm_put_vcpu_events(CPUState *env)
 787 {
 788 #ifdef KVM_CAP_VCPU_EVENTS
 789     struct kvm_vcpu_events events;
 790
 791     if (!kvm_has_vcpu_events()) {
 792         return 0;
 793     }
 794
 795     events.exception.injected = (env->exception_injected >= 0);
 796     events.exception.nr = env->exception_injected;
 797     events.exception.has_error_code = env->has_error_code;
 798     events.exception.error_code = env->error_code;
 799
 800     events.interrupt.injected = (env->interrupt_injected >= 0);
 801     events.interrupt.nr = env->interrupt_injected;
 802     events.interrupt.soft = env->soft_interrupt;
 803
 804     events.nmi.injected = env->nmi_injected;
 805     events.nmi.pending = env->nmi_pending;
 806     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
 807
 808     events.sipi_vector = env->sipi_vector;
 809
 810     events.flags =
 811         KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
 812
 813     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
 814 #else
 815     return 0;
 816 #endif
 817 }
 818
 819 int kvm_get_vcpu_events(CPUState *env)
 820 {
 821 #ifdef KVM_CAP_VCPU_EVENTS
 822     struct kvm_vcpu_events events;
 823     int ret;
 824
 825     if (!kvm_has_vcpu_events()) {
 826         return 0;
 827     }
 828
 829     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
 830     if (ret < 0) {
 831        return ret;
 832     }
 833     env->exception_injected =
 834        events.exception.injected ? events.exception.nr : -1;
 835     env->has_error_code = events.exception.has_error_code;
 836     env->error_code = events.exception.error_code;
 837
 838     env->interrupt_injected =
 839         events.interrupt.injected ? events.interrupt.nr : -1;
 840     env->soft_interrupt = events.interrupt.soft;
 841
 842     env->nmi_injected = events.nmi.injected;
 843     env->nmi_pending = events.nmi.pending;
 844     if (events.nmi.masked) {
 845         env->hflags2 |= HF2_NMI_MASK;
 846     } else {
 847         env->hflags2 &= ~HF2_NMI_MASK;
 848     }
 849
 850     env->sipi_vector = events.sipi_vector;
 851 #endif
 852
 853     return 0;
 854 }
 855
 856 #ifdef KVM_UPSTREAM
 857 int kvm_arch_put_registers(CPUState *env)
 858 {
 859     int ret;
 860
 861     ret = kvm_getput_regs(env, 1);
 862     if (ret < 0)
 863         return ret;
 864
 865     ret = kvm_put_fpu(env);
 866     if (ret < 0)
 867         return ret;
 868
 869     ret = kvm_put_sregs(env);
 870     if (ret < 0)
 871         return ret;
 872
 873     ret = kvm_put_msrs(env);
 874     if (ret < 0)
 875         return ret;
 876
 877     ret = kvm_put_mp_state(env);
 878     if (ret < 0)
 879         return ret;
 880
 881     ret = kvm_put_vcpu_events(env);
 882     if (ret < 0)
 883         return ret;
 884
 885     return 0;
 886 }
 887
 888 int kvm_arch_get_registers(CPUState *env)
 889 {
 890     int ret;
 891
 892     ret = kvm_getput_regs(env, 0);
 893     if (ret < 0)
 894         return ret;
 895
 896     ret = kvm_get_fpu(env);
 897     if (ret < 0)
 898         return ret;
 899
 900     ret = kvm_get_sregs(env);
 901     if (ret < 0)
 902         return ret;
 903
 904     ret = kvm_get_msrs(env);
 905     if (ret < 0)
 906         return ret;
 907
 908     ret = kvm_get_mp_state(env);
 909     if (ret < 0)
 910         return ret;
 911
 912     ret = kvm_get_vcpu_events(env);
 913     if (ret < 0)
 914         return ret;
 915
 916     return 0;
 917 }
 918
 919 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 920 {
 921     /* Try to inject an interrupt if the guest can accept it */
 922     if (run->ready_for_interrupt_injection &&
 923         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 924         (env->eflags & IF_MASK)) {
 925         int irq;
 926
 927         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 928         irq = cpu_get_pic_interrupt(env);
 929         if (irq >= 0) {
 930             struct kvm_interrupt intr;
 931             intr.irq = irq;
 932             /* FIXME: errors */
 933             dprintf("injected interrupt %d\n", irq);
 934             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 935         }
 936     }
 937
 938     /* If we have an interrupt but the guest is not ready to receive an
 939      * interrupt, request an interrupt window exit.  This will
 940      * cause a return to userspace as soon as the guest is ready to
 941      * receive interrupts. */
 942     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 943         run->request_interrupt_window = 1;
 944     else
 945         run->request_interrupt_window = 0;
 946
 947     dprintf("setting tpr\n");
 948     run->cr8 = cpu_get_apic_tpr(env);
 949
 950     return 0;
 951 }
 952 #endif
 953
 954 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 955 {
 956     if (run->if_flag)
 957         env->eflags |= IF_MASK;
 958     else
 959         env->eflags &= ~IF_MASK;
 960
 961     cpu_set_apic_tpr(env, run->cr8);
 962     cpu_set_apic_base(env, run->apic_base);
 963
 964     return 0;
 965 }
 966
 967 #ifdef KVM_UPSTREAM
 968 static int kvm_handle_halt(CPUState *env)
 969 {
 970     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 971           (env->eflags & IF_MASK)) &&
 972         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 973         env->halted = 1;
 974         env->exception_index = EXCP_HLT;
 975         return 0;
 976     }
 977
 978     return 1;
 979 }
 980
 981 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 982 {
 983     int ret = 0;
 984
 985     switch (run->exit_reason) {
 986     case KVM_EXIT_HLT:
 987         dprintf("handle_hlt\n");
 988         ret = kvm_handle_halt(env);
 989         break;
 990     }
 991
 992     return ret;
 993 }
 994
 995 #ifdef KVM_CAP_SET_GUEST_DEBUG
 996 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 997 {
 998     static const uint8_t int3 = 0xcc;
 999
1000     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1001         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
1002         return -EINVAL;
1003     return 0;
1004 }
1005
1006 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1007 {
1008     uint8_t int3;
1009
1010     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1011         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1012         return -EINVAL;
1013     return 0;
1014 }
1015
1016 static struct {
1017     target_ulong addr;
1018     int len;
1019     int type;
1020 } hw_breakpoint[4];
1021
1022 static int nb_hw_breakpoint;
1023
1024 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1025 {
1026     int n;
1027
1028     for (n = 0; n < nb_hw_breakpoint; n++)
1029         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1030             (hw_breakpoint[n].len == len || len == -1))
1031             return n;
1032     return -1;
1033 }
1034
1035 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1036                                   target_ulong len, int type)
1037 {
1038     switch (type) {
1039     case GDB_BREAKPOINT_HW:
1040         len = 1;
1041         break;
1042     case GDB_WATCHPOINT_WRITE:
1043     case GDB_WATCHPOINT_ACCESS:
1044         switch (len) {
1045         case 1:
1046             break;
1047         case 2:
1048         case 4:
1049         case 8:
1050             if (addr & (len - 1))
1051                 return -EINVAL;
1052             break;
1053         default:
1054             return -EINVAL;
1055         }
1056         break;
1057     default:
1058         return -ENOSYS;
1059     }
1060
1061     if (nb_hw_breakpoint == 4)
1062         return -ENOBUFS;
1063
1064     if (find_hw_breakpoint(addr, len, type) >= 0)
1065         return -EEXIST;
1066
1067     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1068     hw_breakpoint[nb_hw_breakpoint].len = len;
1069     hw_breakpoint[nb_hw_breakpoint].type = type;
1070     nb_hw_breakpoint++;
1071
1072     return 0;
1073 }
1074
1075 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1076                                   target_ulong len, int type)
1077 {
1078     int n;
1079
1080     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1081     if (n < 0)
1082         return -ENOENT;
1083
1084     nb_hw_breakpoint--;
1085     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1086
1087     return 0;
1088 }
1089
1090 void kvm_arch_remove_all_hw_breakpoints(void)
1091 {
1092     nb_hw_breakpoint = 0;
1093 }
1094
1095 static CPUWatchpoint hw_watchpoint;
1096
1097 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1098 {
1099     int handle = 0;
1100     int n;
1101
1102     if (arch_info->exception == 1) {
1103         if (arch_info->dr6 & (1 << 14)) {
1104             if (cpu_single_env->singlestep_enabled)
1105                 handle = 1;
1106         } else {
1107             for (n = 0; n < 4; n++)
1108                 if (arch_info->dr6 & (1 << n))
1109                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1110                     case 0x0:
1111                         handle = 1;
1112                         break;
1113                     case 0x1:
1114                         handle = 1;
1115                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1116                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1117                         hw_watchpoint.flags = BP_MEM_WRITE;
1118                         break;
1119                     case 0x3:
1120                         handle = 1;
1121                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1122                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1123                         hw_watchpoint.flags = BP_MEM_ACCESS;
1124                         break;
1125                     }
1126         }
1127     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1128         handle = 1;
1129
1130     if (!handle)
1131         kvm_update_guest_debug(cpu_single_env,
1132                         (arch_info->exception == 1) ?
1133                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1134
1135     return handle;
1136 }
1137
1138 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1139 {
1140     const uint8_t type_code[] = {
1141         [GDB_BREAKPOINT_HW] = 0x0,
1142         [GDB_WATCHPOINT_WRITE] = 0x1,
1143         [GDB_WATCHPOINT_ACCESS] = 0x3
1144     };
1145     const uint8_t len_code[] = {
1146         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1147     };
1148     int n;
1149
1150     if (kvm_sw_breakpoints_active(env))
1151         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1152
1153     if (nb_hw_breakpoint > 0) {
1154         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1155         dbg->arch.debugreg[7] = 0x0600;
1156         for (n = 0; n < nb_hw_breakpoint; n++) {
1157             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1158             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1159                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1160                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1161         }
1162     }
1163 }
1164 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1165 #endif
1166
1167 #include "qemu-kvm-x86.c"