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Make --mem-path memory allocation depend on mmu notifiers
[qemu-kvm/amd-iommu.git] / hw / cirrus_vga.c
blob8b8783be7b883d4996fe135a1acccbb319145399
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #include "kvm.h"
35 #include "qemu-kvm.h"
36
37 /*
38 * TODO:
39 * - destination write mask support not complete (bits 5..7)
40 * - optimize linear mappings
41 * - optimize bitblt functions
42 */
43
44 //#define DEBUG_CIRRUS
45 //#define DEBUG_BITBLT
46
47 /***************************************
48 *
49 * definitions
50 *
51 ***************************************/
52
53 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
54
55 // ID
56 #define CIRRUS_ID_CLGD5422 (0x23<<2)
57 #define CIRRUS_ID_CLGD5426 (0x24<<2)
58 #define CIRRUS_ID_CLGD5424 (0x25<<2)
59 #define CIRRUS_ID_CLGD5428 (0x26<<2)
60 #define CIRRUS_ID_CLGD5430 (0x28<<2)
61 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
62 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
63 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
64
65 // sequencer 0x07
66 #define CIRRUS_SR7_BPP_VGA 0x00
67 #define CIRRUS_SR7_BPP_SVGA 0x01
68 #define CIRRUS_SR7_BPP_MASK 0x0e
69 #define CIRRUS_SR7_BPP_8 0x00
70 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
71 #define CIRRUS_SR7_BPP_24 0x04
72 #define CIRRUS_SR7_BPP_16 0x06
73 #define CIRRUS_SR7_BPP_32 0x08
74 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
75
76 // sequencer 0x0f
77 #define CIRRUS_MEMSIZE_512k 0x08
78 #define CIRRUS_MEMSIZE_1M 0x10
79 #define CIRRUS_MEMSIZE_2M 0x18
80 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
81
82 // sequencer 0x12
83 #define CIRRUS_CURSOR_SHOW 0x01
84 #define CIRRUS_CURSOR_HIDDENPEL 0x02
85 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
86
87 // sequencer 0x17
88 #define CIRRUS_BUSTYPE_VLBFAST 0x10
89 #define CIRRUS_BUSTYPE_PCI 0x20
90 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
91 #define CIRRUS_BUSTYPE_ISA 0x38
92 #define CIRRUS_MMIO_ENABLE 0x04
93 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
94 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
95
96 // control 0x0b
97 #define CIRRUS_BANKING_DUAL 0x01
98 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
99
100 // control 0x30
101 #define CIRRUS_BLTMODE_BACKWARDS 0x01
102 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
103 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
104 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
105 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
106 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
107 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
108 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
109 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
110 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
111 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
112
113 // control 0x31
114 #define CIRRUS_BLT_BUSY 0x01
115 #define CIRRUS_BLT_START 0x02
116 #define CIRRUS_BLT_RESET 0x04
117 #define CIRRUS_BLT_FIFOUSED 0x10
118 #define CIRRUS_BLT_AUTOSTART 0x80
119
120 // control 0x32
121 #define CIRRUS_ROP_0 0x00
122 #define CIRRUS_ROP_SRC_AND_DST 0x05
123 #define CIRRUS_ROP_NOP 0x06
124 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
125 #define CIRRUS_ROP_NOTDST 0x0b
126 #define CIRRUS_ROP_SRC 0x0d
127 #define CIRRUS_ROP_1 0x0e
128 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
129 #define CIRRUS_ROP_SRC_XOR_DST 0x59
130 #define CIRRUS_ROP_SRC_OR_DST 0x6d
131 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
132 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
133 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
134 #define CIRRUS_ROP_NOTSRC 0xd0
135 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
136 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
137
138 #define CIRRUS_ROP_NOP_INDEX 2
139 #define CIRRUS_ROP_SRC_INDEX 5
140
141 // control 0x33
142 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
143 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
144 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
145
146 // memory-mapped IO
147 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
148 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
149 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
150 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
151 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
152 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
153 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
154 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
155 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
156 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
157 #define CIRRUS_MMIO_BLTROP 0x1a // byte
158 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
161 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
162 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
169 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
170 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
171 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
172 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
173 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
174 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
175 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
176
177 // PCI 0x00: vendor, 0x02: device
178 #define PCI_VENDOR_CIRRUS 0x1013
179 #define PCI_DEVICE_CLGD5462 0x00d0
180 #define PCI_DEVICE_CLGD5465 0x00d6
181
182 // PCI 0x04: command(word), 0x06(word): status
183 #define PCI_COMMAND_IOACCESS 0x0001
184 #define PCI_COMMAND_MEMACCESS 0x0002
185 #define PCI_COMMAND_BUSMASTER 0x0004
186 #define PCI_COMMAND_SPECIALCYCLE 0x0008
187 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
188 #define PCI_COMMAND_PALETTESNOOPING 0x0020
189 #define PCI_COMMAND_PARITYDETECTION 0x0040
190 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
191 #define PCI_COMMAND_SERR 0x0100
192 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
193 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
194 #define PCI_CLASS_BASE_DISPLAY 0x03
195 // PCI 0x08, 0x00ff0000
196 #define PCI_CLASS_SUB_VGA 0x00
197 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
198 #define PCI_CLASS_HEADERTYPE_00h 0x00
199 // 0x10-0x3f (headertype 00h)
200 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
201 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
202 #define PCI_MAP_MEM 0x0
203 #define PCI_MAP_IO 0x1
204 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
205 #define PCI_MAP_IO_ADDR_MASK (~0x3)
206 #define PCI_MAP_MEMFLAGS_32BIT 0x0
207 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
208 #define PCI_MAP_MEMFLAGS_64BIT 0x4
209 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
210 // PCI 0x28: cardbus CIS pointer
211 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
212 // PCI 0x30: expansion ROM base address
213 #define PCI_ROMBIOS_ENABLED 0x1
214 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
215 // PCI 0x38: reserved
216 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
217
218 #define CIRRUS_PNPMMIO_SIZE 0x1000
219
220
221 /* I/O and memory hook */
222 #define CIRRUS_HOOK_NOT_HANDLED 0
223 #define CIRRUS_HOOK_HANDLED 1
224
225 #define ABS(a) ((signed)(a) > 0 ? a : -a)
226
227 #define BLTUNSAFE(s) \
228 ( \
229 ( /* check dst is within bounds */ \
230 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
231 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
232 (s)->vram_size \
233 ) || \
234 ( /* check src is within bounds */ \
235 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
236 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
237 (s)->vram_size \
238 ) \
239 )
240
241 struct CirrusVGAState;
242 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
243 uint8_t * dst, const uint8_t * src,
244 int dstpitch, int srcpitch,
245 int bltwidth, int bltheight);
246 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
247 uint8_t *dst, int dst_pitch, int width, int height);
248
249 typedef struct CirrusVGAState {
250 VGA_STATE_COMMON
251
252 int cirrus_linear_io_addr;
253 int cirrus_linear_bitblt_io_addr;
254 int cirrus_mmio_io_addr;
255 uint32_t cirrus_addr_mask;
256 uint32_t linear_mmio_mask;
257 uint8_t cirrus_shadow_gr0;
258 uint8_t cirrus_shadow_gr1;
259 uint8_t cirrus_hidden_dac_lockindex;
260 uint8_t cirrus_hidden_dac_data;
261 uint32_t cirrus_bank_base[2];
262 uint32_t cirrus_bank_limit[2];
263 uint8_t cirrus_hidden_palette[48];
264 uint32_t hw_cursor_x;
265 uint32_t hw_cursor_y;
266 int cirrus_blt_pixelwidth;
267 int cirrus_blt_width;
268 int cirrus_blt_height;
269 int cirrus_blt_dstpitch;
270 int cirrus_blt_srcpitch;
271 uint32_t cirrus_blt_fgcol;
272 uint32_t cirrus_blt_bgcol;
273 uint32_t cirrus_blt_dstaddr;
274 uint32_t cirrus_blt_srcaddr;
275 uint8_t cirrus_blt_mode;
276 uint8_t cirrus_blt_modeext;
277 cirrus_bitblt_rop_t cirrus_rop;
278 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
279 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
280 uint8_t *cirrus_srcptr;
281 uint8_t *cirrus_srcptr_end;
282 uint32_t cirrus_srccounter;
283 /* hwcursor display state */
284 int last_hw_cursor_size;
285 int last_hw_cursor_x;
286 int last_hw_cursor_y;
287 int last_hw_cursor_y_start;
288 int last_hw_cursor_y_end;
289 int real_vram_size; /* XXX: suppress that */
290 CPUWriteMemoryFunc **cirrus_linear_write;
291 int device_id;
292 int bustype;
293 } CirrusVGAState;
294
295 typedef struct PCICirrusVGAState {
296 PCIDevice dev;
297 CirrusVGAState cirrus_vga;
298 } PCICirrusVGAState;
299
300 static uint8_t rop_to_index[256];
301
302 /***************************************
303 *
304 * prototypes.
305 *
306 ***************************************/
307
308
309 static void cirrus_bitblt_reset(CirrusVGAState *s);
310 static void cirrus_update_memory_access(CirrusVGAState *s);
311
312 /***************************************
313 *
314 * raster operations
315 *
316 ***************************************/
317
318 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
319 uint8_t *dst,const uint8_t *src,
320 int dstpitch,int srcpitch,
321 int bltwidth,int bltheight)
322 {
323 }
324
325 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
326 uint8_t *dst,
327 int dstpitch, int bltwidth,int bltheight)
328 {
329 }
330
331 #define ROP_NAME 0
332 #define ROP_OP(d, s) d = 0
333 #include "cirrus_vga_rop.h"
334
335 #define ROP_NAME src_and_dst
336 #define ROP_OP(d, s) d = (s) & (d)
337 #include "cirrus_vga_rop.h"
338
339 #define ROP_NAME src_and_notdst
340 #define ROP_OP(d, s) d = (s) & (~(d))
341 #include "cirrus_vga_rop.h"
342
343 #define ROP_NAME notdst
344 #define ROP_OP(d, s) d = ~(d)
345 #include "cirrus_vga_rop.h"
346
347 #define ROP_NAME src
348 #define ROP_OP(d, s) d = s
349 #include "cirrus_vga_rop.h"
350
351 #define ROP_NAME 1
352 #define ROP_OP(d, s) d = ~0
353 #include "cirrus_vga_rop.h"
354
355 #define ROP_NAME notsrc_and_dst
356 #define ROP_OP(d, s) d = (~(s)) & (d)
357 #include "cirrus_vga_rop.h"
358
359 #define ROP_NAME src_xor_dst
360 #define ROP_OP(d, s) d = (s) ^ (d)
361 #include "cirrus_vga_rop.h"
362
363 #define ROP_NAME src_or_dst
364 #define ROP_OP(d, s) d = (s) | (d)
365 #include "cirrus_vga_rop.h"
366
367 #define ROP_NAME notsrc_or_notdst
368 #define ROP_OP(d, s) d = (~(s)) | (~(d))
369 #include "cirrus_vga_rop.h"
370
371 #define ROP_NAME src_notxor_dst
372 #define ROP_OP(d, s) d = ~((s) ^ (d))
373 #include "cirrus_vga_rop.h"
374
375 #define ROP_NAME src_or_notdst
376 #define ROP_OP(d, s) d = (s) | (~(d))
377 #include "cirrus_vga_rop.h"
378
379 #define ROP_NAME notsrc
380 #define ROP_OP(d, s) d = (~(s))
381 #include "cirrus_vga_rop.h"
382
383 #define ROP_NAME notsrc_or_dst
384 #define ROP_OP(d, s) d = (~(s)) | (d)
385 #include "cirrus_vga_rop.h"
386
387 #define ROP_NAME notsrc_and_notdst
388 #define ROP_OP(d, s) d = (~(s)) & (~(d))
389 #include "cirrus_vga_rop.h"
390
391 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
392 cirrus_bitblt_rop_fwd_0,
393 cirrus_bitblt_rop_fwd_src_and_dst,
394 cirrus_bitblt_rop_nop,
395 cirrus_bitblt_rop_fwd_src_and_notdst,
396 cirrus_bitblt_rop_fwd_notdst,
397 cirrus_bitblt_rop_fwd_src,
398 cirrus_bitblt_rop_fwd_1,
399 cirrus_bitblt_rop_fwd_notsrc_and_dst,
400 cirrus_bitblt_rop_fwd_src_xor_dst,
401 cirrus_bitblt_rop_fwd_src_or_dst,
402 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
403 cirrus_bitblt_rop_fwd_src_notxor_dst,
404 cirrus_bitblt_rop_fwd_src_or_notdst,
405 cirrus_bitblt_rop_fwd_notsrc,
406 cirrus_bitblt_rop_fwd_notsrc_or_dst,
407 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
408 };
409
410 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
411 cirrus_bitblt_rop_bkwd_0,
412 cirrus_bitblt_rop_bkwd_src_and_dst,
413 cirrus_bitblt_rop_nop,
414 cirrus_bitblt_rop_bkwd_src_and_notdst,
415 cirrus_bitblt_rop_bkwd_notdst,
416 cirrus_bitblt_rop_bkwd_src,
417 cirrus_bitblt_rop_bkwd_1,
418 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
419 cirrus_bitblt_rop_bkwd_src_xor_dst,
420 cirrus_bitblt_rop_bkwd_src_or_dst,
421 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
422 cirrus_bitblt_rop_bkwd_src_notxor_dst,
423 cirrus_bitblt_rop_bkwd_src_or_notdst,
424 cirrus_bitblt_rop_bkwd_notsrc,
425 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
426 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
427 };
428
429 #define TRANSP_ROP(name) {\
430 name ## _8,\
431 name ## _16,\
432 }
433 #define TRANSP_NOP(func) {\
434 func,\
435 func,\
436 }
437
438 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
441 TRANSP_NOP(cirrus_bitblt_rop_nop),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
454 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
455 };
456
457 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
460 TRANSP_NOP(cirrus_bitblt_rop_nop),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
473 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
474 };
475
476 #define ROP2(name) {\
477 name ## _8,\
478 name ## _16,\
479 name ## _24,\
480 name ## _32,\
481 }
482
483 #define ROP_NOP2(func) {\
484 func,\
485 func,\
486 func,\
487 func,\
488 }
489
490 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
491 ROP2(cirrus_patternfill_0),
492 ROP2(cirrus_patternfill_src_and_dst),
493 ROP_NOP2(cirrus_bitblt_rop_nop),
494 ROP2(cirrus_patternfill_src_and_notdst),
495 ROP2(cirrus_patternfill_notdst),
496 ROP2(cirrus_patternfill_src),
497 ROP2(cirrus_patternfill_1),
498 ROP2(cirrus_patternfill_notsrc_and_dst),
499 ROP2(cirrus_patternfill_src_xor_dst),
500 ROP2(cirrus_patternfill_src_or_dst),
501 ROP2(cirrus_patternfill_notsrc_or_notdst),
502 ROP2(cirrus_patternfill_src_notxor_dst),
503 ROP2(cirrus_patternfill_src_or_notdst),
504 ROP2(cirrus_patternfill_notsrc),
505 ROP2(cirrus_patternfill_notsrc_or_dst),
506 ROP2(cirrus_patternfill_notsrc_and_notdst),
507 };
508
509 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
510 ROP2(cirrus_colorexpand_transp_0),
511 ROP2(cirrus_colorexpand_transp_src_and_dst),
512 ROP_NOP2(cirrus_bitblt_rop_nop),
513 ROP2(cirrus_colorexpand_transp_src_and_notdst),
514 ROP2(cirrus_colorexpand_transp_notdst),
515 ROP2(cirrus_colorexpand_transp_src),
516 ROP2(cirrus_colorexpand_transp_1),
517 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
518 ROP2(cirrus_colorexpand_transp_src_xor_dst),
519 ROP2(cirrus_colorexpand_transp_src_or_dst),
520 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
521 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
522 ROP2(cirrus_colorexpand_transp_src_or_notdst),
523 ROP2(cirrus_colorexpand_transp_notsrc),
524 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
525 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
526 };
527
528 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
529 ROP2(cirrus_colorexpand_0),
530 ROP2(cirrus_colorexpand_src_and_dst),
531 ROP_NOP2(cirrus_bitblt_rop_nop),
532 ROP2(cirrus_colorexpand_src_and_notdst),
533 ROP2(cirrus_colorexpand_notdst),
534 ROP2(cirrus_colorexpand_src),
535 ROP2(cirrus_colorexpand_1),
536 ROP2(cirrus_colorexpand_notsrc_and_dst),
537 ROP2(cirrus_colorexpand_src_xor_dst),
538 ROP2(cirrus_colorexpand_src_or_dst),
539 ROP2(cirrus_colorexpand_notsrc_or_notdst),
540 ROP2(cirrus_colorexpand_src_notxor_dst),
541 ROP2(cirrus_colorexpand_src_or_notdst),
542 ROP2(cirrus_colorexpand_notsrc),
543 ROP2(cirrus_colorexpand_notsrc_or_dst),
544 ROP2(cirrus_colorexpand_notsrc_and_notdst),
545 };
546
547 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
548 ROP2(cirrus_colorexpand_pattern_transp_0),
549 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
550 ROP_NOP2(cirrus_bitblt_rop_nop),
551 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
552 ROP2(cirrus_colorexpand_pattern_transp_notdst),
553 ROP2(cirrus_colorexpand_pattern_transp_src),
554 ROP2(cirrus_colorexpand_pattern_transp_1),
555 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
556 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
557 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
558 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
559 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
560 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
561 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
562 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
563 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
564 };
565
566 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
567 ROP2(cirrus_colorexpand_pattern_0),
568 ROP2(cirrus_colorexpand_pattern_src_and_dst),
569 ROP_NOP2(cirrus_bitblt_rop_nop),
570 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
571 ROP2(cirrus_colorexpand_pattern_notdst),
572 ROP2(cirrus_colorexpand_pattern_src),
573 ROP2(cirrus_colorexpand_pattern_1),
574 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
575 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
576 ROP2(cirrus_colorexpand_pattern_src_or_dst),
577 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
578 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
579 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
580 ROP2(cirrus_colorexpand_pattern_notsrc),
581 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
582 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
583 };
584
585 static const cirrus_fill_t cirrus_fill[16][4] = {
586 ROP2(cirrus_fill_0),
587 ROP2(cirrus_fill_src_and_dst),
588 ROP_NOP2(cirrus_bitblt_fill_nop),
589 ROP2(cirrus_fill_src_and_notdst),
590 ROP2(cirrus_fill_notdst),
591 ROP2(cirrus_fill_src),
592 ROP2(cirrus_fill_1),
593 ROP2(cirrus_fill_notsrc_and_dst),
594 ROP2(cirrus_fill_src_xor_dst),
595 ROP2(cirrus_fill_src_or_dst),
596 ROP2(cirrus_fill_notsrc_or_notdst),
597 ROP2(cirrus_fill_src_notxor_dst),
598 ROP2(cirrus_fill_src_or_notdst),
599 ROP2(cirrus_fill_notsrc),
600 ROP2(cirrus_fill_notsrc_or_dst),
601 ROP2(cirrus_fill_notsrc_and_notdst),
602 };
603
604 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
605 {
606 unsigned int color;
607 switch (s->cirrus_blt_pixelwidth) {
608 case 1:
609 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
610 break;
611 case 2:
612 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
613 s->cirrus_blt_fgcol = le16_to_cpu(color);
614 break;
615 case 3:
616 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
617 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
618 break;
619 default:
620 case 4:
621 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
622 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
623 s->cirrus_blt_fgcol = le32_to_cpu(color);
624 break;
625 }
626 }
627
628 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
629 {
630 unsigned int color;
631 switch (s->cirrus_blt_pixelwidth) {
632 case 1:
633 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
634 break;
635 case 2:
636 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
637 s->cirrus_blt_bgcol = le16_to_cpu(color);
638 break;
639 case 3:
640 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
641 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
642 break;
643 default:
644 case 4:
645 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
646 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
647 s->cirrus_blt_bgcol = le32_to_cpu(color);
648 break;
649 }
650 }
651
652 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
653 int off_pitch, int bytesperline,
654 int lines)
655 {
656 int y;
657 int off_cur;
658 int off_cur_end;
659
660 for (y = 0; y < lines; y++) {
661 off_cur = off_begin;
662 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
663 off_cur &= TARGET_PAGE_MASK;
664 while (off_cur < off_cur_end) {
665 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
666 off_cur += TARGET_PAGE_SIZE;
667 }
668 off_begin += off_pitch;
669 }
670 }
671
672 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
673 const uint8_t * src)
674 {
675 uint8_t *dst;
676
677 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
678
679 if (BLTUNSAFE(s))
680 return 0;
681
682 (*s->cirrus_rop) (s, dst, src,
683 s->cirrus_blt_dstpitch, 0,
684 s->cirrus_blt_width, s->cirrus_blt_height);
685 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
686 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
687 s->cirrus_blt_height);
688 return 1;
689 }
690
691 /* fill */
692
693 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
694 {
695 cirrus_fill_t rop_func;
696
697 if (BLTUNSAFE(s))
698 return 0;
699 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
700 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
701 s->cirrus_blt_dstpitch,
702 s->cirrus_blt_width, s->cirrus_blt_height);
703 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
704 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
705 s->cirrus_blt_height);
706 cirrus_bitblt_reset(s);
707 return 1;
708 }
709
710 /***************************************
711 *
712 * bitblt (video-to-video)
713 *
714 ***************************************/
715
716 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
717 {
718 return cirrus_bitblt_common_patterncopy(s,
719 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
720 s->cirrus_addr_mask));
721 }
722
723 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
724 {
725 int sx, sy;
726 int dx, dy;
727 int width, height;
728 int depth;
729 int notify = 0;
730
731 depth = s->get_bpp((VGAState *)s) / 8;
732 s->get_resolution((VGAState *)s, &width, &height);
733
734 /* extra x, y */
735 sx = (src % (width * depth)) / depth;
736 sy = (src / (width * depth));
737 dx = (dst % (width *depth)) / depth;
738 dy = (dst / (width * depth));
739
740 /* normalize width */
741 w /= depth;
742
743 /* if we're doing a backward copy, we have to adjust
744 our x/y to be the upper left corner (instead of the lower
745 right corner) */
746 if (s->cirrus_blt_dstpitch < 0) {
747 sx -= (s->cirrus_blt_width / depth) - 1;
748 dx -= (s->cirrus_blt_width / depth) - 1;
749 sy -= s->cirrus_blt_height - 1;
750 dy -= s->cirrus_blt_height - 1;
751 }
752
753 /* are we in the visible portion of memory? */
754 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
755 (sx + w) <= width && (sy + h) <= height &&
756 (dx + w) <= width && (dy + h) <= height) {
757 notify = 1;
758 }
759
760 /* make to sure only copy if it's a plain copy ROP */
761 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
762 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
763 notify = 0;
764
765 /* we have to flush all pending changes so that the copy
766 is generated at the appropriate moment in time */
767 if (notify)
768 vga_hw_update();
769
770 (*s->cirrus_rop) (s, s->vram_ptr +
771 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
772 s->vram_ptr +
773 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
774 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
775 s->cirrus_blt_width, s->cirrus_blt_height);
776
777 if (notify)
778 qemu_console_copy(s->ds,
779 sx, sy, dx, dy,
780 s->cirrus_blt_width / depth,
781 s->cirrus_blt_height);
782
783 /* we don't have to notify the display that this portion has
784 changed since qemu_console_copy implies this */
785
786 if (!notify)
787 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
788 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
789 s->cirrus_blt_height);
790 }
791
792 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
793 {
794 if (BLTUNSAFE(s))
795 return 0;
796
797 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
798 s->cirrus_blt_srcaddr - s->start_addr,
799 s->cirrus_blt_width, s->cirrus_blt_height);
800
801 return 1;
802 }
803
804 /***************************************
805 *
806 * bitblt (cpu-to-video)
807 *
808 ***************************************/
809
810 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
811 {
812 int copy_count;
813 uint8_t *end_ptr;
814
815 if (s->cirrus_srccounter > 0) {
816 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
817 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
818 the_end:
819 s->cirrus_srccounter = 0;
820 cirrus_bitblt_reset(s);
821 } else {
822 /* at least one scan line */
823 do {
824 (*s->cirrus_rop)(s, s->vram_ptr +
825 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
826 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
827 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
828 s->cirrus_blt_width, 1);
829 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
830 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
831 if (s->cirrus_srccounter <= 0)
832 goto the_end;
833 /* more bytes than needed can be transfered because of
834 word alignment, so we keep them for the next line */
835 /* XXX: keep alignment to speed up transfer */
836 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
837 copy_count = s->cirrus_srcptr_end - end_ptr;
838 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
839 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
840 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
841 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
842 }
843 }
844 }
845
846 /***************************************
847 *
848 * bitblt wrapper
849 *
850 ***************************************/
851
852 static void cirrus_bitblt_reset(CirrusVGAState * s)
853 {
854 int need_update;
855
856 s->gr[0x31] &=
857 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
858 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
859 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
860 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
861 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
862 s->cirrus_srccounter = 0;
863 if (!need_update)
864 return;
865 cirrus_update_memory_access(s);
866 }
867
868 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
869 {
870 int w;
871
872 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
873 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
874 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
875
876 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
877 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
878 s->cirrus_blt_srcpitch = 8;
879 } else {
880 /* XXX: check for 24 bpp */
881 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
882 }
883 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
884 } else {
885 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
886 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
887 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
888 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
889 else
890 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
891 } else {
892 /* always align input size to 32 bits */
893 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
894 }
895 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
896 }
897 s->cirrus_srcptr = s->cirrus_bltbuf;
898 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
899 cirrus_update_memory_access(s);
900 return 1;
901 }
902
903 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
904 {
905 /* XXX */
906 #ifdef DEBUG_BITBLT
907 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
908 #endif
909 return 0;
910 }
911
912 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
913 {
914 int ret;
915
916 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
917 ret = cirrus_bitblt_videotovideo_patterncopy(s);
918 } else {
919 ret = cirrus_bitblt_videotovideo_copy(s);
920 }
921 if (ret)
922 cirrus_bitblt_reset(s);
923 return ret;
924 }
925
926 static void cirrus_bitblt_start(CirrusVGAState * s)
927 {
928 uint8_t blt_rop;
929
930 s->gr[0x31] |= CIRRUS_BLT_BUSY;
931
932 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
933 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
934 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
935 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
936 s->cirrus_blt_dstaddr =
937 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
938 s->cirrus_blt_srcaddr =
939 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
940 s->cirrus_blt_mode = s->gr[0x30];
941 s->cirrus_blt_modeext = s->gr[0x33];
942 blt_rop = s->gr[0x32];
943
944 #ifdef DEBUG_BITBLT
945 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
946 blt_rop,
947 s->cirrus_blt_mode,
948 s->cirrus_blt_modeext,
949 s->cirrus_blt_width,
950 s->cirrus_blt_height,
951 s->cirrus_blt_dstpitch,
952 s->cirrus_blt_srcpitch,
953 s->cirrus_blt_dstaddr,
954 s->cirrus_blt_srcaddr,
955 s->gr[0x2f]);
956 #endif
957
958 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
959 case CIRRUS_BLTMODE_PIXELWIDTH8:
960 s->cirrus_blt_pixelwidth = 1;
961 break;
962 case CIRRUS_BLTMODE_PIXELWIDTH16:
963 s->cirrus_blt_pixelwidth = 2;
964 break;
965 case CIRRUS_BLTMODE_PIXELWIDTH24:
966 s->cirrus_blt_pixelwidth = 3;
967 break;
968 case CIRRUS_BLTMODE_PIXELWIDTH32:
969 s->cirrus_blt_pixelwidth = 4;
970 break;
971 default:
972 #ifdef DEBUG_BITBLT
973 printf("cirrus: bitblt - pixel width is unknown\n");
974 #endif
975 goto bitblt_ignore;
976 }
977 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
978
979 if ((s->
980 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
981 CIRRUS_BLTMODE_MEMSYSDEST))
982 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
983 #ifdef DEBUG_BITBLT
984 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
985 #endif
986 goto bitblt_ignore;
987 }
988
989 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
990 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
991 CIRRUS_BLTMODE_TRANSPARENTCOMP |
992 CIRRUS_BLTMODE_PATTERNCOPY |
993 CIRRUS_BLTMODE_COLOREXPAND)) ==
994 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
995 cirrus_bitblt_fgcol(s);
996 cirrus_bitblt_solidfill(s, blt_rop);
997 } else {
998 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
999 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1000 CIRRUS_BLTMODE_COLOREXPAND) {
1001
1002 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1003 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1004 cirrus_bitblt_bgcol(s);
1005 else
1006 cirrus_bitblt_fgcol(s);
1007 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1008 } else {
1009 cirrus_bitblt_fgcol(s);
1010 cirrus_bitblt_bgcol(s);
1011 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1012 }
1013 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1014 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1015 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1016 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1017 cirrus_bitblt_bgcol(s);
1018 else
1019 cirrus_bitblt_fgcol(s);
1020 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1021 } else {
1022 cirrus_bitblt_fgcol(s);
1023 cirrus_bitblt_bgcol(s);
1024 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1025 }
1026 } else {
1027 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1028 }
1029 } else {
1030 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1031 if (s->cirrus_blt_pixelwidth > 2) {
1032 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1033 goto bitblt_ignore;
1034 }
1035 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1036 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1037 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1038 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1039 } else {
1040 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1041 }
1042 } else {
1043 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1044 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1045 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1046 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1047 } else {
1048 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1049 }
1050 }
1051 }
1052 // setup bitblt engine.
1053 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1054 if (!cirrus_bitblt_cputovideo(s))
1055 goto bitblt_ignore;
1056 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1057 if (!cirrus_bitblt_videotocpu(s))
1058 goto bitblt_ignore;
1059 } else {
1060 if (!cirrus_bitblt_videotovideo(s))
1061 goto bitblt_ignore;
1062 }
1063 }
1064 return;
1065 bitblt_ignore:;
1066 cirrus_bitblt_reset(s);
1067 }
1068
1069 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1070 {
1071 unsigned old_value;
1072
1073 old_value = s->gr[0x31];
1074 s->gr[0x31] = reg_value;
1075
1076 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1077 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1078 cirrus_bitblt_reset(s);
1079 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1080 ((reg_value & CIRRUS_BLT_START) != 0)) {
1081 cirrus_bitblt_start(s);
1082 }
1083 }
1084
1085
1086 /***************************************
1087 *
1088 * basic parameters
1089 *
1090 ***************************************/
1091
1092 static void cirrus_get_offsets(VGAState *s1,
1093 uint32_t *pline_offset,
1094 uint32_t *pstart_addr,
1095 uint32_t *pline_compare)
1096 {
1097 CirrusVGAState * s = (CirrusVGAState *)s1;
1098 uint32_t start_addr, line_offset, line_compare;
1099
1100 line_offset = s->cr[0x13]
1101 | ((s->cr[0x1b] & 0x10) << 4);
1102 line_offset <<= 3;
1103 *pline_offset = line_offset;
1104
1105 start_addr = (s->cr[0x0c] << 8)
1106 | s->cr[0x0d]
1107 | ((s->cr[0x1b] & 0x01) << 16)
1108 | ((s->cr[0x1b] & 0x0c) << 15)
1109 | ((s->cr[0x1d] & 0x80) << 12);
1110 *pstart_addr = start_addr;
1111
1112 line_compare = s->cr[0x18] |
1113 ((s->cr[0x07] & 0x10) << 4) |
1114 ((s->cr[0x09] & 0x40) << 3);
1115 *pline_compare = line_compare;
1116 }
1117
1118 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1119 {
1120 uint32_t ret = 16;
1121
1122 switch (s->cirrus_hidden_dac_data & 0xf) {
1123 case 0:
1124 ret = 15;
1125 break; /* Sierra HiColor */
1126 case 1:
1127 ret = 16;
1128 break; /* XGA HiColor */
1129 default:
1130 #ifdef DEBUG_CIRRUS
1131 printf("cirrus: invalid DAC value %x in 16bpp\n",
1132 (s->cirrus_hidden_dac_data & 0xf));
1133 #endif
1134 ret = 15; /* XXX */
1135 break;
1136 }
1137 return ret;
1138 }
1139
1140 static int cirrus_get_bpp(VGAState *s1)
1141 {
1142 CirrusVGAState * s = (CirrusVGAState *)s1;
1143 uint32_t ret = 8;
1144
1145 if ((s->sr[0x07] & 0x01) != 0) {
1146 /* Cirrus SVGA */
1147 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1148 case CIRRUS_SR7_BPP_8:
1149 ret = 8;
1150 break;
1151 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1152 ret = cirrus_get_bpp16_depth(s);
1153 break;
1154 case CIRRUS_SR7_BPP_24:
1155 ret = 24;
1156 break;
1157 case CIRRUS_SR7_BPP_16:
1158 ret = cirrus_get_bpp16_depth(s);
1159 break;
1160 case CIRRUS_SR7_BPP_32:
1161 ret = 32;
1162 break;
1163 default:
1164 #ifdef DEBUG_CIRRUS
1165 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1166 #endif
1167 ret = 8;
1168 break;
1169 }
1170 } else {
1171 /* VGA */
1172 ret = 0;
1173 }
1174
1175 return ret;
1176 }
1177
1178 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1179 {
1180 int width, height;
1181
1182 width = (s->cr[0x01] + 1) * 8;
1183 height = s->cr[0x12] |
1184 ((s->cr[0x07] & 0x02) << 7) |
1185 ((s->cr[0x07] & 0x40) << 3);
1186 height = (height + 1);
1187 /* interlace support */
1188 if (s->cr[0x1a] & 0x01)
1189 height = height * 2;
1190 *pwidth = width;
1191 *pheight = height;
1192 }
1193
1194 /***************************************
1195 *
1196 * bank memory
1197 *
1198 ***************************************/
1199
1200 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1201 {
1202 unsigned offset;
1203 unsigned limit;
1204
1205 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1206 offset = s->gr[0x09 + bank_index];
1207 else /* single bank */
1208 offset = s->gr[0x09];
1209
1210 if ((s->gr[0x0b] & 0x20) != 0)
1211 offset <<= 14;
1212 else
1213 offset <<= 12;
1214
1215 if (s->real_vram_size <= offset)
1216 limit = 0;
1217 else
1218 limit = s->real_vram_size - offset;
1219
1220 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1221 if (limit > 0x8000) {
1222 offset += 0x8000;
1223 limit -= 0x8000;
1224 } else {
1225 limit = 0;
1226 }
1227 }
1228
1229 if (limit > 0) {
1230 /* Thinking about changing bank base? First, drop the dirty bitmap information
1231 * on the current location, otherwise we lose this pointer forever */
1232 if (s->lfb_vram_mapped) {
1233 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1234 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1235 }
1236 s->cirrus_bank_base[bank_index] = offset;
1237 s->cirrus_bank_limit[bank_index] = limit;
1238 } else {
1239 s->cirrus_bank_base[bank_index] = 0;
1240 s->cirrus_bank_limit[bank_index] = 0;
1241 }
1242 }
1243
1244 /***************************************
1245 *
1246 * I/O access between 0x3c4-0x3c5
1247 *
1248 ***************************************/
1249
1250 static int
1251 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1252 {
1253 switch (reg_index) {
1254 case 0x00: // Standard VGA
1255 case 0x01: // Standard VGA
1256 case 0x02: // Standard VGA
1257 case 0x03: // Standard VGA
1258 case 0x04: // Standard VGA
1259 return CIRRUS_HOOK_NOT_HANDLED;
1260 case 0x06: // Unlock Cirrus extensions
1261 *reg_value = s->sr[reg_index];
1262 break;
1263 case 0x10:
1264 case 0x30:
1265 case 0x50:
1266 case 0x70: // Graphics Cursor X
1267 case 0x90:
1268 case 0xb0:
1269 case 0xd0:
1270 case 0xf0: // Graphics Cursor X
1271 *reg_value = s->sr[0x10];
1272 break;
1273 case 0x11:
1274 case 0x31:
1275 case 0x51:
1276 case 0x71: // Graphics Cursor Y
1277 case 0x91:
1278 case 0xb1:
1279 case 0xd1:
1280 case 0xf1: // Graphics Cursor Y
1281 *reg_value = s->sr[0x11];
1282 break;
1283 case 0x05: // ???
1284 case 0x07: // Extended Sequencer Mode
1285 case 0x08: // EEPROM Control
1286 case 0x09: // Scratch Register 0
1287 case 0x0a: // Scratch Register 1
1288 case 0x0b: // VCLK 0
1289 case 0x0c: // VCLK 1
1290 case 0x0d: // VCLK 2
1291 case 0x0e: // VCLK 3
1292 case 0x0f: // DRAM Control
1293 case 0x12: // Graphics Cursor Attribute
1294 case 0x13: // Graphics Cursor Pattern Address
1295 case 0x14: // Scratch Register 2
1296 case 0x15: // Scratch Register 3
1297 case 0x16: // Performance Tuning Register
1298 case 0x17: // Configuration Readback and Extended Control
1299 case 0x18: // Signature Generator Control
1300 case 0x19: // Signal Generator Result
1301 case 0x1a: // Signal Generator Result
1302 case 0x1b: // VCLK 0 Denominator & Post
1303 case 0x1c: // VCLK 1 Denominator & Post
1304 case 0x1d: // VCLK 2 Denominator & Post
1305 case 0x1e: // VCLK 3 Denominator & Post
1306 case 0x1f: // BIOS Write Enable and MCLK select
1307 #ifdef DEBUG_CIRRUS
1308 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1309 #endif
1310 *reg_value = s->sr[reg_index];
1311 break;
1312 default:
1313 #ifdef DEBUG_CIRRUS
1314 printf("cirrus: inport sr_index %02x\n", reg_index);
1315 #endif
1316 *reg_value = 0xff;
1317 break;
1318 }
1319
1320 return CIRRUS_HOOK_HANDLED;
1321 }
1322
1323 static int
1324 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1325 {
1326 switch (reg_index) {
1327 case 0x00: // Standard VGA
1328 case 0x01: // Standard VGA
1329 case 0x02: // Standard VGA
1330 case 0x03: // Standard VGA
1331 case 0x04: // Standard VGA
1332 return CIRRUS_HOOK_NOT_HANDLED;
1333 case 0x06: // Unlock Cirrus extensions
1334 reg_value &= 0x17;
1335 if (reg_value == 0x12) {
1336 s->sr[reg_index] = 0x12;
1337 } else {
1338 s->sr[reg_index] = 0x0f;
1339 }
1340 break;
1341 case 0x10:
1342 case 0x30:
1343 case 0x50:
1344 case 0x70: // Graphics Cursor X
1345 case 0x90:
1346 case 0xb0:
1347 case 0xd0:
1348 case 0xf0: // Graphics Cursor X
1349 s->sr[0x10] = reg_value;
1350 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1351 break;
1352 case 0x11:
1353 case 0x31:
1354 case 0x51:
1355 case 0x71: // Graphics Cursor Y
1356 case 0x91:
1357 case 0xb1:
1358 case 0xd1:
1359 case 0xf1: // Graphics Cursor Y
1360 s->sr[0x11] = reg_value;
1361 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1362 break;
1363 case 0x07: // Extended Sequencer Mode
1364 cirrus_update_memory_access(s);
1365 case 0x08: // EEPROM Control
1366 case 0x09: // Scratch Register 0
1367 case 0x0a: // Scratch Register 1
1368 case 0x0b: // VCLK 0
1369 case 0x0c: // VCLK 1
1370 case 0x0d: // VCLK 2
1371 case 0x0e: // VCLK 3
1372 case 0x0f: // DRAM Control
1373 case 0x12: // Graphics Cursor Attribute
1374 case 0x13: // Graphics Cursor Pattern Address
1375 case 0x14: // Scratch Register 2
1376 case 0x15: // Scratch Register 3
1377 case 0x16: // Performance Tuning Register
1378 case 0x18: // Signature Generator Control
1379 case 0x19: // Signature Generator Result
1380 case 0x1a: // Signature Generator Result
1381 case 0x1b: // VCLK 0 Denominator & Post
1382 case 0x1c: // VCLK 1 Denominator & Post
1383 case 0x1d: // VCLK 2 Denominator & Post
1384 case 0x1e: // VCLK 3 Denominator & Post
1385 case 0x1f: // BIOS Write Enable and MCLK select
1386 s->sr[reg_index] = reg_value;
1387 #ifdef DEBUG_CIRRUS
1388 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1389 reg_index, reg_value);
1390 #endif
1391 if (reg_index == 0x07)
1392 cirrus_update_memory_access(s);
1393 break;
1394 case 0x17: // Configuration Readback and Extended Control
1395 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1396 cirrus_update_memory_access(s);
1397 break;
1398 default:
1399 #ifdef DEBUG_CIRRUS
1400 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1401 reg_value);
1402 #endif
1403 break;
1404 }
1405
1406 return CIRRUS_HOOK_HANDLED;
1407 }
1408
1409 /***************************************
1410 *
1411 * I/O access at 0x3c6
1412 *
1413 ***************************************/
1414
1415 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1416 {
1417 *reg_value = 0xff;
1418 if (++s->cirrus_hidden_dac_lockindex == 5) {
1419 *reg_value = s->cirrus_hidden_dac_data;
1420 s->cirrus_hidden_dac_lockindex = 0;
1421 }
1422 }
1423
1424 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1425 {
1426 if (s->cirrus_hidden_dac_lockindex == 4) {
1427 s->cirrus_hidden_dac_data = reg_value;
1428 #if defined(DEBUG_CIRRUS)
1429 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1430 #endif
1431 }
1432 s->cirrus_hidden_dac_lockindex = 0;
1433 }
1434
1435 /***************************************
1436 *
1437 * I/O access at 0x3c9
1438 *
1439 ***************************************/
1440
1441 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1442 {
1443 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1444 return CIRRUS_HOOK_NOT_HANDLED;
1445 *reg_value =
1446 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1447 s->dac_sub_index];
1448 if (++s->dac_sub_index == 3) {
1449 s->dac_sub_index = 0;
1450 s->dac_read_index++;
1451 }
1452 return CIRRUS_HOOK_HANDLED;
1453 }
1454
1455 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1456 {
1457 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1458 return CIRRUS_HOOK_NOT_HANDLED;
1459 s->dac_cache[s->dac_sub_index] = reg_value;
1460 if (++s->dac_sub_index == 3) {
1461 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1462 s->dac_cache, 3);
1463 /* XXX update cursor */
1464 s->dac_sub_index = 0;
1465 s->dac_write_index++;
1466 }
1467 return CIRRUS_HOOK_HANDLED;
1468 }
1469
1470 /***************************************
1471 *
1472 * I/O access between 0x3ce-0x3cf
1473 *
1474 ***************************************/
1475
1476 static int
1477 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1478 {
1479 switch (reg_index) {
1480 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1481 *reg_value = s->cirrus_shadow_gr0;
1482 return CIRRUS_HOOK_HANDLED;
1483 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1484 *reg_value = s->cirrus_shadow_gr1;
1485 return CIRRUS_HOOK_HANDLED;
1486 case 0x02: // Standard VGA
1487 case 0x03: // Standard VGA
1488 case 0x04: // Standard VGA
1489 case 0x06: // Standard VGA
1490 case 0x07: // Standard VGA
1491 case 0x08: // Standard VGA
1492 return CIRRUS_HOOK_NOT_HANDLED;
1493 case 0x05: // Standard VGA, Cirrus extended mode
1494 default:
1495 break;
1496 }
1497
1498 if (reg_index < 0x3a) {
1499 *reg_value = s->gr[reg_index];
1500 } else {
1501 #ifdef DEBUG_CIRRUS
1502 printf("cirrus: inport gr_index %02x\n", reg_index);
1503 #endif
1504 *reg_value = 0xff;
1505 }
1506
1507 return CIRRUS_HOOK_HANDLED;
1508 }
1509
1510 static int
1511 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1512 {
1513 #if defined(DEBUG_BITBLT) && 0
1514 printf("gr%02x: %02x\n", reg_index, reg_value);
1515 #endif
1516 switch (reg_index) {
1517 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1518 s->cirrus_shadow_gr0 = reg_value;
1519 return CIRRUS_HOOK_NOT_HANDLED;
1520 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1521 s->cirrus_shadow_gr1 = reg_value;
1522 return CIRRUS_HOOK_NOT_HANDLED;
1523 case 0x02: // Standard VGA
1524 case 0x03: // Standard VGA
1525 case 0x04: // Standard VGA
1526 case 0x06: // Standard VGA
1527 case 0x07: // Standard VGA
1528 case 0x08: // Standard VGA
1529 return CIRRUS_HOOK_NOT_HANDLED;
1530 case 0x05: // Standard VGA, Cirrus extended mode
1531 s->gr[reg_index] = reg_value & 0x7f;
1532 cirrus_update_memory_access(s);
1533 break;
1534 case 0x09: // bank offset #0
1535 case 0x0A: // bank offset #1
1536 s->gr[reg_index] = reg_value;
1537 cirrus_update_bank_ptr(s, 0);
1538 cirrus_update_bank_ptr(s, 1);
1539 cirrus_update_memory_access(s);
1540 break;
1541 case 0x0B:
1542 s->gr[reg_index] = reg_value;
1543 cirrus_update_bank_ptr(s, 0);
1544 cirrus_update_bank_ptr(s, 1);
1545 cirrus_update_memory_access(s);
1546 break;
1547 case 0x10: // BGCOLOR 0x0000ff00
1548 case 0x11: // FGCOLOR 0x0000ff00
1549 case 0x12: // BGCOLOR 0x00ff0000
1550 case 0x13: // FGCOLOR 0x00ff0000
1551 case 0x14: // BGCOLOR 0xff000000
1552 case 0x15: // FGCOLOR 0xff000000
1553 case 0x20: // BLT WIDTH 0x0000ff
1554 case 0x22: // BLT HEIGHT 0x0000ff
1555 case 0x24: // BLT DEST PITCH 0x0000ff
1556 case 0x26: // BLT SRC PITCH 0x0000ff
1557 case 0x28: // BLT DEST ADDR 0x0000ff
1558 case 0x29: // BLT DEST ADDR 0x00ff00
1559 case 0x2c: // BLT SRC ADDR 0x0000ff
1560 case 0x2d: // BLT SRC ADDR 0x00ff00
1561 case 0x2f: // BLT WRITEMASK
1562 case 0x30: // BLT MODE
1563 case 0x32: // RASTER OP
1564 case 0x33: // BLT MODEEXT
1565 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1566 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1567 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1568 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1569 s->gr[reg_index] = reg_value;
1570 break;
1571 case 0x21: // BLT WIDTH 0x001f00
1572 case 0x23: // BLT HEIGHT 0x001f00
1573 case 0x25: // BLT DEST PITCH 0x001f00
1574 case 0x27: // BLT SRC PITCH 0x001f00
1575 s->gr[reg_index] = reg_value & 0x1f;
1576 break;
1577 case 0x2a: // BLT DEST ADDR 0x3f0000
1578 s->gr[reg_index] = reg_value & 0x3f;
1579 /* if auto start mode, starts bit blt now */
1580 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1581 cirrus_bitblt_start(s);
1582 }
1583 break;
1584 case 0x2e: // BLT SRC ADDR 0x3f0000
1585 s->gr[reg_index] = reg_value & 0x3f;
1586 break;
1587 case 0x31: // BLT STATUS/START
1588 cirrus_write_bitblt(s, reg_value);
1589 break;
1590 default:
1591 #ifdef DEBUG_CIRRUS
1592 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1593 reg_value);
1594 #endif
1595 break;
1596 }
1597
1598 return CIRRUS_HOOK_HANDLED;
1599 }
1600
1601 /***************************************
1602 *
1603 * I/O access between 0x3d4-0x3d5
1604 *
1605 ***************************************/
1606
1607 static int
1608 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1609 {
1610 switch (reg_index) {
1611 case 0x00: // Standard VGA
1612 case 0x01: // Standard VGA
1613 case 0x02: // Standard VGA
1614 case 0x03: // Standard VGA
1615 case 0x04: // Standard VGA
1616 case 0x05: // Standard VGA
1617 case 0x06: // Standard VGA
1618 case 0x07: // Standard VGA
1619 case 0x08: // Standard VGA
1620 case 0x09: // Standard VGA
1621 case 0x0a: // Standard VGA
1622 case 0x0b: // Standard VGA
1623 case 0x0c: // Standard VGA
1624 case 0x0d: // Standard VGA
1625 case 0x0e: // Standard VGA
1626 case 0x0f: // Standard VGA
1627 case 0x10: // Standard VGA
1628 case 0x11: // Standard VGA
1629 case 0x12: // Standard VGA
1630 case 0x13: // Standard VGA
1631 case 0x14: // Standard VGA
1632 case 0x15: // Standard VGA
1633 case 0x16: // Standard VGA
1634 case 0x17: // Standard VGA
1635 case 0x18: // Standard VGA
1636 return CIRRUS_HOOK_NOT_HANDLED;
1637 case 0x24: // Attribute Controller Toggle Readback (R)
1638 *reg_value = (s->ar_flip_flop << 7);
1639 break;
1640 case 0x19: // Interlace End
1641 case 0x1a: // Miscellaneous Control
1642 case 0x1b: // Extended Display Control
1643 case 0x1c: // Sync Adjust and Genlock
1644 case 0x1d: // Overlay Extended Control
1645 case 0x22: // Graphics Data Latches Readback (R)
1646 case 0x25: // Part Status
1647 case 0x27: // Part ID (R)
1648 *reg_value = s->cr[reg_index];
1649 break;
1650 case 0x26: // Attribute Controller Index Readback (R)
1651 *reg_value = s->ar_index & 0x3f;
1652 break;
1653 default:
1654 #ifdef DEBUG_CIRRUS
1655 printf("cirrus: inport cr_index %02x\n", reg_index);
1656 *reg_value = 0xff;
1657 #endif
1658 break;
1659 }
1660
1661 return CIRRUS_HOOK_HANDLED;
1662 }
1663
1664 static int
1665 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1666 {
1667 switch (reg_index) {
1668 case 0x00: // Standard VGA
1669 case 0x01: // Standard VGA
1670 case 0x02: // Standard VGA
1671 case 0x03: // Standard VGA
1672 case 0x04: // Standard VGA
1673 case 0x05: // Standard VGA
1674 case 0x06: // Standard VGA
1675 case 0x07: // Standard VGA
1676 case 0x08: // Standard VGA
1677 case 0x09: // Standard VGA
1678 case 0x0a: // Standard VGA
1679 case 0x0b: // Standard VGA
1680 case 0x0c: // Standard VGA
1681 case 0x0d: // Standard VGA
1682 case 0x0e: // Standard VGA
1683 case 0x0f: // Standard VGA
1684 case 0x10: // Standard VGA
1685 case 0x11: // Standard VGA
1686 case 0x12: // Standard VGA
1687 case 0x13: // Standard VGA
1688 case 0x14: // Standard VGA
1689 case 0x15: // Standard VGA
1690 case 0x16: // Standard VGA
1691 case 0x17: // Standard VGA
1692 case 0x18: // Standard VGA
1693 return CIRRUS_HOOK_NOT_HANDLED;
1694 case 0x19: // Interlace End
1695 case 0x1a: // Miscellaneous Control
1696 case 0x1b: // Extended Display Control
1697 case 0x1c: // Sync Adjust and Genlock
1698 case 0x1d: // Overlay Extended Control
1699 s->cr[reg_index] = reg_value;
1700 #ifdef DEBUG_CIRRUS
1701 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1702 reg_index, reg_value);
1703 #endif
1704 break;
1705 case 0x22: // Graphics Data Latches Readback (R)
1706 case 0x24: // Attribute Controller Toggle Readback (R)
1707 case 0x26: // Attribute Controller Index Readback (R)
1708 case 0x27: // Part ID (R)
1709 break;
1710 case 0x25: // Part Status
1711 default:
1712 #ifdef DEBUG_CIRRUS
1713 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1714 reg_value);
1715 #endif
1716 break;
1717 }
1718
1719 return CIRRUS_HOOK_HANDLED;
1720 }
1721
1722 /***************************************
1723 *
1724 * memory-mapped I/O (bitblt)
1725 *
1726 ***************************************/
1727
1728 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1729 {
1730 int value = 0xff;
1731
1732 switch (address) {
1733 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1734 cirrus_hook_read_gr(s, 0x00, &value);
1735 break;
1736 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1737 cirrus_hook_read_gr(s, 0x10, &value);
1738 break;
1739 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1740 cirrus_hook_read_gr(s, 0x12, &value);
1741 break;
1742 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1743 cirrus_hook_read_gr(s, 0x14, &value);
1744 break;
1745 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1746 cirrus_hook_read_gr(s, 0x01, &value);
1747 break;
1748 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1749 cirrus_hook_read_gr(s, 0x11, &value);
1750 break;
1751 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1752 cirrus_hook_read_gr(s, 0x13, &value);
1753 break;
1754 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1755 cirrus_hook_read_gr(s, 0x15, &value);
1756 break;
1757 case (CIRRUS_MMIO_BLTWIDTH + 0):
1758 cirrus_hook_read_gr(s, 0x20, &value);
1759 break;
1760 case (CIRRUS_MMIO_BLTWIDTH + 1):
1761 cirrus_hook_read_gr(s, 0x21, &value);
1762 break;
1763 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1764 cirrus_hook_read_gr(s, 0x22, &value);
1765 break;
1766 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1767 cirrus_hook_read_gr(s, 0x23, &value);
1768 break;
1769 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1770 cirrus_hook_read_gr(s, 0x24, &value);
1771 break;
1772 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1773 cirrus_hook_read_gr(s, 0x25, &value);
1774 break;
1775 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1776 cirrus_hook_read_gr(s, 0x26, &value);
1777 break;
1778 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1779 cirrus_hook_read_gr(s, 0x27, &value);
1780 break;
1781 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1782 cirrus_hook_read_gr(s, 0x28, &value);
1783 break;
1784 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1785 cirrus_hook_read_gr(s, 0x29, &value);
1786 break;
1787 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1788 cirrus_hook_read_gr(s, 0x2a, &value);
1789 break;
1790 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1791 cirrus_hook_read_gr(s, 0x2c, &value);
1792 break;
1793 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1794 cirrus_hook_read_gr(s, 0x2d, &value);
1795 break;
1796 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1797 cirrus_hook_read_gr(s, 0x2e, &value);
1798 break;
1799 case CIRRUS_MMIO_BLTWRITEMASK:
1800 cirrus_hook_read_gr(s, 0x2f, &value);
1801 break;
1802 case CIRRUS_MMIO_BLTMODE:
1803 cirrus_hook_read_gr(s, 0x30, &value);
1804 break;
1805 case CIRRUS_MMIO_BLTROP:
1806 cirrus_hook_read_gr(s, 0x32, &value);
1807 break;
1808 case CIRRUS_MMIO_BLTMODEEXT:
1809 cirrus_hook_read_gr(s, 0x33, &value);
1810 break;
1811 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1812 cirrus_hook_read_gr(s, 0x34, &value);
1813 break;
1814 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1815 cirrus_hook_read_gr(s, 0x35, &value);
1816 break;
1817 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1818 cirrus_hook_read_gr(s, 0x38, &value);
1819 break;
1820 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1821 cirrus_hook_read_gr(s, 0x39, &value);
1822 break;
1823 case CIRRUS_MMIO_BLTSTATUS:
1824 cirrus_hook_read_gr(s, 0x31, &value);
1825 break;
1826 default:
1827 #ifdef DEBUG_CIRRUS
1828 printf("cirrus: mmio read - address 0x%04x\n", address);
1829 #endif
1830 break;
1831 }
1832
1833 return (uint8_t) value;
1834 }
1835
1836 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1837 uint8_t value)
1838 {
1839 switch (address) {
1840 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1841 cirrus_hook_write_gr(s, 0x00, value);
1842 break;
1843 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1844 cirrus_hook_write_gr(s, 0x10, value);
1845 break;
1846 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1847 cirrus_hook_write_gr(s, 0x12, value);
1848 break;
1849 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1850 cirrus_hook_write_gr(s, 0x14, value);
1851 break;
1852 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1853 cirrus_hook_write_gr(s, 0x01, value);
1854 break;
1855 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1856 cirrus_hook_write_gr(s, 0x11, value);
1857 break;
1858 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1859 cirrus_hook_write_gr(s, 0x13, value);
1860 break;
1861 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1862 cirrus_hook_write_gr(s, 0x15, value);
1863 break;
1864 case (CIRRUS_MMIO_BLTWIDTH + 0):
1865 cirrus_hook_write_gr(s, 0x20, value);
1866 break;
1867 case (CIRRUS_MMIO_BLTWIDTH + 1):
1868 cirrus_hook_write_gr(s, 0x21, value);
1869 break;
1870 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1871 cirrus_hook_write_gr(s, 0x22, value);
1872 break;
1873 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1874 cirrus_hook_write_gr(s, 0x23, value);
1875 break;
1876 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1877 cirrus_hook_write_gr(s, 0x24, value);
1878 break;
1879 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1880 cirrus_hook_write_gr(s, 0x25, value);
1881 break;
1882 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1883 cirrus_hook_write_gr(s, 0x26, value);
1884 break;
1885 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1886 cirrus_hook_write_gr(s, 0x27, value);
1887 break;
1888 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1889 cirrus_hook_write_gr(s, 0x28, value);
1890 break;
1891 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1892 cirrus_hook_write_gr(s, 0x29, value);
1893 break;
1894 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1895 cirrus_hook_write_gr(s, 0x2a, value);
1896 break;
1897 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1898 /* ignored */
1899 break;
1900 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1901 cirrus_hook_write_gr(s, 0x2c, value);
1902 break;
1903 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1904 cirrus_hook_write_gr(s, 0x2d, value);
1905 break;
1906 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1907 cirrus_hook_write_gr(s, 0x2e, value);
1908 break;
1909 case CIRRUS_MMIO_BLTWRITEMASK:
1910 cirrus_hook_write_gr(s, 0x2f, value);
1911 break;
1912 case CIRRUS_MMIO_BLTMODE:
1913 cirrus_hook_write_gr(s, 0x30, value);
1914 break;
1915 case CIRRUS_MMIO_BLTROP:
1916 cirrus_hook_write_gr(s, 0x32, value);
1917 break;
1918 case CIRRUS_MMIO_BLTMODEEXT:
1919 cirrus_hook_write_gr(s, 0x33, value);
1920 break;
1921 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1922 cirrus_hook_write_gr(s, 0x34, value);
1923 break;
1924 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1925 cirrus_hook_write_gr(s, 0x35, value);
1926 break;
1927 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1928 cirrus_hook_write_gr(s, 0x38, value);
1929 break;
1930 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1931 cirrus_hook_write_gr(s, 0x39, value);
1932 break;
1933 case CIRRUS_MMIO_BLTSTATUS:
1934 cirrus_hook_write_gr(s, 0x31, value);
1935 break;
1936 default:
1937 #ifdef DEBUG_CIRRUS
1938 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1939 address, value);
1940 #endif
1941 break;
1942 }
1943 }
1944
1945 /***************************************
1946 *
1947 * write mode 4/5
1948 *
1949 * assume TARGET_PAGE_SIZE >= 16
1950 *
1951 ***************************************/
1952
1953 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1954 unsigned mode,
1955 unsigned offset,
1956 uint32_t mem_value)
1957 {
1958 int x;
1959 unsigned val = mem_value;
1960 uint8_t *dst;
1961
1962 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1963 for (x = 0; x < 8; x++) {
1964 if (val & 0x80) {
1965 *dst = s->cirrus_shadow_gr1;
1966 } else if (mode == 5) {
1967 *dst = s->cirrus_shadow_gr0;
1968 }
1969 val <<= 1;
1970 dst++;
1971 }
1972 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1973 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1974 }
1975
1976 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1977 unsigned mode,
1978 unsigned offset,
1979 uint32_t mem_value)
1980 {
1981 int x;
1982 unsigned val = mem_value;
1983 uint8_t *dst;
1984
1985 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1986 for (x = 0; x < 8; x++) {
1987 if (val & 0x80) {
1988 *dst = s->cirrus_shadow_gr1;
1989 *(dst + 1) = s->gr[0x11];
1990 } else if (mode == 5) {
1991 *dst = s->cirrus_shadow_gr0;
1992 *(dst + 1) = s->gr[0x10];
1993 }
1994 val <<= 1;
1995 dst += 2;
1996 }
1997 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1998 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1999 }
2000
2001 /***************************************
2002 *
2003 * memory access between 0xa0000-0xbffff
2004 *
2005 ***************************************/
2006
2007 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
2008 {
2009 CirrusVGAState *s = opaque;
2010 unsigned bank_index;
2011 unsigned bank_offset;
2012 uint32_t val;
2013
2014 if ((s->sr[0x07] & 0x01) == 0) {
2015 return vga_mem_readb(s, addr);
2016 }
2017
2018 addr &= 0x1ffff;
2019
2020 if (addr < 0x10000) {
2021 /* XXX handle bitblt */
2022 /* video memory */
2023 bank_index = addr >> 15;
2024 bank_offset = addr & 0x7fff;
2025 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2026 bank_offset += s->cirrus_bank_base[bank_index];
2027 if ((s->gr[0x0B] & 0x14) == 0x14) {
2028 bank_offset <<= 4;
2029 } else if (s->gr[0x0B] & 0x02) {
2030 bank_offset <<= 3;
2031 }
2032 bank_offset &= s->cirrus_addr_mask;
2033 val = *(s->vram_ptr + bank_offset);
2034 } else
2035 val = 0xff;
2036 } else if (addr >= 0x18000 && addr < 0x18100) {
2037 /* memory-mapped I/O */
2038 val = 0xff;
2039 if ((s->sr[0x17] & 0x44) == 0x04) {
2040 val = cirrus_mmio_blt_read(s, addr & 0xff);
2041 }
2042 } else {
2043 val = 0xff;
2044 #ifdef DEBUG_CIRRUS
2045 printf("cirrus: mem_readb %06x\n", addr);
2046 #endif
2047 }
2048 return val;
2049 }
2050
2051 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2052 {
2053 uint32_t v;
2054 #ifdef TARGET_WORDS_BIGENDIAN
2055 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2056 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2057 #else
2058 v = cirrus_vga_mem_readb(opaque, addr);
2059 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2060 #endif
2061 return v;
2062 }
2063
2064 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2065 {
2066 uint32_t v;
2067 #ifdef TARGET_WORDS_BIGENDIAN
2068 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2069 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2070 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2071 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2072 #else
2073 v = cirrus_vga_mem_readb(opaque, addr);
2074 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2075 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2076 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2077 #endif
2078 return v;
2079 }
2080
2081 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2082 uint32_t mem_value)
2083 {
2084 CirrusVGAState *s = opaque;
2085 unsigned bank_index;
2086 unsigned bank_offset;
2087 unsigned mode;
2088
2089 if ((s->sr[0x07] & 0x01) == 0) {
2090 vga_mem_writeb(s, addr, mem_value);
2091 return;
2092 }
2093
2094 addr &= 0x1ffff;
2095
2096 if (addr < 0x10000) {
2097 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2098 /* bitblt */
2099 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2100 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2101 cirrus_bitblt_cputovideo_next(s);
2102 }
2103 } else {
2104 /* video memory */
2105 bank_index = addr >> 15;
2106 bank_offset = addr & 0x7fff;
2107 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2108 bank_offset += s->cirrus_bank_base[bank_index];
2109 if ((s->gr[0x0B] & 0x14) == 0x14) {
2110 bank_offset <<= 4;
2111 } else if (s->gr[0x0B] & 0x02) {
2112 bank_offset <<= 3;
2113 }
2114 bank_offset &= s->cirrus_addr_mask;
2115 mode = s->gr[0x05] & 0x7;
2116 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2117 *(s->vram_ptr + bank_offset) = mem_value;
2118 cpu_physical_memory_set_dirty(s->vram_offset +
2119 bank_offset);
2120 } else {
2121 if ((s->gr[0x0B] & 0x14) != 0x14) {
2122 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2123 bank_offset,
2124 mem_value);
2125 } else {
2126 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2127 bank_offset,
2128 mem_value);
2129 }
2130 }
2131 }
2132 }
2133 } else if (addr >= 0x18000 && addr < 0x18100) {
2134 /* memory-mapped I/O */
2135 if ((s->sr[0x17] & 0x44) == 0x04) {
2136 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2137 }
2138 } else {
2139 #ifdef DEBUG_CIRRUS
2140 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2141 #endif
2142 }
2143 }
2144
2145 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2146 {
2147 #ifdef TARGET_WORDS_BIGENDIAN
2148 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2149 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2150 #else
2151 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2152 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2153 #endif
2154 }
2155
2156 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2157 {
2158 #ifdef TARGET_WORDS_BIGENDIAN
2159 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2160 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2161 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2162 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2163 #else
2164 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2165 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2166 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2167 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2168 #endif
2169 }
2170
2171 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2172 cirrus_vga_mem_readb,
2173 cirrus_vga_mem_readw,
2174 cirrus_vga_mem_readl,
2175 };
2176
2177 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2178 cirrus_vga_mem_writeb,
2179 cirrus_vga_mem_writew,
2180 cirrus_vga_mem_writel,
2181 };
2182
2183 /***************************************
2184 *
2185 * hardware cursor
2186 *
2187 ***************************************/
2188
2189 static inline void invalidate_cursor1(CirrusVGAState *s)
2190 {
2191 if (s->last_hw_cursor_size) {
2192 vga_invalidate_scanlines((VGAState *)s,
2193 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2194 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2195 }
2196 }
2197
2198 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2199 {
2200 const uint8_t *src;
2201 uint32_t content;
2202 int y, y_min, y_max;
2203
2204 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2205 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2206 src += (s->sr[0x13] & 0x3c) * 256;
2207 y_min = 64;
2208 y_max = -1;
2209 for(y = 0; y < 64; y++) {
2210 content = ((uint32_t *)src)[0] |
2211 ((uint32_t *)src)[1] |
2212 ((uint32_t *)src)[2] |
2213 ((uint32_t *)src)[3];
2214 if (content) {
2215 if (y < y_min)
2216 y_min = y;
2217 if (y > y_max)
2218 y_max = y;
2219 }
2220 src += 16;
2221 }
2222 } else {
2223 src += (s->sr[0x13] & 0x3f) * 256;
2224 y_min = 32;
2225 y_max = -1;
2226 for(y = 0; y < 32; y++) {
2227 content = ((uint32_t *)src)[0] |
2228 ((uint32_t *)(src + 128))[0];
2229 if (content) {
2230 if (y < y_min)
2231 y_min = y;
2232 if (y > y_max)
2233 y_max = y;
2234 }
2235 src += 4;
2236 }
2237 }
2238 if (y_min > y_max) {
2239 s->last_hw_cursor_y_start = 0;
2240 s->last_hw_cursor_y_end = 0;
2241 } else {
2242 s->last_hw_cursor_y_start = y_min;
2243 s->last_hw_cursor_y_end = y_max + 1;
2244 }
2245 }
2246
2247 /* NOTE: we do not currently handle the cursor bitmap change, so we
2248 update the cursor only if it moves. */
2249 static void cirrus_cursor_invalidate(VGAState *s1)
2250 {
2251 CirrusVGAState *s = (CirrusVGAState *)s1;
2252 int size;
2253
2254 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2255 size = 0;
2256 } else {
2257 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2258 size = 64;
2259 else
2260 size = 32;
2261 }
2262 /* invalidate last cursor and new cursor if any change */
2263 if (s->last_hw_cursor_size != size ||
2264 s->last_hw_cursor_x != s->hw_cursor_x ||
2265 s->last_hw_cursor_y != s->hw_cursor_y) {
2266
2267 invalidate_cursor1(s);
2268
2269 s->last_hw_cursor_size = size;
2270 s->last_hw_cursor_x = s->hw_cursor_x;
2271 s->last_hw_cursor_y = s->hw_cursor_y;
2272 /* compute the real cursor min and max y */
2273 cirrus_cursor_compute_yrange(s);
2274 invalidate_cursor1(s);
2275 }
2276 }
2277
2278 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2279 {
2280 CirrusVGAState *s = (CirrusVGAState *)s1;
2281 int w, h, bpp, x1, x2, poffset;
2282 unsigned int color0, color1;
2283 const uint8_t *palette, *src;
2284 uint32_t content;
2285
2286 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2287 return;
2288 /* fast test to see if the cursor intersects with the scan line */
2289 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2290 h = 64;
2291 } else {
2292 h = 32;
2293 }
2294 if (scr_y < s->hw_cursor_y ||
2295 scr_y >= (s->hw_cursor_y + h))
2296 return;
2297
2298 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2299 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2300 src += (s->sr[0x13] & 0x3c) * 256;
2301 src += (scr_y - s->hw_cursor_y) * 16;
2302 poffset = 8;
2303 content = ((uint32_t *)src)[0] |
2304 ((uint32_t *)src)[1] |
2305 ((uint32_t *)src)[2] |
2306 ((uint32_t *)src)[3];
2307 } else {
2308 src += (s->sr[0x13] & 0x3f) * 256;
2309 src += (scr_y - s->hw_cursor_y) * 4;
2310 poffset = 128;
2311 content = ((uint32_t *)src)[0] |
2312 ((uint32_t *)(src + 128))[0];
2313 }
2314 /* if nothing to draw, no need to continue */
2315 if (!content)
2316 return;
2317 w = h;
2318
2319 x1 = s->hw_cursor_x;
2320 if (x1 >= s->last_scr_width)
2321 return;
2322 x2 = s->hw_cursor_x + w;
2323 if (x2 > s->last_scr_width)
2324 x2 = s->last_scr_width;
2325 w = x2 - x1;
2326 palette = s->cirrus_hidden_palette;
2327 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2328 c6_to_8(palette[0x0 * 3 + 1]),
2329 c6_to_8(palette[0x0 * 3 + 2]));
2330 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2331 c6_to_8(palette[0xf * 3 + 1]),
2332 c6_to_8(palette[0xf * 3 + 2]));
2333 bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
2334 d1 += x1 * bpp;
2335 switch(ds_get_bits_per_pixel(s->ds)) {
2336 default:
2337 break;
2338 case 8:
2339 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2340 break;
2341 case 15:
2342 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2343 break;
2344 case 16:
2345 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2346 break;
2347 case 32:
2348 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2349 break;
2350 }
2351 }
2352
2353 /***************************************
2354 *
2355 * LFB memory access
2356 *
2357 ***************************************/
2358
2359 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2360 {
2361 CirrusVGAState *s = (CirrusVGAState *) opaque;
2362 uint32_t ret;
2363
2364 addr &= s->cirrus_addr_mask;
2365
2366 if (((s->sr[0x17] & 0x44) == 0x44) &&
2367 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2368 /* memory-mapped I/O */
2369 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2370 } else if (0) {
2371 /* XXX handle bitblt */
2372 ret = 0xff;
2373 } else {
2374 /* video memory */
2375 if ((s->gr[0x0B] & 0x14) == 0x14) {
2376 addr <<= 4;
2377 } else if (s->gr[0x0B] & 0x02) {
2378 addr <<= 3;
2379 }
2380 addr &= s->cirrus_addr_mask;
2381 ret = *(s->vram_ptr + addr);
2382 }
2383
2384 return ret;
2385 }
2386
2387 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2388 {
2389 uint32_t v;
2390 #ifdef TARGET_WORDS_BIGENDIAN
2391 v = cirrus_linear_readb(opaque, addr) << 8;
2392 v |= cirrus_linear_readb(opaque, addr + 1);
2393 #else
2394 v = cirrus_linear_readb(opaque, addr);
2395 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2396 #endif
2397 return v;
2398 }
2399
2400 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2401 {
2402 uint32_t v;
2403 #ifdef TARGET_WORDS_BIGENDIAN
2404 v = cirrus_linear_readb(opaque, addr) << 24;
2405 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2406 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2407 v |= cirrus_linear_readb(opaque, addr + 3);
2408 #else
2409 v = cirrus_linear_readb(opaque, addr);
2410 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2411 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2412 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2413 #endif
2414 return v;
2415 }
2416
2417 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2418 uint32_t val)
2419 {
2420 CirrusVGAState *s = (CirrusVGAState *) opaque;
2421 unsigned mode;
2422
2423 addr &= s->cirrus_addr_mask;
2424
2425 if (((s->sr[0x17] & 0x44) == 0x44) &&
2426 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2427 /* memory-mapped I/O */
2428 cirrus_mmio_blt_write(s, addr & 0xff, val);
2429 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2430 /* bitblt */
2431 *s->cirrus_srcptr++ = (uint8_t) val;
2432 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2433 cirrus_bitblt_cputovideo_next(s);
2434 }
2435 } else {
2436 /* video memory */
2437 if ((s->gr[0x0B] & 0x14) == 0x14) {
2438 addr <<= 4;
2439 } else if (s->gr[0x0B] & 0x02) {
2440 addr <<= 3;
2441 }
2442 addr &= s->cirrus_addr_mask;
2443
2444 mode = s->gr[0x05] & 0x7;
2445 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2446 *(s->vram_ptr + addr) = (uint8_t) val;
2447 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2448 } else {
2449 if ((s->gr[0x0B] & 0x14) != 0x14) {
2450 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2451 } else {
2452 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2453 }
2454 }
2455 }
2456 }
2457
2458 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2459 uint32_t val)
2460 {
2461 #ifdef TARGET_WORDS_BIGENDIAN
2462 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2463 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2464 #else
2465 cirrus_linear_writeb(opaque, addr, val & 0xff);
2466 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2467 #endif
2468 }
2469
2470 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2471 uint32_t val)
2472 {
2473 #ifdef TARGET_WORDS_BIGENDIAN
2474 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2475 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2476 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2477 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2478 #else
2479 cirrus_linear_writeb(opaque, addr, val & 0xff);
2480 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2481 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2482 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2483 #endif
2484 }
2485
2486
2487 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2488 cirrus_linear_readb,
2489 cirrus_linear_readw,
2490 cirrus_linear_readl,
2491 };
2492
2493 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2494 cirrus_linear_writeb,
2495 cirrus_linear_writew,
2496 cirrus_linear_writel,
2497 };
2498
2499 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2500 uint32_t val)
2501 {
2502 CirrusVGAState *s = (CirrusVGAState *) opaque;
2503
2504 addr &= s->cirrus_addr_mask;
2505 *(s->vram_ptr + addr) = val;
2506 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2507 }
2508
2509 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2510 uint32_t val)
2511 {
2512 CirrusVGAState *s = (CirrusVGAState *) opaque;
2513
2514 addr &= s->cirrus_addr_mask;
2515 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2516 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2517 }
2518
2519 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2520 uint32_t val)
2521 {
2522 CirrusVGAState *s = (CirrusVGAState *) opaque;
2523
2524 addr &= s->cirrus_addr_mask;
2525 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2526 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2527 }
2528
2529 /***************************************
2530 *
2531 * system to screen memory access
2532 *
2533 ***************************************/
2534
2535
2536 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2537 {
2538 uint32_t ret;
2539
2540 /* XXX handle bitblt */
2541 ret = 0xff;
2542 return ret;
2543 }
2544
2545 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2546 {
2547 uint32_t v;
2548 #ifdef TARGET_WORDS_BIGENDIAN
2549 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2550 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2551 #else
2552 v = cirrus_linear_bitblt_readb(opaque, addr);
2553 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2554 #endif
2555 return v;
2556 }
2557
2558 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2559 {
2560 uint32_t v;
2561 #ifdef TARGET_WORDS_BIGENDIAN
2562 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2563 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2564 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2565 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2566 #else
2567 v = cirrus_linear_bitblt_readb(opaque, addr);
2568 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2569 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2570 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2571 #endif
2572 return v;
2573 }
2574
2575 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2576 uint32_t val)
2577 {
2578 CirrusVGAState *s = (CirrusVGAState *) opaque;
2579
2580 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2581 /* bitblt */
2582 *s->cirrus_srcptr++ = (uint8_t) val;
2583 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2584 cirrus_bitblt_cputovideo_next(s);
2585 }
2586 }
2587 }
2588
2589 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2590 uint32_t val)
2591 {
2592 #ifdef TARGET_WORDS_BIGENDIAN
2593 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2594 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2595 #else
2596 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2597 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2598 #endif
2599 }
2600
2601 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2602 uint32_t val)
2603 {
2604 #ifdef TARGET_WORDS_BIGENDIAN
2605 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2606 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2607 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2608 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2609 #else
2610 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2611 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2612 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2613 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2614 #endif
2615 }
2616
2617
2618 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2619 cirrus_linear_bitblt_readb,
2620 cirrus_linear_bitblt_readw,
2621 cirrus_linear_bitblt_readl,
2622 };
2623
2624 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2625 cirrus_linear_bitblt_writeb,
2626 cirrus_linear_bitblt_writew,
2627 cirrus_linear_bitblt_writel,
2628 };
2629
2630 static void map_linear_vram(CirrusVGAState *s)
2631 {
2632
2633 vga_dirty_log_stop((VGAState *)s);
2634 if (!s->map_addr && s->lfb_addr && s->lfb_end) {
2635 s->map_addr = s->lfb_addr;
2636 s->map_end = s->lfb_end;
2637 cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset);
2638 vga_dirty_log_start((VGAState *)s);
2639 }
2640
2641 if (!s->map_addr)
2642 return;
2643
2644 #ifndef TARGET_IA64
2645 s->lfb_vram_mapped = 0;
2646
2647 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2648 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_UNASSIGNED);
2649 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2650 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_UNASSIGNED);
2651 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2652 && !((s->sr[0x07] & 0x01) == 0)
2653 && !((s->gr[0x0B] & 0x14) == 0x14)
2654 && !(s->gr[0x0B] & 0x02)) {
2655
2656 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2657 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2658 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2659 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2660
2661 s->lfb_vram_mapped = 1;
2662 }
2663 else {
2664 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000, s->vga_io_memory);
2665 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000, s->vga_io_memory);
2666 }
2667 #endif
2668 vga_dirty_log_start((VGAState *)s);
2669 }
2670
2671 static void unmap_linear_vram(CirrusVGAState *s)
2672 {
2673 vga_dirty_log_stop((VGAState *)s);
2674 if (s->map_addr && s->lfb_addr && s->lfb_end)
2675 s->map_addr = s->map_end = 0;
2676
2677 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2678 s->vga_io_memory);
2679 vga_dirty_log_start((VGAState *)s);
2680 }
2681
2682 /* Compute the memory access functions */
2683 static void cirrus_update_memory_access(CirrusVGAState *s)
2684 {
2685 unsigned mode;
2686
2687 if ((s->sr[0x17] & 0x44) == 0x44) {
2688 goto generic_io;
2689 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2690 goto generic_io;
2691 } else {
2692 if ((s->gr[0x0B] & 0x14) == 0x14) {
2693 goto generic_io;
2694 } else if (s->gr[0x0B] & 0x02) {
2695 goto generic_io;
2696 }
2697
2698 mode = s->gr[0x05] & 0x7;
2699 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2700 map_linear_vram(s);
2701 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2702 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2703 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2704 } else {
2705 generic_io:
2706 unmap_linear_vram(s);
2707 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2708 s->cirrus_linear_write[1] = cirrus_linear_writew;
2709 s->cirrus_linear_write[2] = cirrus_linear_writel;
2710 }
2711 }
2712 }
2713
2714
2715 /* I/O ports */
2716
2717 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2718 {
2719 CirrusVGAState *s = opaque;
2720 int val, index;
2721
2722 /* check port range access depending on color/monochrome mode */
2723 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2724 || (addr >= 0x3d0 && addr <= 0x3df
2725 && !(s->msr & MSR_COLOR_EMULATION))) {
2726 val = 0xff;
2727 } else {
2728 switch (addr) {
2729 case 0x3c0:
2730 if (s->ar_flip_flop == 0) {
2731 val = s->ar_index;
2732 } else {
2733 val = 0;
2734 }
2735 break;
2736 case 0x3c1:
2737 index = s->ar_index & 0x1f;
2738 if (index < 21)
2739 val = s->ar[index];
2740 else
2741 val = 0;
2742 break;
2743 case 0x3c2:
2744 val = s->st00;
2745 break;
2746 case 0x3c4:
2747 val = s->sr_index;
2748 break;
2749 case 0x3c5:
2750 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2751 break;
2752 val = s->sr[s->sr_index];
2753 #ifdef DEBUG_VGA_REG
2754 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2755 #endif
2756 break;
2757 case 0x3c6:
2758 cirrus_read_hidden_dac(s, &val);
2759 break;
2760 case 0x3c7:
2761 val = s->dac_state;
2762 break;
2763 case 0x3c8:
2764 val = s->dac_write_index;
2765 s->cirrus_hidden_dac_lockindex = 0;
2766 break;
2767 case 0x3c9:
2768 if (cirrus_hook_read_palette(s, &val))
2769 break;
2770 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2771 if (++s->dac_sub_index == 3) {
2772 s->dac_sub_index = 0;
2773 s->dac_read_index++;
2774 }
2775 break;
2776 case 0x3ca:
2777 val = s->fcr;
2778 break;
2779 case 0x3cc:
2780 val = s->msr;
2781 break;
2782 case 0x3ce:
2783 val = s->gr_index;
2784 break;
2785 case 0x3cf:
2786 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2787 break;
2788 val = s->gr[s->gr_index];
2789 #ifdef DEBUG_VGA_REG
2790 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2791 #endif
2792 break;
2793 case 0x3b4:
2794 case 0x3d4:
2795 val = s->cr_index;
2796 break;
2797 case 0x3b5:
2798 case 0x3d5:
2799 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2800 break;
2801 val = s->cr[s->cr_index];
2802 #ifdef DEBUG_VGA_REG
2803 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2804 #endif
2805 break;
2806 case 0x3ba:
2807 case 0x3da:
2808 /* just toggle to fool polling */
2809 val = s->st01 = s->retrace((VGAState *) s);
2810 s->ar_flip_flop = 0;
2811 break;
2812 default:
2813 val = 0x00;
2814 break;
2815 }
2816 }
2817 #if defined(DEBUG_VGA)
2818 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2819 #endif
2820 return val;
2821 }
2822
2823 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2824 {
2825 CirrusVGAState *s = opaque;
2826 int index;
2827
2828 /* check port range access depending on color/monochrome mode */
2829 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2830 || (addr >= 0x3d0 && addr <= 0x3df
2831 && !(s->msr & MSR_COLOR_EMULATION)))
2832 return;
2833
2834 #ifdef DEBUG_VGA
2835 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2836 #endif
2837
2838 switch (addr) {
2839 case 0x3c0:
2840 if (s->ar_flip_flop == 0) {
2841 val &= 0x3f;
2842 s->ar_index = val;
2843 } else {
2844 index = s->ar_index & 0x1f;
2845 switch (index) {
2846 case 0x00 ... 0x0f:
2847 s->ar[index] = val & 0x3f;
2848 break;
2849 case 0x10:
2850 s->ar[index] = val & ~0x10;
2851 break;
2852 case 0x11:
2853 s->ar[index] = val;
2854 break;
2855 case 0x12:
2856 s->ar[index] = val & ~0xc0;
2857 break;
2858 case 0x13:
2859 s->ar[index] = val & ~0xf0;
2860 break;
2861 case 0x14:
2862 s->ar[index] = val & ~0xf0;
2863 break;
2864 default:
2865 break;
2866 }
2867 }
2868 s->ar_flip_flop ^= 1;
2869 break;
2870 case 0x3c2:
2871 s->msr = val & ~0x10;
2872 s->update_retrace_info((VGAState *) s);
2873 break;
2874 case 0x3c4:
2875 s->sr_index = val;
2876 break;
2877 case 0x3c5:
2878 if (cirrus_hook_write_sr(s, s->sr_index, val))
2879 break;
2880 #ifdef DEBUG_VGA_REG
2881 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2882 #endif
2883 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2884 if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
2885 break;
2886 case 0x3c6:
2887 cirrus_write_hidden_dac(s, val);
2888 break;
2889 case 0x3c7:
2890 s->dac_read_index = val;
2891 s->dac_sub_index = 0;
2892 s->dac_state = 3;
2893 break;
2894 case 0x3c8:
2895 s->dac_write_index = val;
2896 s->dac_sub_index = 0;
2897 s->dac_state = 0;
2898 break;
2899 case 0x3c9:
2900 if (cirrus_hook_write_palette(s, val))
2901 break;
2902 s->dac_cache[s->dac_sub_index] = val;
2903 if (++s->dac_sub_index == 3) {
2904 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2905 s->dac_sub_index = 0;
2906 s->dac_write_index++;
2907 }
2908 break;
2909 case 0x3ce:
2910 s->gr_index = val;
2911 break;
2912 case 0x3cf:
2913 if (cirrus_hook_write_gr(s, s->gr_index, val))
2914 break;
2915 #ifdef DEBUG_VGA_REG
2916 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2917 #endif
2918 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2919 break;
2920 case 0x3b4:
2921 case 0x3d4:
2922 s->cr_index = val;
2923 break;
2924 case 0x3b5:
2925 case 0x3d5:
2926 if (cirrus_hook_write_cr(s, s->cr_index, val))
2927 break;
2928 #ifdef DEBUG_VGA_REG
2929 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2930 #endif
2931 /* handle CR0-7 protection */
2932 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2933 /* can always write bit 4 of CR7 */
2934 if (s->cr_index == 7)
2935 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2936 return;
2937 }
2938 switch (s->cr_index) {
2939 case 0x01: /* horizontal display end */
2940 case 0x07:
2941 case 0x09:
2942 case 0x0c:
2943 case 0x0d:
2944 case 0x12: /* vertical display end */
2945 s->cr[s->cr_index] = val;
2946 break;
2947
2948 default:
2949 s->cr[s->cr_index] = val;
2950 break;
2951 }
2952
2953 switch(s->cr_index) {
2954 case 0x00:
2955 case 0x04:
2956 case 0x05:
2957 case 0x06:
2958 case 0x07:
2959 case 0x11:
2960 case 0x17:
2961 s->update_retrace_info((VGAState *) s);
2962 break;
2963 }
2964 break;
2965 case 0x3ba:
2966 case 0x3da:
2967 s->fcr = val & 0x10;
2968 break;
2969 }
2970 }
2971
2972 /***************************************
2973 *
2974 * memory-mapped I/O access
2975 *
2976 ***************************************/
2977
2978 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2979 {
2980 CirrusVGAState *s = (CirrusVGAState *) opaque;
2981
2982 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2983
2984 if (addr >= 0x100) {
2985 return cirrus_mmio_blt_read(s, addr - 0x100);
2986 } else {
2987 return vga_ioport_read(s, addr + 0x3c0);
2988 }
2989 }
2990
2991 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2992 {
2993 uint32_t v;
2994 #ifdef TARGET_WORDS_BIGENDIAN
2995 v = cirrus_mmio_readb(opaque, addr) << 8;
2996 v |= cirrus_mmio_readb(opaque, addr + 1);
2997 #else
2998 v = cirrus_mmio_readb(opaque, addr);
2999 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3000 #endif
3001 return v;
3002 }
3003
3004 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
3005 {
3006 uint32_t v;
3007 #ifdef TARGET_WORDS_BIGENDIAN
3008 v = cirrus_mmio_readb(opaque, addr) << 24;
3009 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3010 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3011 v |= cirrus_mmio_readb(opaque, addr + 3);
3012 #else
3013 v = cirrus_mmio_readb(opaque, addr);
3014 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3015 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3016 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3017 #endif
3018 return v;
3019 }
3020
3021 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3022 uint32_t val)
3023 {
3024 CirrusVGAState *s = (CirrusVGAState *) opaque;
3025
3026 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3027
3028 if (addr >= 0x100) {
3029 cirrus_mmio_blt_write(s, addr - 0x100, val);
3030 } else {
3031 vga_ioport_write(s, addr + 0x3c0, val);
3032 }
3033 }
3034
3035 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3036 uint32_t val)
3037 {
3038 #ifdef TARGET_WORDS_BIGENDIAN
3039 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3040 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3041 #else
3042 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3043 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3044 #endif
3045 }
3046
3047 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3048 uint32_t val)
3049 {
3050 #ifdef TARGET_WORDS_BIGENDIAN
3051 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3052 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3053 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3054 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3055 #else
3056 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3057 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3058 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3059 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3060 #endif
3061 }
3062
3063
3064 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3065 cirrus_mmio_readb,
3066 cirrus_mmio_readw,
3067 cirrus_mmio_readl,
3068 };
3069
3070 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3071 cirrus_mmio_writeb,
3072 cirrus_mmio_writew,
3073 cirrus_mmio_writel,
3074 };
3075
3076 /* load/save state */
3077
3078 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3079 {
3080 CirrusVGAState *s = opaque;
3081
3082 if (s->pci_dev)
3083 pci_device_save(s->pci_dev, f);
3084
3085 qemu_put_be32s(f, &s->latch);
3086 qemu_put_8s(f, &s->sr_index);
3087 qemu_put_buffer(f, s->sr, 256);
3088 qemu_put_8s(f, &s->gr_index);
3089 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3090 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3091 qemu_put_buffer(f, s->gr + 2, 254);
3092 qemu_put_8s(f, &s->ar_index);
3093 qemu_put_buffer(f, s->ar, 21);
3094 qemu_put_be32(f, s->ar_flip_flop);
3095 qemu_put_8s(f, &s->cr_index);
3096 qemu_put_buffer(f, s->cr, 256);
3097 qemu_put_8s(f, &s->msr);
3098 qemu_put_8s(f, &s->fcr);
3099 qemu_put_8s(f, &s->st00);
3100 qemu_put_8s(f, &s->st01);
3101
3102 qemu_put_8s(f, &s->dac_state);
3103 qemu_put_8s(f, &s->dac_sub_index);
3104 qemu_put_8s(f, &s->dac_read_index);
3105 qemu_put_8s(f, &s->dac_write_index);
3106 qemu_put_buffer(f, s->dac_cache, 3);
3107 qemu_put_buffer(f, s->palette, 768);
3108
3109 qemu_put_be32(f, s->bank_offset);
3110
3111 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3112 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3113
3114 qemu_put_be32s(f, &s->hw_cursor_x);
3115 qemu_put_be32s(f, &s->hw_cursor_y);
3116 /* XXX: we do not save the bitblt state - we assume we do not save
3117 the state when the blitter is active */
3118 }
3119
3120 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3121 {
3122 CirrusVGAState *s = opaque;
3123 int ret;
3124
3125 if (version_id > 2)
3126 return -EINVAL;
3127
3128 if (s->pci_dev && version_id >= 2) {
3129 ret = pci_device_load(s->pci_dev, f);
3130 if (ret < 0)
3131 return ret;
3132 }
3133
3134 qemu_get_be32s(f, &s->latch);
3135 qemu_get_8s(f, &s->sr_index);
3136 qemu_get_buffer(f, s->sr, 256);
3137 qemu_get_8s(f, &s->gr_index);
3138 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3139 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3140 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3141 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3142 qemu_get_buffer(f, s->gr + 2, 254);
3143 qemu_get_8s(f, &s->ar_index);
3144 qemu_get_buffer(f, s->ar, 21);
3145 s->ar_flip_flop=qemu_get_be32(f);
3146 qemu_get_8s(f, &s->cr_index);
3147 qemu_get_buffer(f, s->cr, 256);
3148 qemu_get_8s(f, &s->msr);
3149 qemu_get_8s(f, &s->fcr);
3150 qemu_get_8s(f, &s->st00);
3151 qemu_get_8s(f, &s->st01);
3152
3153 qemu_get_8s(f, &s->dac_state);
3154 qemu_get_8s(f, &s->dac_sub_index);
3155 qemu_get_8s(f, &s->dac_read_index);
3156 qemu_get_8s(f, &s->dac_write_index);
3157 qemu_get_buffer(f, s->dac_cache, 3);
3158 qemu_get_buffer(f, s->palette, 768);
3159
3160 s->bank_offset=qemu_get_be32(f);
3161
3162 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3163 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3164
3165 qemu_get_be32s(f, &s->hw_cursor_x);
3166 qemu_get_be32s(f, &s->hw_cursor_y);
3167
3168 cirrus_update_memory_access(s);
3169 /* force refresh */
3170 s->graphic_mode = -1;
3171 cirrus_update_bank_ptr(s, 0);
3172 cirrus_update_bank_ptr(s, 1);
3173 return 0;
3174 }
3175
3176 /***************************************
3177 *
3178 * initialize
3179 *
3180 ***************************************/
3181
3182 static void cirrus_reset(void *opaque)
3183 {
3184 CirrusVGAState *s = opaque;
3185
3186 vga_reset(s);
3187 s->sr[0x06] = 0x0f;
3188 if (s->device_id == CIRRUS_ID_CLGD5446) {
3189 /* 4MB 64 bit memory config, always PCI */
3190 s->sr[0x1F] = 0x2d; // MemClock
3191 s->gr[0x18] = 0x0f; // fastest memory configuration
3192 #if 1
3193 s->sr[0x0f] = 0x98;
3194 s->sr[0x17] = 0x20;
3195 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3196 s->real_vram_size = 4096 * 1024;
3197 #else
3198 s->sr[0x0f] = 0x18;
3199 s->sr[0x17] = 0x20;
3200 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3201 s->real_vram_size = 2048 * 1024;
3202 #endif
3203 } else {
3204 s->sr[0x1F] = 0x22; // MemClock
3205 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3206 s->sr[0x17] = s->bustype;
3207 s->real_vram_size = 2048 * 1024;
3208 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3209 }
3210 s->cr[0x27] = s->device_id;
3211
3212 /* Win2K seems to assume that the pattern buffer is at 0xff
3213 initially ! */
3214 memset(s->vram_ptr, 0xff, s->real_vram_size);
3215
3216 s->cirrus_hidden_dac_lockindex = 5;
3217 s->cirrus_hidden_dac_data = 0;
3218
3219 /* I/O handler for LFB */
3220 s->cirrus_linear_io_addr =
3221 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3222 s);
3223 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3224
3225 /* I/O handler for LFB */
3226 s->cirrus_linear_bitblt_io_addr =
3227 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3228 s);
3229
3230 /* I/O handler for memory-mapped I/O */
3231 s->cirrus_mmio_io_addr =
3232 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3233
3234 /* XXX: s->vram_size must be a power of two */
3235 s->cirrus_addr_mask = s->real_vram_size - 1;
3236 s->linear_mmio_mask = s->real_vram_size - 256;
3237
3238 s->get_bpp = cirrus_get_bpp;
3239 s->get_offsets = cirrus_get_offsets;
3240 s->get_resolution = cirrus_get_resolution;
3241 s->cursor_invalidate = cirrus_cursor_invalidate;
3242 s->cursor_draw_line = cirrus_cursor_draw_line;
3243 }
3244
3245 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3246 {
3247 int i;
3248 static int inited;
3249
3250 if (!inited) {
3251 inited = 1;
3252 for(i = 0;i < 256; i++)
3253 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3254 rop_to_index[CIRRUS_ROP_0] = 0;
3255 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3256 rop_to_index[CIRRUS_ROP_NOP] = 2;
3257 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3258 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3259 rop_to_index[CIRRUS_ROP_SRC] = 5;
3260 rop_to_index[CIRRUS_ROP_1] = 6;
3261 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3262 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3263 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3264 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3265 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3266 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3267 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3268 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3269 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3270 s->device_id = device_id;
3271 if (is_pci)
3272 s->bustype = CIRRUS_BUSTYPE_PCI;
3273 else
3274 s->bustype = CIRRUS_BUSTYPE_ISA;
3275 }
3276
3277 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3278
3279 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3280 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3281 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3282 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3283
3284 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3285
3286 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3287 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3288 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3289 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3290
3291 s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3292 cirrus_vga_mem_write, s);
3293 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3294 s->vga_io_memory);
3295 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3296
3297 qemu_register_reset(cirrus_reset, s);
3298 cirrus_reset(s);
3299 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3300 }
3301
3302 /***************************************
3303 *
3304 * ISA bus support
3305 *
3306 ***************************************/
3307
3308 void isa_cirrus_vga_init(uint8_t *vga_ram_base,
3309 ram_addr_t vga_ram_offset, int vga_ram_size)
3310 {
3311 CirrusVGAState *s;
3312
3313 s = qemu_mallocz(sizeof(CirrusVGAState));
3314
3315 vga_common_init((VGAState *)s,
3316 vga_ram_base, vga_ram_offset, vga_ram_size);
3317 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3318 s->ds = graphic_console_init(s->update, s->invalidate,
3319 s->screen_dump, s->text_update, s);
3320 /* XXX ISA-LFB support */
3321 }
3322
3323 /***************************************
3324 *
3325 * PCI bus support
3326 *
3327 ***************************************/
3328
3329 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3330 uint32_t addr, uint32_t size, int type)
3331 {
3332 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3333
3334 vga_dirty_log_stop((VGAState *)s);
3335 /* XXX: add byte swapping apertures */
3336 cpu_register_physical_memory(addr, s->vram_size,
3337 s->cirrus_linear_io_addr);
3338 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3339 s->cirrus_linear_bitblt_io_addr);
3340
3341 s->map_addr = s->map_end = 0;
3342 s->lfb_addr = addr & TARGET_PAGE_MASK;
3343 s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3344 /* account for overflow */
3345 if (s->lfb_end < addr + VGA_RAM_SIZE)
3346 s->lfb_end = addr + VGA_RAM_SIZE;
3347 vga_dirty_log_start((VGAState *)s);
3348 }
3349
3350 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3351 uint32_t addr, uint32_t size, int type)
3352 {
3353 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3354
3355 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3356 s->cirrus_mmio_io_addr);
3357 }
3358
3359 static void pci_cirrus_write_config(PCIDevice *d,
3360 uint32_t address, uint32_t val, int len)
3361 {
3362 PCICirrusVGAState *pvs = container_of(d, PCICirrusVGAState, dev);
3363 CirrusVGAState *s = &pvs->cirrus_vga;
3364
3365 vga_dirty_log_stop((VGAState *)s);
3366 pci_default_write_config(d, address, val, len);
3367 if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
3368 s->map_addr = 0;
3369 cirrus_update_memory_access(s);
3370 vga_dirty_log_start((VGAState *)s);
3371 }
3372
3373 void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
3374 ram_addr_t vga_ram_offset, int vga_ram_size)
3375 {
3376 PCICirrusVGAState *d;
3377 uint8_t *pci_conf;
3378 CirrusVGAState *s;
3379 int device_id;
3380
3381 device_id = CIRRUS_ID_CLGD5446;
3382
3383 /* setup PCI configuration registers */
3384 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3385 sizeof(PCICirrusVGAState),
3386 -1, NULL, pci_cirrus_write_config);
3387 pci_conf = d->dev.config;
3388 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3389 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3390 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3391 pci_conf[0x03] = (uint8_t) (device_id >> 8);
3392 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3393 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3394 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3395 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3396
3397 /* setup VGA */
3398 s = &d->cirrus_vga;
3399 vga_common_init((VGAState *)s,
3400 vga_ram_base, vga_ram_offset, vga_ram_size);
3401 cirrus_init_common(s, device_id, 1);
3402
3403 s->ds = graphic_console_init(s->update, s->invalidate,
3404 s->screen_dump, s->text_update, s);
3405
3406 s->pci_dev = (PCIDevice *)d;
3407
3408 /* setup memory space */
3409 /* memory #0 LFB */
3410 /* memory #1 memory-mapped I/O */
3411 /* XXX: s->vram_size must be a power of two */
3412 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3413 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3414 if (device_id == CIRRUS_ID_CLGD5446) {
3415 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3416 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3417 }
3418 /* XXX: ROM BIOS */
3419 }
AMD IOMMU emulation for KVM