4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
21 #include "qemu-timer.h"
31 /* i82731AB (PIIX4) compatible power management function */
32 #define PM_FREQ 3579545
34 #define ACPI_DBG_IO_ADDR 0xb044
36 typedef struct PIIX4PMState
{
44 int64_t tmr_overflow_time
;
57 #define RSM_STS (1 << 15)
58 #define PWRBTN_STS (1 << 8)
59 #define RTC_EN (1 << 10)
60 #define PWRBTN_EN (1 << 8)
61 #define GBL_EN (1 << 5)
62 #define TMROF_EN (1 << 0)
64 #define SCI_EN (1 << 0)
66 #define SUS_EN (1 << 13)
68 #define ACPI_ENABLE 0xf1
69 #define ACPI_DISABLE 0xf0
71 #define SMBHSTSTS 0x00
72 #define SMBHSTCNT 0x02
73 #define SMBHSTCMD 0x03
74 #define SMBHSTADD 0x04
75 #define SMBHSTDAT0 0x05
76 #define SMBHSTDAT1 0x06
77 #define SMBBLKDAT 0x07
79 static PIIX4PMState
*pm_state
;
81 static uint32_t get_pmtmr(PIIX4PMState
*s
)
84 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, get_ticks_per_sec());
88 static int get_pmsts(PIIX4PMState
*s
)
93 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, get_ticks_per_sec());
94 if (d
>= s
->tmr_overflow_time
)
99 static void pm_update_sci(PIIX4PMState
*s
)
101 int sci_level
, pmsts
;
104 pmsts
= get_pmsts(s
);
105 sci_level
= (((pmsts
& s
->pmen
) &
106 (RTC_EN
| PWRBTN_EN
| GBL_EN
| TMROF_EN
)) != 0);
107 qemu_set_irq(s
->irq
, sci_level
);
108 /* schedule a timer interruption if needed */
109 if ((s
->pmen
& TMROF_EN
) && !(pmsts
& TMROF_EN
)) {
110 expire_time
= muldiv64(s
->tmr_overflow_time
, get_ticks_per_sec(), PM_FREQ
);
111 qemu_mod_timer(s
->tmr_timer
, expire_time
);
113 qemu_del_timer(s
->tmr_timer
);
117 static void pm_tmr_timer(void *opaque
)
119 PIIX4PMState
*s
= opaque
;
123 static void pm_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
125 PIIX4PMState
*s
= opaque
;
132 pmsts
= get_pmsts(s
);
133 if (pmsts
& val
& TMROF_EN
) {
134 /* if TMRSTS is reset, then compute the new overflow time */
135 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
,
136 get_ticks_per_sec());
137 s
->tmr_overflow_time
= (d
+ 0x800000LL
) & ~0x7fffffLL
;
150 s
->pmcntrl
= val
& ~(SUS_EN
);
152 /* change suspend type */
153 sus_typ
= (val
>> 10) & 7;
155 case 0: /* soft power off */
156 qemu_system_shutdown_request();
159 /* RSM_STS should be set on resume. Pretend that resume
160 was caused by power button */
161 s
->pmsts
|= (RSM_STS
| PWRBTN_STS
);
162 qemu_system_reset_request();
163 #if defined(TARGET_I386)
164 cmos_set_s3_resume();
176 printf("PM writew port=0x%04x val=0x%04x\n", addr
, val
);
180 static uint32_t pm_ioport_readw(void *opaque
, uint32_t addr
)
182 PIIX4PMState
*s
= opaque
;
201 printf("PM readw port=0x%04x val=0x%04x\n", addr
, val
);
206 static void pm_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
208 // PIIX4PMState *s = opaque;
211 printf("PM writel port=0x%04x val=0x%08x\n", addr
, val
);
215 static uint32_t pm_ioport_readl(void *opaque
, uint32_t addr
)
217 PIIX4PMState
*s
= opaque
;
230 printf("PM readl port=0x%04x val=0x%08x\n", addr
, val
);
235 static void pm_smi_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
237 PIIX4PMState
*s
= opaque
;
240 printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr
, val
);
245 /* ACPI specs 3.0, 4.7.2.5 */
246 if (val
== ACPI_ENABLE
) {
247 s
->pmcntrl
|= SCI_EN
;
248 } else if (val
== ACPI_DISABLE
) {
249 s
->pmcntrl
&= ~SCI_EN
;
252 if (s
->dev
.config
[0x5b] & (1 << 1)) {
253 cpu_interrupt(first_cpu
, CPU_INTERRUPT_SMI
);
260 static uint32_t pm_smi_readb(void *opaque
, uint32_t addr
)
262 PIIX4PMState
*s
= opaque
;
272 printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr
, val
);
277 static void acpi_dbg_writel(void *opaque
, uint32_t addr
, uint32_t val
)
280 printf("ACPI: DBG: 0x%08x\n", val
);
284 static void smb_transaction(PIIX4PMState
*s
)
286 uint8_t prot
= (s
->smb_ctl
>> 2) & 0x07;
287 uint8_t read
= s
->smb_addr
& 0x01;
288 uint8_t cmd
= s
->smb_cmd
;
289 uint8_t addr
= s
->smb_addr
>> 1;
290 i2c_bus
*bus
= s
->smbus
;
293 printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr
, prot
);
297 smbus_quick_command(bus
, addr
, read
);
301 s
->smb_data0
= smbus_receive_byte(bus
, addr
);
303 smbus_send_byte(bus
, addr
, cmd
);
308 s
->smb_data0
= smbus_read_byte(bus
, addr
, cmd
);
310 smbus_write_byte(bus
, addr
, cmd
, s
->smb_data0
);
316 val
= smbus_read_word(bus
, addr
, cmd
);
318 s
->smb_data1
= val
>> 8;
320 smbus_write_word(bus
, addr
, cmd
, (s
->smb_data1
<< 8) | s
->smb_data0
);
325 s
->smb_data0
= smbus_read_block(bus
, addr
, cmd
, s
->smb_data
);
327 smbus_write_block(bus
, addr
, cmd
, s
->smb_data
, s
->smb_data0
);
339 static void smb_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
341 PIIX4PMState
*s
= opaque
;
344 printf("SMB writeb port=0x%04x val=0x%02x\n", addr
, val
);
369 s
->smb_data
[s
->smb_index
++] = val
;
370 if (s
->smb_index
> 31)
378 static uint32_t smb_ioport_readb(void *opaque
, uint32_t addr
)
380 PIIX4PMState
*s
= opaque
;
390 val
= s
->smb_ctl
& 0x1f;
405 val
= s
->smb_data
[s
->smb_index
++];
406 if (s
->smb_index
> 31)
414 printf("SMB readb port=0x%04x val=0x%02x\n", addr
, val
);
419 static void pm_io_space_update(PIIX4PMState
*s
)
423 if (s
->dev
.config
[0x80] & 1) {
424 pm_io_base
= le32_to_cpu(*(uint32_t *)(s
->dev
.config
+ 0x40));
425 pm_io_base
&= 0xffc0;
427 /* XXX: need to improve memory and ioport allocation */
429 printf("PM: mapping to 0x%x\n", pm_io_base
);
431 register_ioport_write(pm_io_base
, 64, 2, pm_ioport_writew
, s
);
432 register_ioport_read(pm_io_base
, 64, 2, pm_ioport_readw
, s
);
433 register_ioport_write(pm_io_base
, 64, 4, pm_ioport_writel
, s
);
434 register_ioport_read(pm_io_base
, 64, 4, pm_ioport_readl
, s
);
438 static void pm_write_config(PCIDevice
*d
,
439 uint32_t address
, uint32_t val
, int len
)
441 pci_default_write_config(d
, address
, val
, len
);
443 pm_io_space_update((PIIX4PMState
*)d
);
446 static int vmstate_acpi_post_load(void *opaque
, int version_id
)
448 PIIX4PMState
*s
= opaque
;
450 pm_io_space_update(s
);
454 static const VMStateDescription vmstate_acpi
= {
457 .minimum_version_id
= 1,
458 .minimum_version_id_old
= 1,
459 .post_load
= vmstate_acpi_post_load
,
460 .fields
= (VMStateField
[]) {
461 VMSTATE_PCI_DEVICE(dev
, PIIX4PMState
),
462 VMSTATE_UINT16(pmsts
, PIIX4PMState
),
463 VMSTATE_UINT16(pmen
, PIIX4PMState
),
464 VMSTATE_UINT16(pmcntrl
, PIIX4PMState
),
465 VMSTATE_UINT8(apmc
, PIIX4PMState
),
466 VMSTATE_UINT8(apms
, PIIX4PMState
),
467 VMSTATE_TIMER(tmr_timer
, PIIX4PMState
),
468 VMSTATE_INT64(tmr_overflow_time
, PIIX4PMState
),
469 VMSTATE_END_OF_LIST()
473 static void piix4_reset(void *opaque
)
475 PIIX4PMState
*s
= opaque
;
476 uint8_t *pci_conf
= s
->dev
.config
;
484 /* Mark SMM as already inited (until KVM supports SMM). */
485 pci_conf
[0x5B] = 0x02;
489 static void piix4_powerdown(void *opaque
, int irq
, int power_failing
)
491 #if defined(TARGET_I386)
492 PIIX4PMState
*s
= opaque
;
495 qemu_system_shutdown_request();
496 } else if (s
->pmen
& PWRBTN_EN
) {
497 s
->pmsts
|= PWRBTN_EN
;
503 i2c_bus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
509 s
= (PIIX4PMState
*)pci_register_device(bus
,
510 "PM", sizeof(PIIX4PMState
),
511 devfn
, NULL
, pm_write_config
);
513 pci_conf
= s
->dev
.config
;
514 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
515 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82371AB_3
);
516 pci_conf
[0x06] = 0x80;
517 pci_conf
[0x07] = 0x02;
518 pci_conf
[0x08] = 0x03; // revision number
519 pci_conf
[0x09] = 0x00;
520 pci_config_set_class(pci_conf
, PCI_CLASS_BRIDGE_OTHER
);
521 pci_conf
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
; // header_type
522 pci_conf
[0x3d] = 0x01; // interrupt pin 1
524 pci_conf
[0x40] = 0x01; /* PM io base read only bit */
526 #if defined(TARGET_IA64)
527 pci_conf
[0x40] = 0x41; /* PM io base read only bit */
528 pci_conf
[0x41] = 0x1f;
529 pm_write_config(s
, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
533 register_ioport_write(0xb2, 2, 1, pm_smi_writeb
, s
);
534 register_ioport_read(0xb2, 2, 1, pm_smi_readb
, s
);
536 register_ioport_write(ACPI_DBG_IO_ADDR
, 4, 4, acpi_dbg_writel
, s
);
539 /* Mark SMM as already inited to prevent SMM from running. KVM does not
540 * support SMM mode. */
541 pci_conf
[0x5B] = 0x02;
544 /* XXX: which specification is used ? The i82731AB has different
546 pci_conf
[0x5f] = (parallel_hds
[0] != NULL
? 0x80 : 0) | 0x10;
547 pci_conf
[0x63] = 0x60;
548 pci_conf
[0x67] = (serial_hds
[0] != NULL
? 0x08 : 0) |
549 (serial_hds
[1] != NULL
? 0x90 : 0);
551 pci_conf
[0x90] = smb_io_base
| 1;
552 pci_conf
[0x91] = smb_io_base
>> 8;
553 pci_conf
[0xd2] = 0x09;
554 register_ioport_write(smb_io_base
, 64, 1, smb_ioport_writeb
, s
);
555 register_ioport_read(smb_io_base
, 64, 1, smb_ioport_readb
, s
);
557 s
->tmr_timer
= qemu_new_timer(vm_clock
, pm_tmr_timer
, s
);
559 qemu_system_powerdown
= *qemu_allocate_irqs(piix4_powerdown
, s
, 1);
561 vmstate_register(0, &vmstate_acpi
, s
);
563 s
->smbus
= i2c_init_bus(NULL
, "i2c");
565 qemu_register_reset(piix4_reset
, s
);
570 #define GPE_BASE 0xafe0
571 #define PROC_BASE 0xaf00
572 #define PCI_BASE 0xae00
573 #define PCI_EJ_BASE 0xae08
576 uint16_t sts
; /* status */
577 uint16_t en
; /* enabled */
578 uint8_t cpus_sts
[32];
586 static struct gpe_regs gpe
;
587 static struct pci_status pci0_status
;
589 static uint32_t gpe_read_val(uint16_t val
, uint32_t addr
)
592 return (val
>> 8) & 0xff;
596 static uint32_t gpe_readb(void *opaque
, uint32_t addr
)
599 struct gpe_regs
*g
= opaque
;
601 case PROC_BASE
... PROC_BASE
+31:
602 val
= g
->cpus_sts
[addr
- PROC_BASE
];
607 val
= gpe_read_val(g
->sts
, addr
);
611 val
= gpe_read_val(g
->en
, addr
);
618 printf("gpe read %x == %x\n", addr
, val
);
623 static void gpe_write_val(uint16_t *cur
, int addr
, uint32_t val
)
626 *cur
= (*cur
& 0xff) | (val
<< 8);
628 *cur
= (*cur
& 0xff00) | (val
& 0xff);
631 static void gpe_reset_val(uint16_t *cur
, int addr
, uint32_t val
)
633 uint16_t x1
, x0
= val
& 0xff;
634 int shift
= (addr
& 1) ? 8 : 0;
636 x1
= (*cur
>> shift
) & 0xff;
640 *cur
= (*cur
& (0xff << (8 - shift
))) | (x1
<< shift
);
643 static void gpe_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
645 struct gpe_regs
*g
= opaque
;
647 case PROC_BASE
... PROC_BASE
+ 31:
648 /* don't allow to change cpus_sts from inside a guest */
653 gpe_reset_val(&g
->sts
, addr
, val
);
657 gpe_write_val(&g
->en
, addr
, val
);
664 printf("gpe write %x <== %d\n", addr
, val
);
668 static uint32_t pcihotplug_read(void *opaque
, uint32_t addr
)
671 struct pci_status
*g
= opaque
;
684 printf("pcihotplug read %x == %x\n", addr
, val
);
689 static void pcihotplug_write(void *opaque
, uint32_t addr
, uint32_t val
)
691 struct pci_status
*g
= opaque
;
702 printf("pcihotplug write %x <== %d\n", addr
, val
);
706 static uint32_t pciej_read(void *opaque
, uint32_t addr
)
709 printf("pciej read %x\n", addr
);
714 static void pciej_write(void *opaque
, uint32_t addr
, uint32_t val
)
716 BusState
*bus
= opaque
;
719 int slot
= ffs(val
) - 1;
721 QLIST_FOREACH(qdev
, &bus
->children
, sibling
) {
722 dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
723 if (PCI_SLOT(dev
->devfn
) == slot
) {
724 #if defined (TARGET_I386)
725 pci_device_hot_remove_success(dev
);
733 printf("pciej write %x <== %d\n", addr
, val
);
737 static const char *model
;
739 static int piix4_device_hotplug(PCIDevice
*dev
, int state
);
741 void piix4_acpi_system_hot_add_init(PCIBus
*bus
, const char *cpu_model
)
743 int i
= 0, cpus
= smp_cpus
;
746 gpe
.cpus_sts
[i
++] = (cpus
< 8) ? (1 << cpus
) - 1 : 0xff;
749 register_ioport_write(GPE_BASE
, 4, 1, gpe_writeb
, &gpe
);
750 register_ioport_read(GPE_BASE
, 4, 1, gpe_readb
, &gpe
);
752 register_ioport_write(PROC_BASE
, 32, 1, gpe_writeb
, &gpe
);
753 register_ioport_read(PROC_BASE
, 32, 1, gpe_readb
, &gpe
);
755 register_ioport_write(PCI_BASE
, 8, 4, pcihotplug_write
, &pci0_status
);
756 register_ioport_read(PCI_BASE
, 8, 4, pcihotplug_read
, &pci0_status
);
758 register_ioport_write(PCI_EJ_BASE
, 4, 4, pciej_write
, bus
);
759 register_ioport_read(PCI_EJ_BASE
, 4, 4, pciej_read
, bus
);
763 pci_bus_hotplug(bus
, piix4_device_hotplug
);
766 #if defined(TARGET_I386)
767 static void enable_processor(struct gpe_regs
*g
, int cpu
)
770 g
->cpus_sts
[cpu
/8] |= (1 << (cpu
%8));
773 static void disable_processor(struct gpe_regs
*g
, int cpu
)
776 g
->cpus_sts
[cpu
/8] &= ~(1 << (cpu
%8));
779 void qemu_system_cpu_hot_add(int cpu
, int state
)
783 if (state
&& !qemu_get_cpu(cpu
)) {
784 env
= pc_new_cpu(model
);
786 fprintf(stderr
, "cpu %d creation failed\n", cpu
);
789 env
->cpuid_apic_id
= cpu
;
793 enable_processor(&gpe
, cpu
);
795 disable_processor(&gpe
, cpu
);
797 qemu_set_irq(pm_state
->irq
, 1);
798 qemu_set_irq(pm_state
->irq
, 0);
803 static void enable_device(struct pci_status
*p
, struct gpe_regs
*g
, int slot
)
806 p
->up
|= (1 << slot
);
809 static void disable_device(struct pci_status
*p
, struct gpe_regs
*g
, int slot
)
812 p
->down
|= (1 << slot
);
815 static int piix4_device_hotplug(PCIDevice
*dev
, int state
)
817 int slot
= PCI_SLOT(dev
->devfn
);
820 pci0_status
.down
= 0;
822 enable_device(&pci0_status
, &gpe
, slot
);
824 disable_device(&pci0_status
, &gpe
, slot
);
826 qemu_set_irq(pm_state
->irq
, 1);
827 qemu_set_irq(pm_state
->irq
, 0);
832 struct acpi_table_header
834 char signature
[4]; /* ACPI signature (4 ASCII characters) */
835 uint32_t length
; /* Length of table, in bytes, including header */
836 uint8_t revision
; /* ACPI Specification minor version # */
837 uint8_t checksum
; /* To make sum of entire table == 0 */
838 char oem_id
[6]; /* OEM identification */
839 char oem_table_id
[8]; /* OEM table identification */
840 uint32_t oem_revision
; /* OEM revision number */
841 char asl_compiler_id
[4]; /* ASL compiler vendor ID */
842 uint32_t asl_compiler_revision
; /* ASL compiler revision number */
843 } __attribute__((packed
));
846 size_t acpi_tables_len
;
848 static int acpi_checksum(const uint8_t *data
, int len
)
852 for(i
= 0; i
< len
; i
++)
854 return (-sum
) & 0xff;
857 int acpi_table_add(const char *t
)
859 static const char *dfl_id
= "QEMUQEMU";
860 char buf
[1024], *p
, *f
;
861 struct acpi_table_header acpi_hdr
;
865 memset(&acpi_hdr
, 0, sizeof(acpi_hdr
));
867 if (get_param_value(buf
, sizeof(buf
), "sig", t
)) {
868 strncpy(acpi_hdr
.signature
, buf
, 4);
870 strncpy(acpi_hdr
.signature
, dfl_id
, 4);
872 if (get_param_value(buf
, sizeof(buf
), "rev", t
)) {
873 val
= strtoul(buf
, &p
, 10);
874 if (val
> 255 || *p
!= '\0')
879 acpi_hdr
.revision
= (int8_t)val
;
881 if (get_param_value(buf
, sizeof(buf
), "oem_id", t
)) {
882 strncpy(acpi_hdr
.oem_id
, buf
, 6);
884 strncpy(acpi_hdr
.oem_id
, dfl_id
, 6);
887 if (get_param_value(buf
, sizeof(buf
), "oem_table_id", t
)) {
888 strncpy(acpi_hdr
.oem_table_id
, buf
, 8);
890 strncpy(acpi_hdr
.oem_table_id
, dfl_id
, 8);
893 if (get_param_value(buf
, sizeof(buf
), "oem_rev", t
)) {
894 val
= strtol(buf
, &p
, 10);
900 acpi_hdr
.oem_revision
= cpu_to_le32(val
);
902 if (get_param_value(buf
, sizeof(buf
), "asl_compiler_id", t
)) {
903 strncpy(acpi_hdr
.asl_compiler_id
, buf
, 4);
905 strncpy(acpi_hdr
.asl_compiler_id
, dfl_id
, 4);
908 if (get_param_value(buf
, sizeof(buf
), "asl_compiler_rev", t
)) {
909 val
= strtol(buf
, &p
, 10);
915 acpi_hdr
.asl_compiler_revision
= cpu_to_le32(val
);
917 if (!get_param_value(buf
, sizeof(buf
), "data", t
)) {
921 acpi_hdr
.length
= sizeof(acpi_hdr
);
926 char *n
= strchr(f
, ':');
929 if(stat(f
, &s
) < 0) {
930 fprintf(stderr
, "Can't stat file '%s': %s\n", f
, strerror(errno
));
933 acpi_hdr
.length
+= s
.st_size
;
941 acpi_tables_len
= sizeof(uint16_t);
942 acpi_tables
= qemu_mallocz(acpi_tables_len
);
944 p
= acpi_tables
+ acpi_tables_len
;
945 acpi_tables_len
+= sizeof(uint16_t) + acpi_hdr
.length
;
946 acpi_tables
= qemu_realloc(acpi_tables
, acpi_tables_len
);
948 acpi_hdr
.length
= cpu_to_le32(acpi_hdr
.length
);
949 *(uint16_t*)p
= acpi_hdr
.length
;
950 p
+= sizeof(uint16_t);
951 memcpy(p
, &acpi_hdr
, sizeof(acpi_hdr
));
952 off
= sizeof(acpi_hdr
);
958 char *n
= strchr(f
, ':');
961 fd
= open(f
, O_RDONLY
);
965 if(fstat(fd
, &s
) < 0) {
972 r
= read(fd
, p
+ off
, s
.st_size
);
976 } else if ((r
< 0 && errno
!= EINTR
) || r
== 0) {
988 ((struct acpi_table_header
*)p
)->checksum
= acpi_checksum((uint8_t*)p
, off
);
989 /* increase number of tables */
990 (*(uint16_t*)acpi_tables
) =
991 cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables
) + 1);