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get rid of MSR_COUNT
[qemu-kvm/amd-iommu.git] / qemu-kvm-x86.c
blobd071d5e47a7f5e8e8e895d0b324abaf084e6fca0
1 /*
2 * qemu/kvm integration, x86 specific code
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 *
6 * Licensed under the terms of the GNU GPL version 2 or higher.
7 */
8
9 #include "config.h"
10 #include "config-host.h"
11
12 #include <string.h>
13 #include "hw/hw.h"
14 #include "gdbstub.h"
15 #include <sys/io.h>
16
17 #include "qemu-kvm.h"
18 #include "libkvm.h"
19 #include <pthread.h>
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
22 #include <sys/ioctl.h>
23
24 #include "kvm.h"
25 #include "hw/pc.h"
26
27 #define MSR_IA32_TSC 0x10
28
29 static struct kvm_msr_list *kvm_msr_list;
30 extern unsigned int kvm_shadow_memory;
31 static int kvm_has_msr_star;
32 static int kvm_has_vm_hsave_pa;
33
34 static int lm_capable_kernel;
35
36 int kvm_set_tss_addr(kvm_context_t kvm, unsigned long addr)
37 {
38 #ifdef KVM_CAP_SET_TSS_ADDR
39 int r;
40
41 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
42 if (r > 0) {
43 r = kvm_vm_ioctl(kvm_state, KVM_SET_TSS_ADDR, addr);
44 if (r < 0) {
45 fprintf(stderr, "kvm_set_tss_addr: %m\n");
46 return r;
47 }
48 return 0;
49 }
50 #endif
51 return -ENOSYS;
52 }
53
54 static int kvm_init_tss(kvm_context_t kvm)
55 {
56 #ifdef KVM_CAP_SET_TSS_ADDR
57 int r;
58
59 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
60 if (r > 0) {
61 /*
62 * this address is 3 pages before the bios, and the bios should present
63 * as unavaible memory
64 */
65 r = kvm_set_tss_addr(kvm, 0xfeffd000);
66 if (r < 0) {
67 fprintf(stderr, "kvm_init_tss: unable to set tss addr\n");
68 return r;
69 }
70
71 }
72 #endif
73 return 0;
74 }
75
76 static int kvm_set_identity_map_addr(kvm_context_t kvm, uint64_t addr)
77 {
78 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
79 int r;
80
81 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
82 if (r > 0) {
83 r = kvm_vm_ioctl(kvm_state, KVM_SET_IDENTITY_MAP_ADDR, &addr);
84 if (r == -1) {
85 fprintf(stderr, "kvm_set_identity_map_addr: %m\n");
86 return -errno;
87 }
88 return 0;
89 }
90 #endif
91 return -ENOSYS;
92 }
93
94 static int kvm_init_identity_map_page(kvm_context_t kvm)
95 {
96 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
97 int r;
98
99 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
100 if (r > 0) {
101 /*
102 * this address is 4 pages before the bios, and the bios should present
103 * as unavaible memory
104 */
105 r = kvm_set_identity_map_addr(kvm, 0xfeffc000);
106 if (r < 0) {
107 fprintf(stderr, "kvm_init_identity_map_page: "
108 "unable to set identity mapping addr\n");
109 return r;
110 }
111
112 }
113 #endif
114 return 0;
115 }
116
117 static int kvm_create_pit(kvm_context_t kvm)
118 {
119 #ifdef KVM_CAP_PIT
120 int r;
121
122 kvm->pit_in_kernel = 0;
123 if (!kvm->no_pit_creation) {
124 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_PIT);
125 if (r > 0) {
126 r = kvm_vm_ioctl(kvm_state, KVM_CREATE_PIT);
127 if (r >= 0)
128 kvm->pit_in_kernel = 1;
129 else {
130 fprintf(stderr, "Create kernel PIC irqchip failed\n");
131 return r;
132 }
133 }
134 }
135 #endif
136 return 0;
137 }
138
139 int kvm_arch_create(kvm_context_t kvm, unsigned long phys_mem_bytes,
140 void **vm_mem)
141 {
142 int r = 0;
143
144 r = kvm_init_tss(kvm);
145 if (r < 0)
146 return r;
147
148 r = kvm_init_identity_map_page(kvm);
149 if (r < 0)
150 return r;
151
152 r = kvm_create_pit(kvm);
153 if (r < 0)
154 return r;
155
156 r = kvm_init_coalesced_mmio(kvm);
157 if (r < 0)
158 return r;
159
160 return 0;
161 }
162
163 #ifdef KVM_EXIT_TPR_ACCESS
164
165 static int kvm_handle_tpr_access(CPUState *env)
166 {
167 struct kvm_run *run = env->kvm_run;
168 kvm_tpr_access_report(env,
169 run->tpr_access.rip,
170 run->tpr_access.is_write);
171 return 0;
172 }
173
174
175 int kvm_enable_vapic(CPUState *env, uint64_t vapic)
176 {
177 int r;
178 struct kvm_vapic_addr va = {
179 .vapic_addr = vapic,
180 };
181
182 r = ioctl(env->kvm_fd, KVM_SET_VAPIC_ADDR, &va);
183 if (r == -1) {
184 r = -errno;
185 perror("kvm_enable_vapic");
186 return r;
187 }
188 return 0;
189 }
190
191 #endif
192
193 int kvm_arch_run(CPUState *env)
194 {
195 int r = 0;
196 struct kvm_run *run = env->kvm_run;
197
198
199 switch (run->exit_reason) {
200 #ifdef KVM_EXIT_SET_TPR
201 case KVM_EXIT_SET_TPR:
202 break;
203 #endif
204 #ifdef KVM_EXIT_TPR_ACCESS
205 case KVM_EXIT_TPR_ACCESS:
206 r = kvm_handle_tpr_access(env);
207 break;
208 #endif
209 default:
210 r = 1;
211 break;
212 }
213
214 return r;
215 }
216
217 #define MAX_ALIAS_SLOTS 4
218 static struct {
219 uint64_t start;
220 uint64_t len;
221 } kvm_aliases[MAX_ALIAS_SLOTS];
222
223 static int get_alias_slot(uint64_t start)
224 {
225 int i;
226
227 for (i=0; i<MAX_ALIAS_SLOTS; i++)
228 if (kvm_aliases[i].start == start)
229 return i;
230 return -1;
231 }
232 static int get_free_alias_slot(void)
233 {
234 int i;
235
236 for (i=0; i<MAX_ALIAS_SLOTS; i++)
237 if (kvm_aliases[i].len == 0)
238 return i;
239 return -1;
240 }
241
242 static void register_alias(int slot, uint64_t start, uint64_t len)
243 {
244 kvm_aliases[slot].start = start;
245 kvm_aliases[slot].len = len;
246 }
247
248 int kvm_create_memory_alias(kvm_context_t kvm,
249 uint64_t phys_start,
250 uint64_t len,
251 uint64_t target_phys)
252 {
253 struct kvm_memory_alias alias = {
254 .flags = 0,
255 .guest_phys_addr = phys_start,
256 .memory_size = len,
257 .target_phys_addr = target_phys,
258 };
259 int r;
260 int slot;
261
262 slot = get_alias_slot(phys_start);
263 if (slot < 0)
264 slot = get_free_alias_slot();
265 if (slot < 0)
266 return -EBUSY;
267 alias.slot = slot;
268
269 r = kvm_vm_ioctl(kvm_state, KVM_SET_MEMORY_ALIAS, &alias);
270 if (r == -1)
271 return -errno;
272
273 register_alias(slot, phys_start, len);
274 return 0;
275 }
276
277 int kvm_destroy_memory_alias(kvm_context_t kvm, uint64_t phys_start)
278 {
279 return kvm_create_memory_alias(kvm, phys_start, 0, 0);
280 }
281
282 #ifdef KVM_CAP_IRQCHIP
283
284 int kvm_get_lapic(CPUState *env, struct kvm_lapic_state *s)
285 {
286 int r;
287 if (!kvm_irqchip_in_kernel())
288 return 0;
289 r = ioctl(env->kvm_fd, KVM_GET_LAPIC, s);
290 if (r == -1) {
291 r = -errno;
292 perror("kvm_get_lapic");
293 }
294 return r;
295 }
296
297 int kvm_set_lapic(CPUState *env, struct kvm_lapic_state *s)
298 {
299 int r;
300 if (!kvm_irqchip_in_kernel())
301 return 0;
302 r = ioctl(env->kvm_fd, KVM_SET_LAPIC, s);
303 if (r == -1) {
304 r = -errno;
305 perror("kvm_set_lapic");
306 }
307 return r;
308 }
309
310 #endif
311
312 #ifdef KVM_CAP_PIT
313
314 int kvm_get_pit(kvm_context_t kvm, struct kvm_pit_state *s)
315 {
316 if (!kvm->pit_in_kernel)
317 return 0;
318 return kvm_vm_ioctl(kvm_state, KVM_GET_PIT, s);
319 }
320
321 int kvm_set_pit(kvm_context_t kvm, struct kvm_pit_state *s)
322 {
323 if (!kvm->pit_in_kernel)
324 return 0;
325 return kvm_vm_ioctl(kvm_state, KVM_SET_PIT, s);
326 }
327
328 #ifdef KVM_CAP_PIT_STATE2
329 int kvm_get_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
330 {
331 if (!kvm->pit_in_kernel)
332 return 0;
333 return kvm_vm_ioctl(kvm_state, KVM_GET_PIT2, ps2);
334 }
335
336 int kvm_set_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
337 {
338 if (!kvm->pit_in_kernel)
339 return 0;
340 return kvm_vm_ioctl(kvm_state, KVM_SET_PIT2, ps2);
341 }
342
343 #endif
344 #endif
345
346 int kvm_has_pit_state2(kvm_context_t kvm)
347 {
348 int r = 0;
349
350 #ifdef KVM_CAP_PIT_STATE2
351 r = kvm_check_extension(kvm_state, KVM_CAP_PIT_STATE2);
352 #endif
353 return r;
354 }
355
356 void kvm_show_code(CPUState *env)
357 {
358 #define SHOW_CODE_LEN 50
359 int fd = env->kvm_fd;
360 struct kvm_regs regs;
361 struct kvm_sregs sregs;
362 int r, n;
363 int back_offset;
364 unsigned char code;
365 char code_str[SHOW_CODE_LEN * 3 + 1];
366 unsigned long rip;
367
368 r = ioctl(fd, KVM_GET_SREGS, &sregs);
369 if (r == -1) {
370 perror("KVM_GET_SREGS");
371 return;
372 }
373 r = ioctl(fd, KVM_GET_REGS, &regs);
374 if (r == -1) {
375 perror("KVM_GET_REGS");
376 return;
377 }
378 rip = sregs.cs.base + regs.rip;
379 back_offset = regs.rip;
380 if (back_offset > 20)
381 back_offset = 20;
382 *code_str = 0;
383 for (n = -back_offset; n < SHOW_CODE_LEN-back_offset; ++n) {
384 if (n == 0)
385 strcat(code_str, " -->");
386 cpu_physical_memory_rw(rip + n, &code, 1, 1);
387 sprintf(code_str + strlen(code_str), " %02x", code);
388 }
389 fprintf(stderr, "code:%s\n", code_str);
390 }
391
392
393 /*
394 * Returns available msr list. User must free.
395 */
396 struct kvm_msr_list *kvm_get_msr_list(kvm_context_t kvm)
397 {
398 struct kvm_msr_list sizer, *msrs;
399 int r;
400
401 sizer.nmsrs = 0;
402 r = kvm_ioctl(kvm_state, KVM_GET_MSR_INDEX_LIST, &sizer);
403 if (r < 0 && r != -E2BIG)
404 return NULL;
405 /* Old kernel modules had a bug and could write beyond the provided
406 memory. Allocate at least a safe amount of 1K. */
407 msrs = qemu_malloc(MAX(1024, sizeof(*msrs) +
408 sizer.nmsrs * sizeof(*msrs->indices)));
409
410 msrs->nmsrs = sizer.nmsrs;
411 r = kvm_ioctl(kvm_state, KVM_GET_MSR_INDEX_LIST, msrs);
412 if (r < 0) {
413 free(msrs);
414 errno = r;
415 return NULL;
416 }
417 return msrs;
418 }
419
420 int kvm_get_msrs(CPUState *env, struct kvm_msr_entry *msrs, int n)
421 {
422 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
423 int r, e;
424
425 kmsrs->nmsrs = n;
426 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
427 r = ioctl(env->kvm_fd, KVM_GET_MSRS, kmsrs);
428 e = errno;
429 memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
430 free(kmsrs);
431 errno = e;
432 return r;
433 }
434
435 int kvm_set_msrs(CPUState *env, struct kvm_msr_entry *msrs, int n)
436 {
437 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
438 int r, e;
439
440 kmsrs->nmsrs = n;
441 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
442 r = ioctl(env->kvm_fd, KVM_SET_MSRS, kmsrs);
443 e = errno;
444 free(kmsrs);
445 errno = e;
446 return r;
447 }
448
449 int kvm_get_mce_cap_supported(kvm_context_t kvm, uint64_t *mce_cap,
450 int *max_banks)
451 {
452 #ifdef KVM_CAP_MCE
453 int r;
454
455 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_MCE);
456 if (r > 0) {
457 *max_banks = r;
458 return kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
459 }
460 #endif
461 return -ENOSYS;
462 }
463
464 int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
465 {
466 #ifdef KVM_CAP_MCE
467 return ioctl(env->kvm_fd, KVM_X86_SETUP_MCE, mcg_cap);
468 #else
469 return -ENOSYS;
470 #endif
471 }
472
473 int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
474 {
475 #ifdef KVM_CAP_MCE
476 return ioctl(env->kvm_fd, KVM_X86_SET_MCE, m);
477 #else
478 return -ENOSYS;
479 #endif
480 }
481
482 static void print_seg(FILE *file, const char *name, struct kvm_segment *seg)
483 {
484 fprintf(stderr,
485 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
486 " g %d avl %d)\n",
487 name, seg->selector, seg->base, seg->limit, seg->present,
488 seg->dpl, seg->db, seg->s, seg->type, seg->l, seg->g,
489 seg->avl);
490 }
491
492 static void print_dt(FILE *file, const char *name, struct kvm_dtable *dt)
493 {
494 fprintf(stderr, "%s %llx/%x\n", name, dt->base, dt->limit);
495 }
496
497 void kvm_show_regs(CPUState *env)
498 {
499 int fd = env->kvm_fd;
500 struct kvm_regs regs;
501 struct kvm_sregs sregs;
502 int r;
503
504 r = ioctl(fd, KVM_GET_REGS, &regs);
505 if (r == -1) {
506 perror("KVM_GET_REGS");
507 return;
508 }
509 fprintf(stderr,
510 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
511 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
512 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
513 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
514 "rip %016llx rflags %08llx\n",
515 regs.rax, regs.rbx, regs.rcx, regs.rdx,
516 regs.rsi, regs.rdi, regs.rsp, regs.rbp,
517 regs.r8, regs.r9, regs.r10, regs.r11,
518 regs.r12, regs.r13, regs.r14, regs.r15,
519 regs.rip, regs.rflags);
520 r = ioctl(fd, KVM_GET_SREGS, &sregs);
521 if (r == -1) {
522 perror("KVM_GET_SREGS");
523 return;
524 }
525 print_seg(stderr, "cs", &sregs.cs);
526 print_seg(stderr, "ds", &sregs.ds);
527 print_seg(stderr, "es", &sregs.es);
528 print_seg(stderr, "ss", &sregs.ss);
529 print_seg(stderr, "fs", &sregs.fs);
530 print_seg(stderr, "gs", &sregs.gs);
531 print_seg(stderr, "tr", &sregs.tr);
532 print_seg(stderr, "ldt", &sregs.ldt);
533 print_dt(stderr, "gdt", &sregs.gdt);
534 print_dt(stderr, "idt", &sregs.idt);
535 fprintf(stderr, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
536 " efer %llx\n",
537 sregs.cr0, sregs.cr2, sregs.cr3, sregs.cr4, sregs.cr8,
538 sregs.efer);
539 }
540
541 static uint64_t kvm_get_apic_base(CPUState *env)
542 {
543 return env->kvm_run->apic_base;
544 }
545
546 static void kvm_set_cr8(CPUState *env, uint64_t cr8)
547 {
548 env->kvm_run->cr8 = cr8;
549 }
550
551 static __u64 kvm_get_cr8(CPUState *env)
552 {
553 return env->kvm_run->cr8;
554 }
555
556 int kvm_setup_cpuid(CPUState *env, int nent,
557 struct kvm_cpuid_entry *entries)
558 {
559 struct kvm_cpuid *cpuid;
560 int r;
561
562 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
563
564 cpuid->nent = nent;
565 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
566 r = ioctl(env->kvm_fd, KVM_SET_CPUID, cpuid);
567
568 free(cpuid);
569 return r;
570 }
571
572 int kvm_setup_cpuid2(CPUState *env, int nent,
573 struct kvm_cpuid_entry2 *entries)
574 {
575 struct kvm_cpuid2 *cpuid;
576 int r;
577
578 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
579
580 cpuid->nent = nent;
581 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
582 r = ioctl(env->kvm_fd, KVM_SET_CPUID2, cpuid);
583 if (r == -1) {
584 fprintf(stderr, "kvm_setup_cpuid2: %m\n");
585 r = -errno;
586 }
587 free(cpuid);
588 return r;
589 }
590
591 int kvm_set_shadow_pages(kvm_context_t kvm, unsigned int nrshadow_pages)
592 {
593 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
594 int r;
595
596 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION,
597 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
598 if (r > 0) {
599 r = kvm_vm_ioctl(kvm_state, KVM_SET_NR_MMU_PAGES, nrshadow_pages);
600 if (r < 0) {
601 fprintf(stderr, "kvm_set_shadow_pages: %m\n");
602 return r;
603 }
604 return 0;
605 }
606 #endif
607 return -1;
608 }
609
610 int kvm_get_shadow_pages(kvm_context_t kvm, unsigned int *nrshadow_pages)
611 {
612 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
613 int r;
614
615 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION,
616 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
617 if (r > 0) {
618 *nrshadow_pages = kvm_vm_ioctl(kvm_state, KVM_GET_NR_MMU_PAGES);
619 return 0;
620 }
621 #endif
622 return -1;
623 }
624
625 #ifdef KVM_CAP_VAPIC
626
627 static int tpr_access_reporting(CPUState *env, int enabled)
628 {
629 int r;
630 struct kvm_tpr_access_ctl tac = {
631 .enabled = enabled,
632 };
633
634 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_VAPIC);
635 if (r <= 0)
636 return -ENOSYS;
637 r = ioctl(env->kvm_fd, KVM_TPR_ACCESS_REPORTING, &tac);
638 if (r == -1) {
639 r = -errno;
640 perror("KVM_TPR_ACCESS_REPORTING");
641 return r;
642 }
643 return 0;
644 }
645
646 int kvm_enable_tpr_access_reporting(CPUState *env)
647 {
648 return tpr_access_reporting(env, 1);
649 }
650
651 int kvm_disable_tpr_access_reporting(CPUState *env)
652 {
653 return tpr_access_reporting(env, 0);
654 }
655
656 #endif
657
658 #ifdef KVM_CAP_EXT_CPUID
659
660 static struct kvm_cpuid2 *try_get_cpuid(kvm_context_t kvm, int max)
661 {
662 struct kvm_cpuid2 *cpuid;
663 int r, size;
664
665 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
666 cpuid = qemu_malloc(size);
667 cpuid->nent = max;
668 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_CPUID, cpuid);
669 if (r == 0 && cpuid->nent >= max)
670 r = -E2BIG;
671 if (r < 0) {
672 if (r == -E2BIG) {
673 free(cpuid);
674 return NULL;
675 } else {
676 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
677 strerror(-r));
678 exit(1);
679 }
680 }
681 return cpuid;
682 }
683
684 #define R_EAX 0
685 #define R_ECX 1
686 #define R_EDX 2
687 #define R_EBX 3
688 #define R_ESP 4
689 #define R_EBP 5
690 #define R_ESI 6
691 #define R_EDI 7
692
693 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
694 {
695 struct kvm_cpuid2 *cpuid;
696 int i, max;
697 uint32_t ret = 0;
698 uint32_t cpuid_1_edx;
699
700 if (!kvm_check_extension(kvm_state, KVM_CAP_EXT_CPUID)) {
701 return -1U;
702 }
703
704 max = 1;
705 while ((cpuid = try_get_cpuid(kvm, max)) == NULL) {
706 max *= 2;
707 }
708
709 for (i = 0; i < cpuid->nent; ++i) {
710 if (cpuid->entries[i].function == function) {
711 switch (reg) {
712 case R_EAX:
713 ret = cpuid->entries[i].eax;
714 break;
715 case R_EBX:
716 ret = cpuid->entries[i].ebx;
717 break;
718 case R_ECX:
719 ret = cpuid->entries[i].ecx;
720 break;
721 case R_EDX:
722 ret = cpuid->entries[i].edx;
723 if (function == 1) {
724 /* kvm misreports the following features
725 */
726 ret |= 1 << 12; /* MTRR */
727 ret |= 1 << 16; /* PAT */
728 ret |= 1 << 7; /* MCE */
729 ret |= 1 << 14; /* MCA */
730 }
731
732 /* On Intel, kvm returns cpuid according to
733 * the Intel spec, so add missing bits
734 * according to the AMD spec:
735 */
736 if (function == 0x80000001) {
737 cpuid_1_edx = kvm_get_supported_cpuid(kvm, 1, R_EDX);
738 ret |= cpuid_1_edx & 0xdfeff7ff;
739 }
740 break;
741 }
742 }
743 }
744
745 free(cpuid);
746
747 return ret;
748 }
749
750 #else
751
752 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm, uint32_t function, int reg)
753 {
754 return -1U;
755 }
756
757 #endif
758 int kvm_qemu_create_memory_alias(uint64_t phys_start,
759 uint64_t len,
760 uint64_t target_phys)
761 {
762 return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
763 }
764
765 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
766 {
767 return kvm_destroy_memory_alias(kvm_context, phys_start);
768 }
769
770 int kvm_arch_qemu_create_context(void)
771 {
772 int i;
773 struct utsname utsname;
774
775 uname(&utsname);
776 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
777
778 if (kvm_shadow_memory)
779 kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
780
781 kvm_msr_list = kvm_get_msr_list(kvm_context);
782 if (!kvm_msr_list)
783 return -1;
784 for (i = 0; i < kvm_msr_list->nmsrs; ++i) {
785 if (kvm_msr_list->indices[i] == MSR_STAR)
786 kvm_has_msr_star = 1;
787 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA)
788 kvm_has_vm_hsave_pa = 1;
789 }
790
791 return 0;
792 }
793
794 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
795 uint64_t data)
796 {
797 entry->index = index;
798 entry->data = data;
799 }
800
801 /* returns 0 on success, non-0 on failure */
802 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
803 {
804 switch (entry->index) {
805 case MSR_IA32_SYSENTER_CS:
806 env->sysenter_cs = entry->data;
807 break;
808 case MSR_IA32_SYSENTER_ESP:
809 env->sysenter_esp = entry->data;
810 break;
811 case MSR_IA32_SYSENTER_EIP:
812 env->sysenter_eip = entry->data;
813 break;
814 case MSR_STAR:
815 env->star = entry->data;
816 break;
817 #ifdef TARGET_X86_64
818 case MSR_CSTAR:
819 env->cstar = entry->data;
820 break;
821 case MSR_KERNELGSBASE:
822 env->kernelgsbase = entry->data;
823 break;
824 case MSR_FMASK:
825 env->fmask = entry->data;
826 break;
827 case MSR_LSTAR:
828 env->lstar = entry->data;
829 break;
830 #endif
831 case MSR_IA32_TSC:
832 env->tsc = entry->data;
833 break;
834 case MSR_VM_HSAVE_PA:
835 env->vm_hsave = entry->data;
836 break;
837 default:
838 printf("Warning unknown msr index 0x%x\n", entry->index);
839 return 1;
840 }
841 return 0;
842 }
843
844 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
845 {
846 lhs->selector = rhs->selector;
847 lhs->base = rhs->base;
848 lhs->limit = rhs->limit;
849 lhs->type = 3;
850 lhs->present = 1;
851 lhs->dpl = 3;
852 lhs->db = 0;
853 lhs->s = 1;
854 lhs->l = 0;
855 lhs->g = 0;
856 lhs->avl = 0;
857 lhs->unusable = 0;
858 }
859
860 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
861 {
862 unsigned flags = rhs->flags;
863 lhs->selector = rhs->selector;
864 lhs->base = rhs->base;
865 lhs->limit = rhs->limit;
866 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
867 lhs->present = (flags & DESC_P_MASK) != 0;
868 lhs->dpl = rhs->selector & 3;
869 lhs->db = (flags >> DESC_B_SHIFT) & 1;
870 lhs->s = (flags & DESC_S_MASK) != 0;
871 lhs->l = (flags >> DESC_L_SHIFT) & 1;
872 lhs->g = (flags & DESC_G_MASK) != 0;
873 lhs->avl = (flags & DESC_AVL_MASK) != 0;
874 lhs->unusable = 0;
875 }
876
877 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
878 {
879 lhs->selector = rhs->selector;
880 lhs->base = rhs->base;
881 lhs->limit = rhs->limit;
882 lhs->flags =
883 (rhs->type << DESC_TYPE_SHIFT)
884 | (rhs->present * DESC_P_MASK)
885 | (rhs->dpl << DESC_DPL_SHIFT)
886 | (rhs->db << DESC_B_SHIFT)
887 | (rhs->s * DESC_S_MASK)
888 | (rhs->l << DESC_L_SHIFT)
889 | (rhs->g * DESC_G_MASK)
890 | (rhs->avl * DESC_AVL_MASK);
891 }
892
893 void kvm_arch_load_regs(CPUState *env)
894 {
895 struct kvm_regs regs;
896 struct kvm_fpu fpu;
897 struct kvm_sregs sregs;
898 struct kvm_msr_entry msrs[100];
899 int rc, n, i;
900
901 regs.rax = env->regs[R_EAX];
902 regs.rbx = env->regs[R_EBX];
903 regs.rcx = env->regs[R_ECX];
904 regs.rdx = env->regs[R_EDX];
905 regs.rsi = env->regs[R_ESI];
906 regs.rdi = env->regs[R_EDI];
907 regs.rsp = env->regs[R_ESP];
908 regs.rbp = env->regs[R_EBP];
909 #ifdef TARGET_X86_64
910 regs.r8 = env->regs[8];
911 regs.r9 = env->regs[9];
912 regs.r10 = env->regs[10];
913 regs.r11 = env->regs[11];
914 regs.r12 = env->regs[12];
915 regs.r13 = env->regs[13];
916 regs.r14 = env->regs[14];
917 regs.r15 = env->regs[15];
918 #endif
919
920 regs.rflags = env->eflags;
921 regs.rip = env->eip;
922
923 kvm_set_regs(env, &regs);
924
925 memset(&fpu, 0, sizeof fpu);
926 fpu.fsw = env->fpus & ~(7 << 11);
927 fpu.fsw |= (env->fpstt & 7) << 11;
928 fpu.fcw = env->fpuc;
929 for (i = 0; i < 8; ++i)
930 fpu.ftwx |= (!env->fptags[i]) << i;
931 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
932 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
933 fpu.mxcsr = env->mxcsr;
934 kvm_set_fpu(env, &fpu);
935
936 memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
937
938 if ((env->eflags & VM_MASK)) {
939 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
940 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
941 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
942 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
943 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
944 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
945 } else {
946 set_seg(&sregs.cs, &env->segs[R_CS]);
947 set_seg(&sregs.ds, &env->segs[R_DS]);
948 set_seg(&sregs.es, &env->segs[R_ES]);
949 set_seg(&sregs.fs, &env->segs[R_FS]);
950 set_seg(&sregs.gs, &env->segs[R_GS]);
951 set_seg(&sregs.ss, &env->segs[R_SS]);
952
953 if (env->cr[0] & CR0_PE_MASK) {
954 /* force ss cpl to cs cpl */
955 sregs.ss.selector = (sregs.ss.selector & ~3) |
956 (sregs.cs.selector & 3);
957 sregs.ss.dpl = sregs.ss.selector & 3;
958 }
959 }
960
961 set_seg(&sregs.tr, &env->tr);
962 set_seg(&sregs.ldt, &env->ldt);
963
964 sregs.idt.limit = env->idt.limit;
965 sregs.idt.base = env->idt.base;
966 sregs.gdt.limit = env->gdt.limit;
967 sregs.gdt.base = env->gdt.base;
968
969 sregs.cr0 = env->cr[0];
970 sregs.cr2 = env->cr[2];
971 sregs.cr3 = env->cr[3];
972 sregs.cr4 = env->cr[4];
973
974 sregs.cr8 = cpu_get_apic_tpr(env);
975 sregs.apic_base = cpu_get_apic_base(env);
976
977 sregs.efer = env->efer;
978
979 kvm_set_sregs(env, &sregs);
980
981 /* msrs */
982 n = 0;
983 /* Remember to increase msrs size if you add new registers below */
984 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
985 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
986 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
987 if (kvm_has_msr_star)
988 set_msr_entry(&msrs[n++], MSR_STAR, env->star);
989 if (kvm_has_vm_hsave_pa)
990 set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
991 #ifdef TARGET_X86_64
992 if (lm_capable_kernel) {
993 set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar);
994 set_msr_entry(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
995 set_msr_entry(&msrs[n++], MSR_FMASK, env->fmask);
996 set_msr_entry(&msrs[n++], MSR_LSTAR , env->lstar);
997 }
998 #endif
999
1000 rc = kvm_set_msrs(env, msrs, n);
1001 if (rc == -1)
1002 perror("kvm_set_msrs FAILED");
1003 }
1004
1005 void kvm_load_tsc(CPUState *env)
1006 {
1007 int rc;
1008 struct kvm_msr_entry msr;
1009
1010 set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
1011
1012 rc = kvm_set_msrs(env, &msr, 1);
1013 if (rc == -1)
1014 perror("kvm_set_tsc FAILED.\n");
1015 }
1016
1017 void kvm_arch_save_mpstate(CPUState *env)
1018 {
1019 #ifdef KVM_CAP_MP_STATE
1020 int r;
1021 struct kvm_mp_state mp_state;
1022
1023 r = kvm_get_mpstate(env, &mp_state);
1024 if (r < 0)
1025 env->mp_state = -1;
1026 else
1027 env->mp_state = mp_state.mp_state;
1028 #else
1029 env->mp_state = -1;
1030 #endif
1031 }
1032
1033 void kvm_arch_load_mpstate(CPUState *env)
1034 {
1035 #ifdef KVM_CAP_MP_STATE
1036 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1037
1038 /*
1039 * -1 indicates that the host did not support GET_MP_STATE ioctl,
1040 * so don't touch it.
1041 */
1042 if (env->mp_state != -1)
1043 kvm_set_mpstate(env, &mp_state);
1044 #endif
1045 }
1046
1047 void kvm_arch_save_regs(CPUState *env)
1048 {
1049 struct kvm_regs regs;
1050 struct kvm_fpu fpu;
1051 struct kvm_sregs sregs;
1052 struct kvm_msr_entry msrs[100];
1053 uint32_t hflags;
1054 uint32_t i, n, rc;
1055
1056 kvm_get_regs(env, &regs);
1057
1058 env->regs[R_EAX] = regs.rax;
1059 env->regs[R_EBX] = regs.rbx;
1060 env->regs[R_ECX] = regs.rcx;
1061 env->regs[R_EDX] = regs.rdx;
1062 env->regs[R_ESI] = regs.rsi;
1063 env->regs[R_EDI] = regs.rdi;
1064 env->regs[R_ESP] = regs.rsp;
1065 env->regs[R_EBP] = regs.rbp;
1066 #ifdef TARGET_X86_64
1067 env->regs[8] = regs.r8;
1068 env->regs[9] = regs.r9;
1069 env->regs[10] = regs.r10;
1070 env->regs[11] = regs.r11;
1071 env->regs[12] = regs.r12;
1072 env->regs[13] = regs.r13;
1073 env->regs[14] = regs.r14;
1074 env->regs[15] = regs.r15;
1075 #endif
1076
1077 env->eflags = regs.rflags;
1078 env->eip = regs.rip;
1079
1080 kvm_get_fpu(env, &fpu);
1081 env->fpstt = (fpu.fsw >> 11) & 7;
1082 env->fpus = fpu.fsw;
1083 env->fpuc = fpu.fcw;
1084 for (i = 0; i < 8; ++i)
1085 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1086 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1087 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1088 env->mxcsr = fpu.mxcsr;
1089
1090 kvm_get_sregs(env, &sregs);
1091
1092 memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
1093
1094 get_seg(&env->segs[R_CS], &sregs.cs);
1095 get_seg(&env->segs[R_DS], &sregs.ds);
1096 get_seg(&env->segs[R_ES], &sregs.es);
1097 get_seg(&env->segs[R_FS], &sregs.fs);
1098 get_seg(&env->segs[R_GS], &sregs.gs);
1099 get_seg(&env->segs[R_SS], &sregs.ss);
1100
1101 get_seg(&env->tr, &sregs.tr);
1102 get_seg(&env->ldt, &sregs.ldt);
1103
1104 env->idt.limit = sregs.idt.limit;
1105 env->idt.base = sregs.idt.base;
1106 env->gdt.limit = sregs.gdt.limit;
1107 env->gdt.base = sregs.gdt.base;
1108
1109 env->cr[0] = sregs.cr0;
1110 env->cr[2] = sregs.cr2;
1111 env->cr[3] = sregs.cr3;
1112 env->cr[4] = sregs.cr4;
1113
1114 cpu_set_apic_base(env, sregs.apic_base);
1115
1116 env->efer = sregs.efer;
1117 //cpu_set_apic_tpr(env, sregs.cr8);
1118
1119 #define HFLAG_COPY_MASK ~( \
1120 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1121 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1122 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1123 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1124
1125
1126
1127 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1128 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1129 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1130 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1131 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1132 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1133 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1134
1135 if (env->efer & MSR_EFER_LMA) {
1136 hflags |= HF_LMA_MASK;
1137 }
1138
1139 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1140 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1141 } else {
1142 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1143 (DESC_B_SHIFT - HF_CS32_SHIFT);
1144 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1145 (DESC_B_SHIFT - HF_SS32_SHIFT);
1146 if (!(env->cr[0] & CR0_PE_MASK) ||
1147 (env->eflags & VM_MASK) ||
1148 !(hflags & HF_CS32_MASK)) {
1149 hflags |= HF_ADDSEG_MASK;
1150 } else {
1151 hflags |= ((env->segs[R_DS].base |
1152 env->segs[R_ES].base |
1153 env->segs[R_SS].base) != 0) <<
1154 HF_ADDSEG_SHIFT;
1155 }
1156 }
1157 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1158
1159 /* msrs */
1160 n = 0;
1161 /* Remember to increase msrs size if you add new registers below */
1162 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1163 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1164 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1165 if (kvm_has_msr_star)
1166 msrs[n++].index = MSR_STAR;
1167 msrs[n++].index = MSR_IA32_TSC;
1168 if (kvm_has_vm_hsave_pa)
1169 msrs[n++].index = MSR_VM_HSAVE_PA;
1170 #ifdef TARGET_X86_64
1171 if (lm_capable_kernel) {
1172 msrs[n++].index = MSR_CSTAR;
1173 msrs[n++].index = MSR_KERNELGSBASE;
1174 msrs[n++].index = MSR_FMASK;
1175 msrs[n++].index = MSR_LSTAR;
1176 }
1177 #endif
1178 rc = kvm_get_msrs(env, msrs, n);
1179 if (rc == -1) {
1180 perror("kvm_get_msrs FAILED");
1181 }
1182 else {
1183 n = rc; /* actual number of MSRs */
1184 for (i=0 ; i<n; i++) {
1185 if (get_msr_entry(&msrs[i], env))
1186 return;
1187 }
1188 }
1189 }
1190
1191 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
1192 uint32_t count, CPUState *env)
1193 {
1194 env->regs[R_EAX] = function;
1195 env->regs[R_ECX] = count;
1196 qemu_kvm_cpuid_on_env(env);
1197 e->function = function;
1198 e->flags = 0;
1199 e->index = 0;
1200 e->eax = env->regs[R_EAX];
1201 e->ebx = env->regs[R_EBX];
1202 e->ecx = env->regs[R_ECX];
1203 e->edx = env->regs[R_EDX];
1204 }
1205
1206 struct kvm_para_features {
1207 int cap;
1208 int feature;
1209 } para_features[] = {
1210 #ifdef KVM_CAP_CLOCKSOURCE
1211 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
1212 #endif
1213 #ifdef KVM_CAP_NOP_IO_DELAY
1214 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
1215 #endif
1216 #ifdef KVM_CAP_PV_MMU
1217 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
1218 #endif
1219 #ifdef KVM_CAP_CR3_CACHE
1220 { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
1221 #endif
1222 { -1, -1 }
1223 };
1224
1225 static int get_para_features(kvm_context_t kvm_context)
1226 {
1227 int i, features = 0;
1228
1229 for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
1230 if (kvm_check_extension(kvm_state, para_features[i].cap))
1231 features |= (1 << para_features[i].feature);
1232 }
1233
1234 return features;
1235 }
1236
1237 static void kvm_trim_features(uint32_t *features, uint32_t supported)
1238 {
1239 int i;
1240 uint32_t mask;
1241
1242 for (i = 0; i < 32; ++i) {
1243 mask = 1U << i;
1244 if ((*features & mask) && !(supported & mask)) {
1245 *features &= ~mask;
1246 }
1247 }
1248 }
1249
1250 int kvm_arch_init_vcpu(CPUState *cenv)
1251 {
1252 struct kvm_cpuid_entry2 cpuid_ent[100];
1253 #ifdef KVM_CPUID_SIGNATURE
1254 struct kvm_cpuid_entry2 *pv_ent;
1255 uint32_t signature[3];
1256 #endif
1257 int cpuid_nent = 0;
1258 CPUState copy;
1259 uint32_t i, j, limit;
1260
1261 qemu_kvm_load_lapic(cenv);
1262
1263
1264 #ifdef KVM_CPUID_SIGNATURE
1265 /* Paravirtualization CPUIDs */
1266 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1267 pv_ent = &cpuid_ent[cpuid_nent++];
1268 memset(pv_ent, 0, sizeof(*pv_ent));
1269 pv_ent->function = KVM_CPUID_SIGNATURE;
1270 pv_ent->eax = 0;
1271 pv_ent->ebx = signature[0];
1272 pv_ent->ecx = signature[1];
1273 pv_ent->edx = signature[2];
1274
1275 pv_ent = &cpuid_ent[cpuid_nent++];
1276 memset(pv_ent, 0, sizeof(*pv_ent));
1277 pv_ent->function = KVM_CPUID_FEATURES;
1278 pv_ent->eax = get_para_features(kvm_context);
1279 #endif
1280
1281 kvm_trim_features(&cenv->cpuid_features,
1282 kvm_arch_get_supported_cpuid(cenv, 1, R_EDX));
1283
1284 /* prevent the hypervisor bit from being cleared by the kernel */
1285 i = cenv->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
1286 kvm_trim_features(&cenv->cpuid_ext_features,
1287 kvm_arch_get_supported_cpuid(cenv, 1, R_ECX));
1288 cenv->cpuid_ext_features |= i;
1289
1290 kvm_trim_features(&cenv->cpuid_ext2_features,
1291 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_EDX));
1292 kvm_trim_features(&cenv->cpuid_ext3_features,
1293 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_ECX));
1294
1295 copy = *cenv;
1296
1297 copy.regs[R_EAX] = 0;
1298 qemu_kvm_cpuid_on_env(&copy);
1299 limit = copy.regs[R_EAX];
1300
1301 for (i = 0; i <= limit; ++i) {
1302 if (i == 4 || i == 0xb || i == 0xd) {
1303 for (j = 0; ; ++j) {
1304 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
1305
1306 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1307 cpuid_ent[cpuid_nent].index = j;
1308
1309 cpuid_nent++;
1310
1311 if (i == 4 && copy.regs[R_EAX] == 0)
1312 break;
1313 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
1314 break;
1315 if (i == 0xd && copy.regs[R_EAX] == 0)
1316 break;
1317 }
1318 } else
1319 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1320 }
1321
1322 copy.regs[R_EAX] = 0x80000000;
1323 qemu_kvm_cpuid_on_env(&copy);
1324 limit = copy.regs[R_EAX];
1325
1326 for (i = 0x80000000; i <= limit; ++i)
1327 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1328
1329 kvm_setup_cpuid2(cenv, cpuid_nent, cpuid_ent);
1330
1331 #ifdef KVM_CAP_MCE
1332 if (((cenv->cpuid_version >> 8)&0xF) >= 6
1333 && (cenv->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
1334 && kvm_check_extension(kvm_state, KVM_CAP_MCE) > 0) {
1335 uint64_t mcg_cap;
1336 int banks;
1337
1338 if (kvm_get_mce_cap_supported(kvm_context, &mcg_cap, &banks))
1339 perror("kvm_get_mce_cap_supported FAILED");
1340 else {
1341 if (banks > MCE_BANKS_DEF)
1342 banks = MCE_BANKS_DEF;
1343 mcg_cap &= MCE_CAP_DEF;
1344 mcg_cap |= banks;
1345 if (kvm_setup_mce(cenv, &mcg_cap))
1346 perror("kvm_setup_mce FAILED");
1347 else
1348 cenv->mcg_cap = mcg_cap;
1349 }
1350 }
1351 #endif
1352
1353 return 0;
1354 }
1355
1356 int kvm_arch_halt(CPUState *env)
1357 {
1358
1359 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1360 (env->eflags & IF_MASK)) &&
1361 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1362 env->halted = 1;
1363 }
1364 return 1;
1365 }
1366
1367 void kvm_arch_pre_kvm_run(void *opaque, CPUState *env)
1368 {
1369 if (!kvm_irqchip_in_kernel())
1370 kvm_set_cr8(env, cpu_get_apic_tpr(env));
1371 }
1372
1373 void kvm_arch_post_kvm_run(void *opaque, CPUState *env)
1374 {
1375 cpu_single_env = env;
1376
1377 env->eflags = kvm_get_interrupt_flag(env)
1378 ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
1379
1380 cpu_set_apic_tpr(env, kvm_get_cr8(env));
1381 cpu_set_apic_base(env, kvm_get_apic_base(env));
1382 }
1383
1384 int kvm_arch_has_work(CPUState *env)
1385 {
1386 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1387 (env->eflags & IF_MASK)) ||
1388 (env->interrupt_request & CPU_INTERRUPT_NMI))
1389 return 1;
1390 return 0;
1391 }
1392
1393 int kvm_arch_try_push_interrupts(void *opaque)
1394 {
1395 CPUState *env = cpu_single_env;
1396 int r, irq;
1397
1398 if (kvm_is_ready_for_interrupt_injection(env) &&
1399 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1400 (env->eflags & IF_MASK)) {
1401 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1402 irq = cpu_get_pic_interrupt(env);
1403 if (irq >= 0) {
1404 r = kvm_inject_irq(env, irq);
1405 if (r < 0)
1406 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
1407 }
1408 }
1409
1410 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
1411 }
1412
1413 #ifdef KVM_CAP_USER_NMI
1414 void kvm_arch_push_nmi(void *opaque)
1415 {
1416 CPUState *env = cpu_single_env;
1417 int r;
1418
1419 if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
1420 return;
1421
1422 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1423 r = kvm_inject_nmi(env);
1424 if (r < 0)
1425 printf("cpu %d fail inject NMI\n", env->cpu_index);
1426 }
1427 #endif /* KVM_CAP_USER_NMI */
1428
1429 void kvm_arch_cpu_reset(CPUState *env)
1430 {
1431 kvm_arch_load_regs(env);
1432 if (!cpu_is_bsp(env)) {
1433 if (kvm_irqchip_in_kernel()) {
1434 #ifdef KVM_CAP_MP_STATE
1435 kvm_reset_mpstate(env);
1436 #endif
1437 } else {
1438 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1439 env->halted = 1;
1440 }
1441 }
1442 }
1443
1444 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1445 {
1446 uint8_t int3 = 0xcc;
1447
1448 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1449 cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
1450 return -EINVAL;
1451 return 0;
1452 }
1453
1454 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1455 {
1456 uint8_t int3;
1457
1458 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1459 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1460 return -EINVAL;
1461 return 0;
1462 }
1463
1464 #ifdef KVM_CAP_SET_GUEST_DEBUG
1465 static struct {
1466 target_ulong addr;
1467 int len;
1468 int type;
1469 } hw_breakpoint[4];
1470
1471 static int nb_hw_breakpoint;
1472
1473 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1474 {
1475 int n;
1476
1477 for (n = 0; n < nb_hw_breakpoint; n++)
1478 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1479 (hw_breakpoint[n].len == len || len == -1))
1480 return n;
1481 return -1;
1482 }
1483
1484 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1485 target_ulong len, int type)
1486 {
1487 switch (type) {
1488 case GDB_BREAKPOINT_HW:
1489 len = 1;
1490 break;
1491 case GDB_WATCHPOINT_WRITE:
1492 case GDB_WATCHPOINT_ACCESS:
1493 switch (len) {
1494 case 1:
1495 break;
1496 case 2:
1497 case 4:
1498 case 8:
1499 if (addr & (len - 1))
1500 return -EINVAL;
1501 break;
1502 default:
1503 return -EINVAL;
1504 }
1505 break;
1506 default:
1507 return -ENOSYS;
1508 }
1509
1510 if (nb_hw_breakpoint == 4)
1511 return -ENOBUFS;
1512
1513 if (find_hw_breakpoint(addr, len, type) >= 0)
1514 return -EEXIST;
1515
1516 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1517 hw_breakpoint[nb_hw_breakpoint].len = len;
1518 hw_breakpoint[nb_hw_breakpoint].type = type;
1519 nb_hw_breakpoint++;
1520
1521 return 0;
1522 }
1523
1524 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1525 target_ulong len, int type)
1526 {
1527 int n;
1528
1529 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1530 if (n < 0)
1531 return -ENOENT;
1532
1533 nb_hw_breakpoint--;
1534 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1535
1536 return 0;
1537 }
1538
1539 void kvm_arch_remove_all_hw_breakpoints(void)
1540 {
1541 nb_hw_breakpoint = 0;
1542 }
1543
1544 static CPUWatchpoint hw_watchpoint;
1545
1546 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1547 {
1548 int handle = 0;
1549 int n;
1550
1551 if (arch_info->exception == 1) {
1552 if (arch_info->dr6 & (1 << 14)) {
1553 if (cpu_single_env->singlestep_enabled)
1554 handle = 1;
1555 } else {
1556 for (n = 0; n < 4; n++)
1557 if (arch_info->dr6 & (1 << n))
1558 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1559 case 0x0:
1560 handle = 1;
1561 break;
1562 case 0x1:
1563 handle = 1;
1564 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1565 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1566 hw_watchpoint.flags = BP_MEM_WRITE;
1567 break;
1568 case 0x3:
1569 handle = 1;
1570 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1571 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1572 hw_watchpoint.flags = BP_MEM_ACCESS;
1573 break;
1574 }
1575 }
1576 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1577 handle = 1;
1578
1579 if (!handle)
1580 kvm_update_guest_debug(cpu_single_env,
1581 (arch_info->exception == 1) ?
1582 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1583
1584 return handle;
1585 }
1586
1587 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1588 {
1589 const uint8_t type_code[] = {
1590 [GDB_BREAKPOINT_HW] = 0x0,
1591 [GDB_WATCHPOINT_WRITE] = 0x1,
1592 [GDB_WATCHPOINT_ACCESS] = 0x3
1593 };
1594 const uint8_t len_code[] = {
1595 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1596 };
1597 int n;
1598
1599 if (kvm_sw_breakpoints_active(env))
1600 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1601
1602 if (nb_hw_breakpoint > 0) {
1603 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1604 dbg->arch.debugreg[7] = 0x0600;
1605 for (n = 0; n < nb_hw_breakpoint; n++) {
1606 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1607 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1608 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1609 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1610 }
1611 }
1612 }
1613 #endif
1614
1615 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
1616 void kvm_arch_do_ioperm(void *_data)
1617 {
1618 struct ioperm_data *data = _data;
1619 ioperm(data->start_port, data->num, data->turn_on);
1620 }
1621 #endif
1622
1623 /*
1624 * Setup x86 specific IRQ routing
1625 */
1626 int kvm_arch_init_irq_routing(void)
1627 {
1628 int i, r;
1629
1630 if (kvm_irqchip && kvm_has_gsi_routing(kvm_context)) {
1631 kvm_clear_gsi_routes(kvm_context);
1632 for (i = 0; i < 8; ++i) {
1633 if (i == 2)
1634 continue;
1635 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_MASTER, i);
1636 if (r < 0)
1637 return r;
1638 }
1639 for (i = 8; i < 16; ++i) {
1640 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
1641 if (r < 0)
1642 return r;
1643 }
1644 for (i = 0; i < 24; ++i) {
1645 if (i == 0) {
1646 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, 2);
1647 } else if (i != 2) {
1648 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i);
1649 }
1650 if (r < 0)
1651 return r;
1652 }
1653 kvm_commit_irq_routes(kvm_context);
1654 }
1655 return 0;
1656 }
1657
1658 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
1659 int reg)
1660 {
1661 return kvm_get_supported_cpuid(kvm_context, function, reg);
1662 }
1663
1664 void kvm_arch_process_irqchip_events(CPUState *env)
1665 {
1666 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1667 kvm_cpu_synchronize_state(env);
1668 do_cpu_init(env);
1669 }
1670 if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1671 kvm_cpu_synchronize_state(env);
1672 do_cpu_sipi(env);
1673 }
1674 }
AMD IOMMU emulation for KVM