hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "pc.h"
  21 #include "apic.h"
  22 #include "pci.h"
  23 #include "msix.h"
  24 #include "qemu-timer.h"
  25 #include "host-utils.h"
  26 #include "kvm.h"
  27
  28 //#define DEBUG_APIC
  29
  30 /* APIC Local Vector Table */
  31 #define APIC_LVT_TIMER   0
  32 #define APIC_LVT_THERMAL 1
  33 #define APIC_LVT_PERFORM 2
  34 #define APIC_LVT_LINT0   3
  35 #define APIC_LVT_LINT1   4
  36 #define APIC_LVT_ERROR   5
  37 #define APIC_LVT_NB      6
  38
  39 /* APIC delivery modes */
  40 #define APIC_DM_FIXED   0
  41 #define APIC_DM_LOWPRI  1
  42 #define APIC_DM_SMI     2
  43 #define APIC_DM_NMI     4
  44 #define APIC_DM_INIT    5
  45 #define APIC_DM_SIPI    6
  46 #define APIC_DM_EXTINT  7
  47
  48 /* APIC destination mode */
  49 #define APIC_DESTMODE_FLAT      0xf
  50 #define APIC_DESTMODE_CLUSTER   1
  51
  52 #define APIC_TRIGGER_EDGE  0
  53 #define APIC_TRIGGER_LEVEL 1
  54
  55 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  56 #define APIC_LVT_MASKED                 (1<<16)
  57 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  58 #define APIC_LVT_REMOTE_IRR             (1<<14)
  59 #define APIC_INPUT_POLARITY             (1<<13)
  60 #define APIC_SEND_PENDING               (1<<12)
  61
  62 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  63
  64 #define APIC_SV_ENABLE (1 << 8)
  65
  66 #define MAX_APICS 255
  67 #define MAX_APIC_WORDS 8
  68
  69 /* Intel APIC constants: from include/asm/msidef.h */
  70 #define MSI_DATA_VECTOR_SHIFT           0
  71 #define MSI_DATA_VECTOR_MASK            0x000000ff
  72 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  73 #define MSI_DATA_TRIGGER_SHIFT          15
  74 #define MSI_DATA_LEVEL_SHIFT            14
  75 #define MSI_ADDR_DEST_MODE_SHIFT        2
  76 #define MSI_ADDR_DEST_ID_SHIFT          12
  77 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  78
  79 #define MSI_ADDR_BASE                   0xfee00000
  80 #define MSI_ADDR_SIZE                   0x100000
  81
  82 typedef struct APICState {
  83     CPUState *cpu_env;
  84     uint32_t apicbase;
  85     uint8_t id;
  86     uint8_t arb_id;
  87     uint8_t tpr;
  88     uint32_t spurious_vec;
  89     uint8_t log_dest;
  90     uint8_t dest_mode;
  91     uint32_t isr[8];  /* in service register */
  92     uint32_t tmr[8];  /* trigger mode register */
  93     uint32_t irr[8]; /* interrupt request register */
  94     uint32_t lvt[APIC_LVT_NB];
  95     uint32_t esr; /* error register */
  96     uint32_t icr[2];
  97
  98     uint32_t divide_conf;
  99     int count_shift;
 100     uint32_t initial_count;
 101     int64_t initial_count_load_time, next_time;
 102     uint32_t idx;
 103     QEMUTimer *timer;
 104     int sipi_vector;
 105     int wait_for_sipi;
 106 } APICState;
 107
 108 static int apic_io_memory;
 109 static APICState *local_apics[MAX_APICS + 1];
 110 static int last_apic_idx = 0;
 111 static int apic_irq_delivered;
 112
 113
 114 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 115 static void apic_update_irq(APICState *s);
 116 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 117                                       uint8_t dest, uint8_t dest_mode);
 118
 119 /* Find first bit starting from msb */
 120 static int fls_bit(uint32_t value)
 121 {
 122     return 31 - clz32(value);
 123 }
 124
 125 /* Find first bit starting from lsb */
 126 static int ffs_bit(uint32_t value)
 127 {
 128     return ctz32(value);
 129 }
 130
 131 static inline void set_bit(uint32_t *tab, int index)
 132 {
 133     int i, mask;
 134     i = index >> 5;
 135     mask = 1 << (index & 0x1f);
 136     tab[i] |= mask;
 137 }
 138
 139 static inline void reset_bit(uint32_t *tab, int index)
 140 {
 141     int i, mask;
 142     i = index >> 5;
 143     mask = 1 << (index & 0x1f);
 144     tab[i] &= ~mask;
 145 }
 146
 147 static inline int get_bit(uint32_t *tab, int index)
 148 {
 149     int i, mask;
 150     i = index >> 5;
 151     mask = 1 << (index & 0x1f);
 152     return !!(tab[i] & mask);
 153 }
 154
 155 static void apic_local_deliver(CPUState *env, int vector)
 156 {
 157     APICState *s = env->apic_state;
 158     uint32_t lvt = s->lvt[vector];
 159     int trigger_mode;
 160
 161     if (lvt & APIC_LVT_MASKED)
 162         return;
 163
 164     switch ((lvt >> 8) & 7) {
 165     case APIC_DM_SMI:
 166         cpu_interrupt(env, CPU_INTERRUPT_SMI);
 167         break;
 168
 169     case APIC_DM_NMI:
 170         cpu_interrupt(env, CPU_INTERRUPT_NMI);
 171         break;
 172
 173     case APIC_DM_EXTINT:
 174         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 175         break;
 176
 177     case APIC_DM_FIXED:
 178         trigger_mode = APIC_TRIGGER_EDGE;
 179         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 180             (lvt & APIC_LVT_LEVEL_TRIGGER))
 181             trigger_mode = APIC_TRIGGER_LEVEL;
 182         apic_set_irq(s, lvt & 0xff, trigger_mode);
 183     }
 184 }
 185
 186 void apic_deliver_pic_intr(CPUState *env, int level)
 187 {
 188     if (level)
 189         apic_local_deliver(env, APIC_LVT_LINT0);
 190     else {
 191         APICState *s = env->apic_state;
 192         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 193
 194         switch ((lvt >> 8) & 7) {
 195         case APIC_DM_FIXED:
 196             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 197                 break;
 198             reset_bit(s->irr, lvt & 0xff);
 199             /* fall through */
 200         case APIC_DM_EXTINT:
 201             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 202             break;
 203         }
 204     }
 205 }
 206
 207 #define foreach_apic(apic, deliver_bitmask, code) \
 208 {\
 209     int __i, __j, __mask;\
 210     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 211         __mask = deliver_bitmask[__i];\
 212         if (__mask) {\
 213             for(__j = 0; __j < 32; __j++) {\
 214                 if (__mask & (1 << __j)) {\
 215                     apic = local_apics[__i * 32 + __j];\
 216                     if (apic) {\
 217                         code;\
 218                     }\
 219                 }\
 220             }\
 221         }\
 222     }\
 223 }
 224
 225 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 226                              uint8_t delivery_mode,
 227                              uint8_t vector_num, uint8_t polarity,
 228                              uint8_t trigger_mode)
 229 {
 230     APICState *apic_iter;
 231
 232     switch (delivery_mode) {
 233         case APIC_DM_LOWPRI:
 234             /* XXX: search for focus processor, arbitration */
 235             {
 236                 int i, d;
 237                 d = -1;
 238                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 239                     if (deliver_bitmask[i]) {
 240                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 241                         break;
 242                     }
 243                 }
 244                 if (d >= 0) {
 245                     apic_iter = local_apics[d];
 246                     if (apic_iter) {
 247                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 248                     }
 249                 }
 250             }
 251             return;
 252
 253         case APIC_DM_FIXED:
 254             break;
 255
 256         case APIC_DM_SMI:
 257             foreach_apic(apic_iter, deliver_bitmask,
 258                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 259             return;
 260
 261         case APIC_DM_NMI:
 262             foreach_apic(apic_iter, deliver_bitmask,
 263                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 264             return;
 265
 266         case APIC_DM_INIT:
 267             /* normal INIT IPI sent to processors */
 268             foreach_apic(apic_iter, deliver_bitmask,
 269                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 270             return;
 271
 272         case APIC_DM_EXTINT:
 273             /* handled in I/O APIC code */
 274             break;
 275
 276         default:
 277             return;
 278     }
 279
 280     foreach_apic(apic_iter, deliver_bitmask,
 281                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 282 }
 283
 284 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 285                       uint8_t delivery_mode, uint8_t vector_num,
 286                       uint8_t polarity, uint8_t trigger_mode)
 287 {
 288     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 289
 290     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 291     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 292                      trigger_mode);
 293 }
 294
 295 void cpu_set_apic_base(CPUState *env, uint64_t val)
 296 {
 297     APICState *s = env->apic_state;
 298 #ifdef DEBUG_APIC
 299     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
 300 #endif
 301     if (!s)
 302         return;
 303     if (kvm_enabled() && kvm_irqchip_in_kernel())
 304         s->apicbase = val;
 305     else
 306         s->apicbase = (val & 0xfffff000) |
 307             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 308     /* if disabled, cannot be enabled again */
 309     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 310         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 311         env->cpuid_features &= ~CPUID_APIC;
 312         s->spurious_vec &= ~APIC_SV_ENABLE;
 313     }
 314 }
 315
 316 uint64_t cpu_get_apic_base(CPUState *env)
 317 {
 318     APICState *s = env->apic_state;
 319 #ifdef DEBUG_APIC
 320     printf("cpu_get_apic_base: %016" PRIx64 "\n",
 321            s ? (uint64_t)s->apicbase: 0);
 322 #endif
 323     return s ? s->apicbase : 0;
 324 }
 325
 326 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 327 {
 328     APICState *s = env->apic_state;
 329     if (!s)
 330         return;
 331     s->tpr = (val & 0x0f) << 4;
 332     apic_update_irq(s);
 333 }
 334
 335 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 336 {
 337     APICState *s = env->apic_state;
 338     return s ? s->tpr >> 4 : 0;
 339 }
 340
 341 /* return -1 if no bit is set */
 342 static int get_highest_priority_int(uint32_t *tab)
 343 {
 344     int i;
 345     for(i = 7; i >= 0; i--) {
 346         if (tab[i] != 0) {
 347             return i * 32 + fls_bit(tab[i]);
 348         }
 349     }
 350     return -1;
 351 }
 352
 353 static int apic_get_ppr(APICState *s)
 354 {
 355     int tpr, isrv, ppr;
 356
 357     tpr = (s->tpr >> 4);
 358     isrv = get_highest_priority_int(s->isr);
 359     if (isrv < 0)
 360         isrv = 0;
 361     isrv >>= 4;
 362     if (tpr >= isrv)
 363         ppr = s->tpr;
 364     else
 365         ppr = isrv << 4;
 366     return ppr;
 367 }
 368
 369 static int apic_get_arb_pri(APICState *s)
 370 {
 371     /* XXX: arbitration */
 372     return 0;
 373 }
 374
 375 /* signal the CPU if an irq is pending */
 376 static void apic_update_irq(APICState *s)
 377 {
 378     int irrv, ppr;
 379     if (!(s->spurious_vec & APIC_SV_ENABLE))
 380         return;
 381     irrv = get_highest_priority_int(s->irr);
 382     if (irrv < 0)
 383         return;
 384     ppr = apic_get_ppr(s);
 385     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 386         return;
 387     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 388 }
 389
 390 void apic_reset_irq_delivered(void)
 391 {
 392     apic_irq_delivered = 0;
 393 }
 394
 395 int apic_get_irq_delivered(void)
 396 {
 397     return apic_irq_delivered;
 398 }
 399
 400 void apic_set_irq_delivered(void)
 401 {
 402     apic_irq_delivered = 1;
 403 }
 404
 405 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 406 {
 407     apic_irq_delivered += !get_bit(s->irr, vector_num);
 408
 409     set_bit(s->irr, vector_num);
 410     if (trigger_mode)
 411         set_bit(s->tmr, vector_num);
 412     else
 413         reset_bit(s->tmr, vector_num);
 414     apic_update_irq(s);
 415 }
 416
 417 static void apic_eoi(APICState *s)
 418 {
 419     int isrv;
 420     isrv = get_highest_priority_int(s->isr);
 421     if (isrv < 0)
 422         return;
 423     reset_bit(s->isr, isrv);
 424     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 425             set the remote IRR bit for level triggered interrupts. */
 426     apic_update_irq(s);
 427 }
 428
 429 static int apic_find_dest(uint8_t dest)
 430 {
 431     APICState *apic = local_apics[dest];
 432     int i;
 433
 434     if (apic && apic->id == dest)
 435         return dest;  /* shortcut in case apic->id == apic->idx */
 436
 437     for (i = 0; i < MAX_APICS; i++) {
 438         apic = local_apics[i];
 439         if (apic && apic->id == dest)
 440             return i;
 441     }
 442
 443     return -1;
 444 }
 445
 446 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 447                                       uint8_t dest, uint8_t dest_mode)
 448 {
 449     APICState *apic_iter;
 450     int i;
 451
 452     if (dest_mode == 0) {
 453         if (dest == 0xff) {
 454             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 455         } else {
 456             int idx = apic_find_dest(dest);
 457             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 458             if (idx >= 0)
 459                 set_bit(deliver_bitmask, idx);
 460         }
 461     } else {
 462         /* XXX: cluster mode */
 463         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 464         for(i = 0; i < MAX_APICS; i++) {
 465             apic_iter = local_apics[i];
 466             if (apic_iter) {
 467                 if (apic_iter->dest_mode == 0xf) {
 468                     if (dest & apic_iter->log_dest)
 469                         set_bit(deliver_bitmask, i);
 470                 } else if (apic_iter->dest_mode == 0x0) {
 471                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 472                         (dest & apic_iter->log_dest & 0x0f)) {
 473                         set_bit(deliver_bitmask, i);
 474                     }
 475                 }
 476             }
 477         }
 478     }
 479 }
 480
 481
 482 void apic_init_reset(CPUState *env)
 483 {
 484     APICState *s = env->apic_state;
 485     int i;
 486
 487     if (!s)
 488         return;
 489
 490     s->tpr = 0;
 491     s->spurious_vec = 0xff;
 492     s->log_dest = 0;
 493     s->dest_mode = 0xf;
 494     memset(s->isr, 0, sizeof(s->isr));
 495     memset(s->tmr, 0, sizeof(s->tmr));
 496     memset(s->irr, 0, sizeof(s->irr));
 497     for(i = 0; i < APIC_LVT_NB; i++)
 498         s->lvt[i] = 1 << 16; /* mask LVT */
 499     s->esr = 0;
 500     memset(s->icr, 0, sizeof(s->icr));
 501     s->divide_conf = 0;
 502     s->count_shift = 0;
 503     s->initial_count = 0;
 504     s->initial_count_load_time = 0;
 505     s->next_time = 0;
 506     s->wait_for_sipi = 1;
 507
 508     env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP);
 509 }
 510
 511 static void apic_startup(APICState *s, int vector_num)
 512 {
 513     s->sipi_vector = vector_num;
 514     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 515 }
 516
 517 void apic_sipi(CPUState *env)
 518 {
 519     APICState *s = env->apic_state;
 520
 521     cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI);
 522
 523     if (!s->wait_for_sipi)
 524         return;
 525
 526     env->eip = 0;
 527     cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12,
 528                            env->segs[R_CS].limit, env->segs[R_CS].flags);
 529     env->halted = 0;
 530     s->wait_for_sipi = 0;
 531 }
 532
 533 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 534                          uint8_t delivery_mode, uint8_t vector_num,
 535                          uint8_t polarity, uint8_t trigger_mode)
 536 {
 537     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 538     int dest_shorthand = (s->icr[0] >> 18) & 3;
 539     APICState *apic_iter;
 540
 541     switch (dest_shorthand) {
 542     case 0:
 543         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 544         break;
 545     case 1:
 546         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 547         set_bit(deliver_bitmask, s->idx);
 548         break;
 549     case 2:
 550         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 551         break;
 552     case 3:
 553         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 554         reset_bit(deliver_bitmask, s->idx);
 555         break;
 556     }
 557
 558     switch (delivery_mode) {
 559         case APIC_DM_INIT:
 560             {
 561                 int trig_mode = (s->icr[0] >> 15) & 1;
 562                 int level = (s->icr[0] >> 14) & 1;
 563                 if (level == 0 && trig_mode == 1) {
 564                     foreach_apic(apic_iter, deliver_bitmask,
 565                                  apic_iter->arb_id = apic_iter->id );
 566                     return;
 567                 }
 568             }
 569             break;
 570
 571         case APIC_DM_SIPI:
 572             foreach_apic(apic_iter, deliver_bitmask,
 573                          apic_startup(apic_iter, vector_num) );
 574             return;
 575     }
 576
 577     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 578                      trigger_mode);
 579 }
 580
 581 int apic_get_interrupt(CPUState *env)
 582 {
 583     APICState *s = env->apic_state;
 584     int intno;
 585
 586     /* if the APIC is installed or enabled, we let the 8259 handle the
 587        IRQs */
 588     if (!s)
 589         return -1;
 590     if (!(s->spurious_vec & APIC_SV_ENABLE))
 591         return -1;
 592
 593     /* XXX: spurious IRQ handling */
 594     intno = get_highest_priority_int(s->irr);
 595     if (intno < 0)
 596         return -1;
 597     if (s->tpr && intno <= s->tpr)
 598         return s->spurious_vec & 0xff;
 599     reset_bit(s->irr, intno);
 600     set_bit(s->isr, intno);
 601     apic_update_irq(s);
 602     return intno;
 603 }
 604
 605 int apic_accept_pic_intr(CPUState *env)
 606 {
 607     APICState *s = env->apic_state;
 608     uint32_t lvt0;
 609
 610     if (!s)
 611         return -1;
 612
 613     lvt0 = s->lvt[APIC_LVT_LINT0];
 614
 615     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 616         (lvt0 & APIC_LVT_MASKED) == 0)
 617         return 1;
 618
 619     return 0;
 620 }
 621
 622 static uint32_t apic_get_current_count(APICState *s)
 623 {
 624     int64_t d;
 625     uint32_t val;
 626     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 627         s->count_shift;
 628     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 629         /* periodic */
 630         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 631     } else {
 632         if (d >= s->initial_count)
 633             val = 0;
 634         else
 635             val = s->initial_count - d;
 636     }
 637     return val;
 638 }
 639
 640 static void apic_timer_update(APICState *s, int64_t current_time)
 641 {
 642     int64_t next_time, d;
 643
 644     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 645         d = (current_time - s->initial_count_load_time) >>
 646             s->count_shift;
 647         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 648             if (!s->initial_count)
 649                 goto no_timer;
 650             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 651         } else {
 652             if (d >= s->initial_count)
 653                 goto no_timer;
 654             d = (uint64_t)s->initial_count + 1;
 655         }
 656         next_time = s->initial_count_load_time + (d << s->count_shift);
 657         qemu_mod_timer(s->timer, next_time);
 658         s->next_time = next_time;
 659     } else {
 660     no_timer:
 661         qemu_del_timer(s->timer);
 662     }
 663 }
 664
 665 static void apic_timer(void *opaque)
 666 {
 667     APICState *s = opaque;
 668
 669     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
 670     apic_timer_update(s, s->next_time);
 671 }
 672
 673 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 674 {
 675     return 0;
 676 }
 677
 678 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 679 {
 680     return 0;
 681 }
 682
 683 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 684 {
 685 }
 686
 687 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 688 {
 689 }
 690
 691 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 692 {
 693     CPUState *env;
 694     APICState *s;
 695     uint32_t val;
 696     int index;
 697
 698     env = cpu_single_env;
 699     if (!env)
 700         return 0;
 701     s = env->apic_state;
 702
 703     index = (addr >> 4) & 0xff;
 704     switch(index) {
 705     case 0x02: /* id */
 706         val = s->id << 24;
 707         break;
 708     case 0x03: /* version */
 709         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 710         break;
 711     case 0x08:
 712         val = s->tpr;
 713         break;
 714     case 0x09:
 715         val = apic_get_arb_pri(s);
 716         break;
 717     case 0x0a:
 718         /* ppr */
 719         val = apic_get_ppr(s);
 720         break;
 721     case 0x0b:
 722         val = 0;
 723         break;
 724     case 0x0d:
 725         val = s->log_dest << 24;
 726         break;
 727     case 0x0e:
 728         val = s->dest_mode << 28;
 729         break;
 730     case 0x0f:
 731         val = s->spurious_vec;
 732         break;
 733     case 0x10 ... 0x17:
 734         val = s->isr[index & 7];
 735         break;
 736     case 0x18 ... 0x1f:
 737         val = s->tmr[index & 7];
 738         break;
 739     case 0x20 ... 0x27:
 740         val = s->irr[index & 7];
 741         break;
 742     case 0x28:
 743         val = s->esr;
 744         break;
 745     case 0x30:
 746     case 0x31:
 747         val = s->icr[index & 1];
 748         break;
 749     case 0x32 ... 0x37:
 750         val = s->lvt[index - 0x32];
 751         break;
 752     case 0x38:
 753         val = s->initial_count;
 754         break;
 755     case 0x39:
 756         val = apic_get_current_count(s);
 757         break;
 758     case 0x3e:
 759         val = s->divide_conf;
 760         break;
 761     default:
 762         s->esr |= ESR_ILLEGAL_ADDRESS;
 763         val = 0;
 764         break;
 765     }
 766 #ifdef DEBUG_APIC
 767     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
 768 #endif
 769     return val;
 770 }
 771
 772 static void apic_send_msi(target_phys_addr_t addr, uint32 data)
 773 {
 774     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 775     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 776     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 777     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 778     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 779     /* XXX: Ignore redirection hint. */
 780     apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
 781 }
 782
 783 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 784 {
 785     CPUState *env;
 786     APICState *s;
 787     int index = (addr >> 4) & 0xff;
 788     if (addr > 0xfff || !index) {
 789         /* MSI and MMIO APIC are at the same memory location,
 790          * but actually not on the global bus: MSI is on PCI bus
 791          * APIC is connected directly to the CPU.
 792          * Mapping them on the global bus happens to work because
 793          * MSI registers are reserved in APIC MMIO and vice versa. */
 794         apic_send_msi(addr, val);
 795         return;
 796     }
 797
 798     env = cpu_single_env;
 799     if (!env)
 800         return;
 801     s = env->apic_state;
 802
 803 #ifdef DEBUG_APIC
 804     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 805 #endif
 806
 807     switch(index) {
 808     case 0x02:
 809         s->id = (val >> 24);
 810         break;
 811     case 0x03:
 812         break;
 813     case 0x08:
 814         s->tpr = val;
 815         apic_update_irq(s);
 816         break;
 817     case 0x09:
 818     case 0x0a:
 819         break;
 820     case 0x0b: /* EOI */
 821         apic_eoi(s);
 822         break;
 823     case 0x0d:
 824         s->log_dest = val >> 24;
 825         break;
 826     case 0x0e:
 827         s->dest_mode = val >> 28;
 828         break;
 829     case 0x0f:
 830         s->spurious_vec = val & 0x1ff;
 831         apic_update_irq(s);
 832         break;
 833     case 0x10 ... 0x17:
 834     case 0x18 ... 0x1f:
 835     case 0x20 ... 0x27:
 836     case 0x28:
 837         break;
 838     case 0x30:
 839         s->icr[0] = val;
 840         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 841                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 842                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 843         break;
 844     case 0x31:
 845         s->icr[1] = val;
 846         break;
 847     case 0x32 ... 0x37:
 848         {
 849             int n = index - 0x32;
 850             s->lvt[n] = val;
 851             if (n == APIC_LVT_TIMER)
 852                 apic_timer_update(s, qemu_get_clock(vm_clock));
 853         }
 854         break;
 855     case 0x38:
 856         s->initial_count = val;
 857         s->initial_count_load_time = qemu_get_clock(vm_clock);
 858         apic_timer_update(s, s->initial_count_load_time);
 859         break;
 860     case 0x39:
 861         break;
 862     case 0x3e:
 863         {
 864             int v;
 865             s->divide_conf = val & 0xb;
 866             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 867             s->count_shift = (v + 1) & 7;
 868         }
 869         break;
 870     default:
 871         s->esr |= ESR_ILLEGAL_ADDRESS;
 872         break;
 873     }
 874 }
 875
 876 #ifdef KVM_CAP_IRQCHIP
 877
 878 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 879 {
 880     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 881 }
 882
 883 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 884                                  int reg_id, uint32_t val)
 885 {
 886     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 887 }
 888
 889 static void kvm_kernel_lapic_save_to_user(APICState *s)
 890 {
 891     struct kvm_lapic_state apic;
 892     struct kvm_lapic_state *kapic = &apic;
 893     int i, v;
 894
 895     kvm_get_lapic(s->cpu_env, kapic);
 896
 897     s->id = kapic_reg(kapic, 0x2) >> 24;
 898     s->tpr = kapic_reg(kapic, 0x8);
 899     s->arb_id = kapic_reg(kapic, 0x9);
 900     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 901     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 902     s->spurious_vec = kapic_reg(kapic, 0xf);
 903     for (i = 0; i < 8; i++) {
 904         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 905         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 906         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 907     }
 908     s->esr = kapic_reg(kapic, 0x28);
 909     s->icr[0] = kapic_reg(kapic, 0x30);
 910     s->icr[1] = kapic_reg(kapic, 0x31);
 911     for (i = 0; i < APIC_LVT_NB; i++)
 912         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 913     s->initial_count = kapic_reg(kapic, 0x38);
 914     s->divide_conf = kapic_reg(kapic, 0x3e);
 915
 916     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 917     s->count_shift = (v + 1) & 7;
 918
 919     s->initial_count_load_time = qemu_get_clock(vm_clock);
 920     apic_timer_update(s, s->initial_count_load_time);
 921 }
 922
 923 static void kvm_kernel_lapic_load_from_user(APICState *s)
 924 {
 925     struct kvm_lapic_state apic;
 926     struct kvm_lapic_state *klapic = &apic;
 927     int i;
 928
 929     memset(klapic, 0, sizeof apic);
 930     kapic_set_reg(klapic, 0x2, s->id << 24);
 931     kapic_set_reg(klapic, 0x8, s->tpr);
 932     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 933     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 934     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 935     for (i = 0; i < 8; i++) {
 936         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 937         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 938         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 939     }
 940     kapic_set_reg(klapic, 0x28, s->esr);
 941     kapic_set_reg(klapic, 0x30, s->icr[0]);
 942     kapic_set_reg(klapic, 0x31, s->icr[1]);
 943     for (i = 0; i < APIC_LVT_NB; i++)
 944         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 945     kapic_set_reg(klapic, 0x38, s->initial_count);
 946     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 947
 948     kvm_set_lapic(s->cpu_env, klapic);
 949 }
 950
 951 #endif
 952
 953 void kvm_load_lapic(CPUState *env)
 954 {
 955 #ifdef KVM_CAP_IRQCHIP
 956     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 957         kvm_kernel_lapic_load_from_user(env->apic_state);
 958     }
 959 #endif
 960 }
 961
 962 void kvm_save_lapic(CPUState *env)
 963 {
 964 #ifdef KVM_CAP_IRQCHIP
 965     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 966         kvm_kernel_lapic_save_to_user(env->apic_state);
 967     }
 968 #endif
 969 }
 970
 971 /* This function is only used for old state version 1 and 2 */
 972 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 973 {
 974     APICState *s = opaque;
 975     int i;
 976
 977     if (version_id > 2)
 978         return -EINVAL;
 979
 980     /* XXX: what if the base changes? (registered memory regions) */
 981     qemu_get_be32s(f, &s->apicbase);
 982     qemu_get_8s(f, &s->id);
 983     qemu_get_8s(f, &s->arb_id);
 984     qemu_get_8s(f, &s->tpr);
 985     qemu_get_be32s(f, &s->spurious_vec);
 986     qemu_get_8s(f, &s->log_dest);
 987     qemu_get_8s(f, &s->dest_mode);
 988     for (i = 0; i < 8; i++) {
 989         qemu_get_be32s(f, &s->isr[i]);
 990         qemu_get_be32s(f, &s->tmr[i]);
 991         qemu_get_be32s(f, &s->irr[i]);
 992     }
 993     for (i = 0; i < APIC_LVT_NB; i++) {
 994         qemu_get_be32s(f, &s->lvt[i]);
 995     }
 996     qemu_get_be32s(f, &s->esr);
 997     qemu_get_be32s(f, &s->icr[0]);
 998     qemu_get_be32s(f, &s->icr[1]);
 999     qemu_get_be32s(f, &s->divide_conf);
1000     s->count_shift=qemu_get_be32(f);
1001     qemu_get_be32s(f, &s->initial_count);
1002     s->initial_count_load_time=qemu_get_be64(f);
1003     s->next_time=qemu_get_be64(f);
1004
1005     if (version_id >= 2)
1006         qemu_get_timer(f, s->timer);
1007     return 0;
1008 }
1009
1010 static const VMStateDescription vmstate_apic = {
1011     .name = "apic",
1012     .version_id = 3,
1013     .minimum_version_id = 3,
1014     .minimum_version_id_old = 1,
1015     .load_state_old = apic_load_old,
1016     .fields      = (VMStateField []) {
1017         VMSTATE_UINT32(apicbase, APICState),
1018         VMSTATE_UINT8(id, APICState),
1019         VMSTATE_UINT8(arb_id, APICState),
1020         VMSTATE_UINT8(tpr, APICState),
1021         VMSTATE_UINT32(spurious_vec, APICState),
1022         VMSTATE_UINT8(log_dest, APICState),
1023         VMSTATE_UINT8(dest_mode, APICState),
1024         VMSTATE_UINT32_ARRAY(isr, APICState, 8),
1025         VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
1026         VMSTATE_UINT32_ARRAY(irr, APICState, 8),
1027         VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
1028         VMSTATE_UINT32(esr, APICState),
1029         VMSTATE_UINT32_ARRAY(icr, APICState, 2),
1030         VMSTATE_UINT32(divide_conf, APICState),
1031         VMSTATE_INT32(count_shift, APICState),
1032         VMSTATE_UINT32(initial_count, APICState),
1033         VMSTATE_INT64(initial_count_load_time, APICState),
1034         VMSTATE_INT64(next_time, APICState),
1035         VMSTATE_TIMER(timer, APICState),
1036         VMSTATE_END_OF_LIST()
1037     }
1038 };
1039
1040 static void apic_reset(void *opaque)
1041 {
1042     APICState *s = opaque;
1043     int bsp;
1044
1045     bsp = cpu_is_bsp(s->cpu_env);
1046     s->apicbase = 0xfee00000 |
1047         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
1048
1049     cpu_reset(s->cpu_env);
1050     apic_init_reset(s->cpu_env);
1051
1052     if (bsp) {
1053         /*
1054          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1055          * time typically by BIOS, so PIC interrupt can be delivered to the
1056          * processor when local APIC is enabled.
1057          */
1058         s->lvt[APIC_LVT_LINT0] = 0x700;
1059     }
1060 }
1061
1062 static CPUReadMemoryFunc * const apic_mem_read[3] = {
1063     apic_mem_readb,
1064     apic_mem_readw,
1065     apic_mem_readl,
1066 };
1067
1068 static CPUWriteMemoryFunc * const apic_mem_write[3] = {
1069     apic_mem_writeb,
1070     apic_mem_writew,
1071     apic_mem_writel,
1072 };
1073
1074 int apic_init(CPUState *env)
1075 {
1076     APICState *s;
1077
1078     if (last_apic_idx >= MAX_APICS)
1079         return -1;
1080     s = qemu_mallocz(sizeof(APICState));
1081     env->apic_state = s;
1082     s->idx = last_apic_idx++;
1083     s->id = env->cpuid_apic_id;
1084     s->cpu_env = env;
1085
1086     msix_supported = 1;
1087
1088     /* XXX: mapping more APICs at the same memory location */
1089     if (apic_io_memory == 0) {
1090         /* NOTE: the APIC is directly connected to the CPU - it is not
1091            on the global memory bus. */
1092         apic_io_memory = cpu_register_io_memory(apic_mem_read,
1093                                                 apic_mem_write, NULL);
1094         /* XXX: what if the base changes? */
1095         cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE,
1096                                      apic_io_memory);
1097     }
1098     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1099
1100     vmstate_register(s->idx, &vmstate_apic, s);
1101     qemu_register_reset(apic_reset, s);
1102
1103     local_apics[s->idx] = s;
1104     return 0;
1105 }