hw/ne2000.c

   1 /*
   2  * QEMU NE2000 emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "net.h"
  28
  29 /* debug NE2000 card */
  30 //#define DEBUG_NE2000
  31
  32 #define MAX_ETH_FRAME_SIZE 1514
  33
  34 #define E8390_CMD       0x00  /* The command register (for all pages) */
  35 /* Page 0 register offsets. */
  36 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
  37 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
  38 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
  39 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
  40 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
  41 #define EN0_TSR         0x04    /* Transmit status reg RD */
  42 #define EN0_TPSR        0x04    /* Transmit starting page WR */
  43 #define EN0_NCR         0x05    /* Number of collision reg RD */
  44 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
  45 #define EN0_FIFO        0x06    /* FIFO RD */
  46 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
  47 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
  48 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
  49 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
  50 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
  51 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
  52 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
  53 #define EN0_RTL8029ID0  0x0a    /* Realtek ID byte #1 RD */
  54 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
  55 #define EN0_RTL8029ID1  0x0b    /* Realtek ID byte #2 RD */
  56 #define EN0_RSR         0x0c    /* rx status reg RD */
  57 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
  58 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
  59 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
  60 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
  61 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
  62 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
  63 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
  64
  65 #define EN1_PHYS        0x11
  66 #define EN1_CURPAG      0x17
  67 #define EN1_MULT        0x18
  68
  69 #define EN2_STARTPG     0x21    /* Starting page of ring bfr RD */
  70 #define EN2_STOPPG      0x22    /* Ending page +1 of ring bfr RD */
  71
  72 #define EN3_CONFIG0     0x33
  73 #define EN3_CONFIG1     0x34
  74 #define EN3_CONFIG2     0x35
  75 #define EN3_CONFIG3     0x36
  76
  77 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  78 #define E8390_STOP      0x01    /* Stop and reset the chip */
  79 #define E8390_START     0x02    /* Start the chip, clear reset */
  80 #define E8390_TRANS     0x04    /* Transmit a frame */
  81 #define E8390_RREAD     0x08    /* Remote read */
  82 #define E8390_RWRITE    0x10    /* Remote write  */
  83 #define E8390_NODMA     0x20    /* Remote DMA */
  84 #define E8390_PAGE0     0x00    /* Select page chip registers */
  85 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  86 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  87
  88 /* Bits in EN0_ISR - Interrupt status register */
  89 #define ENISR_RX        0x01    /* Receiver, no error */
  90 #define ENISR_TX        0x02    /* Transmitter, no error */
  91 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
  92 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
  93 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
  94 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
  95 #define ENISR_RDC       0x40    /* remote dma complete */
  96 #define ENISR_RESET     0x80    /* Reset completed */
  97 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
  98
  99 /* Bits in received packet status byte and EN0_RSR*/
 100 #define ENRSR_RXOK      0x01    /* Received a good packet */
 101 #define ENRSR_CRC       0x02    /* CRC error */
 102 #define ENRSR_FAE       0x04    /* frame alignment error */
 103 #define ENRSR_FO        0x08    /* FIFO overrun */
 104 #define ENRSR_MPA       0x10    /* missed pkt */
 105 #define ENRSR_PHY       0x20    /* physical/multicast address */
 106 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
 107 #define ENRSR_DEF       0x80    /* deferring */
 108
 109 /* Transmitted packet status, EN0_TSR. */
 110 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
 111 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
 112 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 113 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 114 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 115 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 116 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 117 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 118
 119 #define NE2000_PMEM_SIZE    (32*1024)
 120 #define NE2000_PMEM_START   (16*1024)
 121 #define NE2000_PMEM_END     (NE2000_PMEM_SIZE+NE2000_PMEM_START)
 122 #define NE2000_MEM_SIZE     NE2000_PMEM_END
 123
 124 typedef struct NE2000State {
 125     uint8_t cmd;
 126     uint32_t start;
 127     uint32_t stop;
 128     uint8_t boundary;
 129     uint8_t tsr;
 130     uint8_t tpsr;
 131     uint16_t tcnt;
 132     uint16_t rcnt;
 133     uint32_t rsar;
 134     uint8_t rsr;
 135     uint8_t rxcr;
 136     uint8_t isr;
 137     uint8_t dcfg;
 138     uint8_t imr;
 139     uint8_t phys[6]; /* mac address */
 140     uint8_t curpag;
 141     uint8_t mult[8]; /* multicast mask array */
 142     qemu_irq irq;
 143     int isa_io_base;
 144     VLANClientState *vc;
 145     uint8_t macaddr[6];
 146     uint8_t mem[NE2000_MEM_SIZE];
 147 } NE2000State;
 148
 149 typedef struct PCINE2000State {
 150     PCIDevice dev;
 151     NE2000State ne2000;
 152 } PCINE2000State;
 153
 154 static void ne2000_reset(NE2000State *s)
 155 {
 156     int i;
 157
 158     s->isr = ENISR_RESET;
 159     memcpy(s->mem, s->macaddr, 6);
 160     s->mem[14] = 0x57;
 161     s->mem[15] = 0x57;
 162
 163     /* duplicate prom data */
 164     for(i = 15;i >= 0; i--) {
 165         s->mem[2 * i] = s->mem[i];
 166         s->mem[2 * i + 1] = s->mem[i];
 167     }
 168 }
 169
 170 static void ne2000_update_irq(NE2000State *s)
 171 {
 172     int isr;
 173     isr = (s->isr & s->imr) & 0x7f;
 174 #if defined(DEBUG_NE2000)
 175     printf("NE2000: Set IRQ to %d (%02x %02x)\n",
 176            isr ? 1 : 0, s->isr, s->imr);
 177 #endif
 178     qemu_set_irq(s->irq, (isr != 0));
 179 }
 180
 181 #define POLYNOMIAL 0x04c11db6
 182
 183 /* From FreeBSD */
 184 /* XXX: optimize */
 185 static int compute_mcast_idx(const uint8_t *ep)
 186 {
 187     uint32_t crc;
 188     int carry, i, j;
 189     uint8_t b;
 190
 191     crc = 0xffffffff;
 192     for (i = 0; i < 6; i++) {
 193         b = *ep++;
 194         for (j = 0; j < 8; j++) {
 195             carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
 196             crc <<= 1;
 197             b >>= 1;
 198             if (carry)
 199                 crc = ((crc ^ POLYNOMIAL) | carry);
 200         }
 201     }
 202     return (crc >> 26);
 203 }
 204
 205 static int ne2000_buffer_full(NE2000State *s)
 206 {
 207     int avail, index, boundary;
 208
 209     index = s->curpag << 8;
 210     boundary = s->boundary << 8;
 211     if (index < boundary)
 212         avail = boundary - index;
 213     else
 214         avail = (s->stop - s->start) - (index - boundary);
 215     if (avail < (MAX_ETH_FRAME_SIZE + 4))
 216         return 1;
 217     return 0;
 218 }
 219
 220 static int ne2000_can_receive(VLANClientState *vc)
 221 {
 222     NE2000State *s = vc->opaque;
 223
 224     if (s->cmd & E8390_STOP)
 225         return 1;
 226     return !ne2000_buffer_full(s);
 227 }
 228
 229 #define MIN_BUF_SIZE 60
 230
 231 static ssize_t ne2000_receive(VLANClientState *vc, const uint8_t *buf, size_t size_)
 232 {
 233     NE2000State *s = vc->opaque;
 234     int size = size_;
 235     uint8_t *p;
 236     unsigned int total_len, next, avail, len, index, mcast_idx;
 237     uint8_t buf1[60];
 238     static const uint8_t broadcast_macaddr[6] =
 239         { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 240
 241 #if defined(DEBUG_NE2000)
 242     printf("NE2000: received len=%d\n", size);
 243 #endif
 244
 245     if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
 246         return -1;
 247
 248     /* XXX: check this */
 249     if (s->rxcr & 0x10) {
 250         /* promiscuous: receive all */
 251     } else {
 252         if (!memcmp(buf,  broadcast_macaddr, 6)) {
 253             /* broadcast address */
 254             if (!(s->rxcr & 0x04))
 255                 return size;
 256         } else if (buf[0] & 0x01) {
 257             /* multicast */
 258             if (!(s->rxcr & 0x08))
 259                 return size;
 260             mcast_idx = compute_mcast_idx(buf);
 261             if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
 262                 return size;
 263         } else if (s->mem[0] == buf[0] &&
 264                    s->mem[2] == buf[1] &&
 265                    s->mem[4] == buf[2] &&
 266                    s->mem[6] == buf[3] &&
 267                    s->mem[8] == buf[4] &&
 268                    s->mem[10] == buf[5]) {
 269             /* match */
 270         } else {
 271             return size;
 272         }
 273     }
 274
 275
 276     /* if too small buffer, then expand it */
 277     if (size < MIN_BUF_SIZE) {
 278         memcpy(buf1, buf, size);
 279         memset(buf1 + size, 0, MIN_BUF_SIZE - size);
 280         buf = buf1;
 281         size = MIN_BUF_SIZE;
 282     }
 283
 284     index = s->curpag << 8;
 285     /* 4 bytes for header */
 286     total_len = size + 4;
 287     /* address for next packet (4 bytes for CRC) */
 288     next = index + ((total_len + 4 + 255) & ~0xff);
 289     if (next >= s->stop)
 290         next -= (s->stop - s->start);
 291     /* prepare packet header */
 292     p = s->mem + index;
 293     s->rsr = ENRSR_RXOK; /* receive status */
 294     /* XXX: check this */
 295     if (buf[0] & 0x01)
 296         s->rsr |= ENRSR_PHY;
 297     p[0] = s->rsr;
 298     p[1] = next >> 8;
 299     p[2] = total_len;
 300     p[3] = total_len >> 8;
 301     index += 4;
 302
 303     /* write packet data */
 304     while (size > 0) {
 305         if (index <= s->stop)
 306             avail = s->stop - index;
 307         else
 308             avail = 0;
 309         len = size;
 310         if (len > avail)
 311             len = avail;
 312         memcpy(s->mem + index, buf, len);
 313         buf += len;
 314         index += len;
 315         if (index == s->stop)
 316             index = s->start;
 317         size -= len;
 318     }
 319     s->curpag = next >> 8;
 320
 321     /* now we can signal we have received something */
 322     s->isr |= ENISR_RX;
 323     ne2000_update_irq(s);
 324
 325     return size_;
 326 }
 327
 328 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 329 {
 330     NE2000State *s = opaque;
 331     int offset, page, index;
 332
 333     addr &= 0xf;
 334 #ifdef DEBUG_NE2000
 335     printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
 336 #endif
 337     if (addr == E8390_CMD) {
 338         /* control register */
 339         s->cmd = val;
 340         if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
 341             s->isr &= ~ENISR_RESET;
 342             /* test specific case: zero length transfer */
 343             if ((val & (E8390_RREAD | E8390_RWRITE)) &&
 344                 s->rcnt == 0) {
 345                 s->isr |= ENISR_RDC;
 346                 ne2000_update_irq(s);
 347             }
 348             if (val & E8390_TRANS) {
 349                 index = (s->tpsr << 8);
 350                 /* XXX: next 2 lines are a hack to make netware 3.11 work */
 351                 if (index >= NE2000_PMEM_END)
 352                     index -= NE2000_PMEM_SIZE;
 353                 /* fail safe: check range on the transmitted length  */
 354                 if (index + s->tcnt <= NE2000_PMEM_END) {
 355                     qemu_send_packet(s->vc, s->mem + index, s->tcnt);
 356                 }
 357                 /* signal end of transfer */
 358                 s->tsr = ENTSR_PTX;
 359                 s->isr |= ENISR_TX;
 360                 s->cmd &= ~E8390_TRANS;
 361                 ne2000_update_irq(s);
 362             }
 363         }
 364     } else {
 365         page = s->cmd >> 6;
 366         offset = addr | (page << 4);
 367         switch(offset) {
 368         case EN0_STARTPG:
 369             s->start = val << 8;
 370             break;
 371         case EN0_STOPPG:
 372             s->stop = val << 8;
 373             break;
 374         case EN0_BOUNDARY:
 375             s->boundary = val;
 376             break;
 377         case EN0_IMR:
 378             s->imr = val;
 379             ne2000_update_irq(s);
 380             break;
 381         case EN0_TPSR:
 382             s->tpsr = val;
 383             break;
 384         case EN0_TCNTLO:
 385             s->tcnt = (s->tcnt & 0xff00) | val;
 386             break;
 387         case EN0_TCNTHI:
 388             s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
 389             break;
 390         case EN0_RSARLO:
 391             s->rsar = (s->rsar & 0xff00) | val;
 392             break;
 393         case EN0_RSARHI:
 394             s->rsar = (s->rsar & 0x00ff) | (val << 8);
 395             break;
 396         case EN0_RCNTLO:
 397             s->rcnt = (s->rcnt & 0xff00) | val;
 398             break;
 399         case EN0_RCNTHI:
 400             s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
 401             break;
 402         case EN0_RXCR:
 403             s->rxcr = val;
 404             break;
 405         case EN0_DCFG:
 406             s->dcfg = val;
 407             break;
 408         case EN0_ISR:
 409             s->isr &= ~(val & 0x7f);
 410             ne2000_update_irq(s);
 411             break;
 412         case EN1_PHYS ... EN1_PHYS + 5:
 413             s->phys[offset - EN1_PHYS] = val;
 414             break;
 415         case EN1_CURPAG:
 416             s->curpag = val;
 417             break;
 418         case EN1_MULT ... EN1_MULT + 7:
 419             s->mult[offset - EN1_MULT] = val;
 420             break;
 421         }
 422     }
 423 }
 424
 425 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
 426 {
 427     NE2000State *s = opaque;
 428     int offset, page, ret;
 429
 430     addr &= 0xf;
 431     if (addr == E8390_CMD) {
 432         ret = s->cmd;
 433     } else {
 434         page = s->cmd >> 6;
 435         offset = addr | (page << 4);
 436         switch(offset) {
 437         case EN0_TSR:
 438             ret = s->tsr;
 439             break;
 440         case EN0_BOUNDARY:
 441             ret = s->boundary;
 442             break;
 443         case EN0_ISR:
 444             ret = s->isr;
 445             break;
 446         case EN0_RSARLO:
 447             ret = s->rsar & 0x00ff;
 448             break;
 449         case EN0_RSARHI:
 450             ret = s->rsar >> 8;
 451             break;
 452         case EN1_PHYS ... EN1_PHYS + 5:
 453             ret = s->phys[offset - EN1_PHYS];
 454             break;
 455         case EN1_CURPAG:
 456             ret = s->curpag;
 457             break;
 458         case EN1_MULT ... EN1_MULT + 7:
 459             ret = s->mult[offset - EN1_MULT];
 460             break;
 461         case EN0_RSR:
 462             ret = s->rsr;
 463             break;
 464         case EN2_STARTPG:
 465             ret = s->start >> 8;
 466             break;
 467         case EN2_STOPPG:
 468             ret = s->stop >> 8;
 469             break;
 470         case EN0_RTL8029ID0:
 471             ret = 0x50;
 472             break;
 473         case EN0_RTL8029ID1:
 474             ret = 0x43;
 475             break;
 476         case EN3_CONFIG0:
 477             ret = 0;            /* 10baseT media */
 478             break;
 479         case EN3_CONFIG2:
 480             ret = 0x40;         /* 10baseT active */
 481             break;
 482         case EN3_CONFIG3:
 483             ret = 0x40;         /* Full duplex */
 484             break;
 485         default:
 486             ret = 0x00;
 487             break;
 488         }
 489     }
 490 #ifdef DEBUG_NE2000
 491     printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
 492 #endif
 493     return ret;
 494 }
 495
 496 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
 497                                      uint32_t val)
 498 {
 499     if (addr < 32 ||
 500         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 501         s->mem[addr] = val;
 502     }
 503 }
 504
 505 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
 506                                      uint32_t val)
 507 {
 508     addr &= ~1; /* XXX: check exact behaviour if not even */
 509     if (addr < 32 ||
 510         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 511         *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
 512     }
 513 }
 514
 515 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
 516                                      uint32_t val)
 517 {
 518     addr &= ~1; /* XXX: check exact behaviour if not even */
 519     if (addr < 32 ||
 520         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 521         cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
 522     }
 523 }
 524
 525 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
 526 {
 527     if (addr < 32 ||
 528         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 529         return s->mem[addr];
 530     } else {
 531         return 0xff;
 532     }
 533 }
 534
 535 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
 536 {
 537     addr &= ~1; /* XXX: check exact behaviour if not even */
 538     if (addr < 32 ||
 539         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 540         return le16_to_cpu(*(uint16_t *)(s->mem + addr));
 541     } else {
 542         return 0xffff;
 543     }
 544 }
 545
 546 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
 547 {
 548     addr &= ~1; /* XXX: check exact behaviour if not even */
 549     if (addr < 32 ||
 550         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 551         return le32_to_cpupu((uint32_t *)(s->mem + addr));
 552     } else {
 553         return 0xffffffff;
 554     }
 555 }
 556
 557 static inline void ne2000_dma_update(NE2000State *s, int len)
 558 {
 559     s->rsar += len;
 560     /* wrap */
 561     /* XXX: check what to do if rsar > stop */
 562     if (s->rsar == s->stop)
 563         s->rsar = s->start;
 564
 565     if (s->rcnt <= len) {
 566         s->rcnt = 0;
 567         /* signal end of transfer */
 568         s->isr |= ENISR_RDC;
 569         ne2000_update_irq(s);
 570     } else {
 571         s->rcnt -= len;
 572     }
 573 }
 574
 575 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 576 {
 577     NE2000State *s = opaque;
 578
 579 #ifdef DEBUG_NE2000
 580     printf("NE2000: asic write val=0x%04x\n", val);
 581 #endif
 582     if (s->rcnt == 0)
 583         return;
 584     if (s->dcfg & 0x01) {
 585         /* 16 bit access */
 586         ne2000_mem_writew(s, s->rsar, val);
 587         ne2000_dma_update(s, 2);
 588     } else {
 589         /* 8 bit access */
 590         ne2000_mem_writeb(s, s->rsar, val);
 591         ne2000_dma_update(s, 1);
 592     }
 593 }
 594
 595 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
 596 {
 597     NE2000State *s = opaque;
 598     int ret;
 599
 600     if (s->dcfg & 0x01) {
 601         /* 16 bit access */
 602         ret = ne2000_mem_readw(s, s->rsar);
 603         ne2000_dma_update(s, 2);
 604     } else {
 605         /* 8 bit access */
 606         ret = ne2000_mem_readb(s, s->rsar);
 607         ne2000_dma_update(s, 1);
 608     }
 609 #ifdef DEBUG_NE2000
 610     printf("NE2000: asic read val=0x%04x\n", ret);
 611 #endif
 612     return ret;
 613 }
 614
 615 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 616 {
 617     NE2000State *s = opaque;
 618
 619 #ifdef DEBUG_NE2000
 620     printf("NE2000: asic writel val=0x%04x\n", val);
 621 #endif
 622     if (s->rcnt == 0)
 623         return;
 624     /* 32 bit access */
 625     ne2000_mem_writel(s, s->rsar, val);
 626     ne2000_dma_update(s, 4);
 627 }
 628
 629 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
 630 {
 631     NE2000State *s = opaque;
 632     int ret;
 633
 634     /* 32 bit access */
 635     ret = ne2000_mem_readl(s, s->rsar);
 636     ne2000_dma_update(s, 4);
 637 #ifdef DEBUG_NE2000
 638     printf("NE2000: asic readl val=0x%04x\n", ret);
 639 #endif
 640     return ret;
 641 }
 642
 643 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 644 {
 645     /* nothing to do (end of reset pulse) */
 646 }
 647
 648 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
 649 {
 650     NE2000State *s = opaque;
 651     ne2000_reset(s);
 652     return 0;
 653 }
 654
 655 static void ne2000_save(QEMUFile* f, void* opaque)
 656 {
 657         NE2000State* s = opaque;
 658         uint32_t tmp;
 659
 660         qemu_put_8s(f, &s->rxcr);
 661
 662         qemu_put_8s(f, &s->cmd);
 663         qemu_put_be32s(f, &s->start);
 664         qemu_put_be32s(f, &s->stop);
 665         qemu_put_8s(f, &s->boundary);
 666         qemu_put_8s(f, &s->tsr);
 667         qemu_put_8s(f, &s->tpsr);
 668         qemu_put_be16s(f, &s->tcnt);
 669         qemu_put_be16s(f, &s->rcnt);
 670         qemu_put_be32s(f, &s->rsar);
 671         qemu_put_8s(f, &s->rsr);
 672         qemu_put_8s(f, &s->isr);
 673         qemu_put_8s(f, &s->dcfg);
 674         qemu_put_8s(f, &s->imr);
 675         qemu_put_buffer(f, s->phys, 6);
 676         qemu_put_8s(f, &s->curpag);
 677         qemu_put_buffer(f, s->mult, 8);
 678         tmp = 0;
 679         qemu_put_be32s(f, &tmp); /* ignored, was irq */
 680         qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
 681 }
 682
 683 static int ne2000_load(QEMUFile* f, void* opaque, int version_id)
 684 {
 685         NE2000State* s = opaque;
 686         uint32_t tmp;
 687
 688         if (version_id > 3)
 689             return -EINVAL;
 690
 691         if (version_id >= 2) {
 692             qemu_get_8s(f, &s->rxcr);
 693         } else {
 694             s->rxcr = 0x0c;
 695         }
 696
 697         qemu_get_8s(f, &s->cmd);
 698         qemu_get_be32s(f, &s->start);
 699         qemu_get_be32s(f, &s->stop);
 700         qemu_get_8s(f, &s->boundary);
 701         qemu_get_8s(f, &s->tsr);
 702         qemu_get_8s(f, &s->tpsr);
 703         qemu_get_be16s(f, &s->tcnt);
 704         qemu_get_be16s(f, &s->rcnt);
 705         qemu_get_be32s(f, &s->rsar);
 706         qemu_get_8s(f, &s->rsr);
 707         qemu_get_8s(f, &s->isr);
 708         qemu_get_8s(f, &s->dcfg);
 709         qemu_get_8s(f, &s->imr);
 710         qemu_get_buffer(f, s->phys, 6);
 711         qemu_get_8s(f, &s->curpag);
 712         qemu_get_buffer(f, s->mult, 8);
 713         qemu_get_be32s(f, &tmp); /* ignored */
 714         qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
 715
 716         return 0;
 717 }
 718
 719 static void pci_ne2000_save(QEMUFile* f, void* opaque)
 720 {
 721         PCINE2000State* s = opaque;
 722
 723         pci_device_save(&s->dev, f);
 724         ne2000_save(f, &s->ne2000);
 725 }
 726
 727 static int pci_ne2000_load(QEMUFile* f, void* opaque, int version_id)
 728 {
 729         PCINE2000State* s = opaque;
 730         int ret;
 731
 732         if (version_id > 3)
 733             return -EINVAL;
 734
 735         if (version_id >= 3) {
 736             ret = pci_device_load(&s->dev, f);
 737             if (ret < 0)
 738                 return ret;
 739         }
 740
 741         return ne2000_load(f, &s->ne2000, version_id);
 742 }
 743
 744 static void isa_ne2000_cleanup(VLANClientState *vc)
 745 {
 746     NE2000State *s = vc->opaque;
 747
 748     unregister_savevm("ne2000", s);
 749
 750     isa_unassign_ioport(s->isa_io_base, 16);
 751     isa_unassign_ioport(s->isa_io_base + 0x10, 2);
 752     isa_unassign_ioport(s->isa_io_base + 0x1f, 1);
 753
 754     qemu_free(s);
 755 }
 756
 757 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd)
 758 {
 759     NE2000State *s;
 760
 761     qemu_check_nic_model(nd, "ne2k_isa");
 762
 763     s = qemu_mallocz(sizeof(NE2000State));
 764
 765     register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
 766     register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
 767
 768     register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 769     register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 770     register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 771     register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 772
 773     register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 774     register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 775     s->isa_io_base = base;
 776     s->irq = irq;
 777     memcpy(s->macaddr, nd->macaddr, 6);
 778
 779     ne2000_reset(s);
 780
 781     s->vc = nd->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
 782                                           ne2000_can_receive, ne2000_receive,
 783                                           NULL, isa_ne2000_cleanup, s);
 784
 785     qemu_format_nic_info_str(s->vc, s->macaddr);
 786
 787     register_savevm("ne2000", -1, 2, ne2000_save, ne2000_load, s);
 788 }
 789
 790 /***********************************************************/
 791 /* PCI NE2000 definitions */
 792
 793 static void ne2000_map(PCIDevice *pci_dev, int region_num,
 794                        uint32_t addr, uint32_t size, int type)
 795 {
 796     PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
 797     NE2000State *s = &d->ne2000;
 798
 799     register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
 800     register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
 801
 802     register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 803     register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 804     register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 805     register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 806     register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
 807     register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
 808
 809     register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 810     register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 811 }
 812
 813 static void ne2000_cleanup(VLANClientState *vc)
 814 {
 815     NE2000State *s = vc->opaque;
 816
 817     unregister_savevm("ne2000", s);
 818 }
 819
 820 static int pci_ne2000_init(PCIDevice *pci_dev)
 821 {
 822     PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
 823     NE2000State *s;
 824     uint8_t *pci_conf;
 825
 826     pci_conf = d->dev.config;
 827     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
 828     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029);
 829     pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
 830     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 831     pci_conf[0x3d] = 1; // interrupt pin 0
 832
 833     pci_register_bar(&d->dev, 0, 0x100,
 834                            PCI_ADDRESS_SPACE_IO, ne2000_map);
 835     s = &d->ne2000;
 836     s->irq = d->dev.irq[0];
 837     qdev_get_macaddr(&d->dev.qdev, s->macaddr);
 838     ne2000_reset(s);
 839     s->vc = qdev_get_vlan_client(&d->dev.qdev,
 840                                  ne2000_can_receive, ne2000_receive, NULL,
 841                                  ne2000_cleanup, s);
 842
 843     qemu_format_nic_info_str(s->vc, s->macaddr);
 844
 845     register_savevm("ne2000", -1, 3, pci_ne2000_save, pci_ne2000_load, d);
 846     return 0;
 847 }
 848
 849 static PCIDeviceInfo ne2000_info = {
 850     .qdev.name = "ne2k_pci",
 851     .qdev.size = sizeof(PCINE2000State),
 852     .init      = pci_ne2000_init,
 853 };
 854
 855 static void ne2000_register_devices(void)
 856 {
 857     pci_qdev_register(&ne2000_info);
 858 }
 859
 860 device_init(ne2000_register_devices)