hw/iommu.h

   1 #ifndef QEMU_IOMMU_H
   2 #define QEMU_IOMMU_H
   3
   4 #include "pci.h"
   5 #include "targphys.h"
   6 #include "qdev.h"
   7
   8 /* Don't use directly. */
   9 struct iommu {
  10     void *opaque;
  11
  12     void (*register_device)(struct iommu *iommu,
  13                             DeviceState *dev);
  14     int (*translate)(struct iommu *iommu,
  15                      DeviceState *dev,
  16                      target_phys_addr_t addr,
  17                      target_phys_addr_t *paddr,
  18                      int *len,
  19                      unsigned perms);
  20     int (*start_transaction)(struct iommu *iommu,
  21                              DeviceState *dev);
  22     void (*end_transaction)(struct iommu *iommu,
  23                             DeviceState *dev);
  24 };
  25
  26 #define IOMMU_PERM_READ   (1 << 0)
  27 #define IOMMU_PERM_WRITE  (1 << 1)
  28
  29 #define IOMMU_PERM_RW     (IOMMU_PERM_READ | IOMMU_PERM_WRITE)
  30
  31 static inline int iommu_nop_translate(struct iommu *iommu,
  32                                       DeviceState *dev,
  33                                       target_phys_addr_t addr,
  34                                       target_phys_addr_t *paddr,
  35                                       int *len,
  36                                       unsigned perms)
  37 {
  38     *paddr = addr;
  39     *len = INT_MAX;
  40
  41     return 0;
  42 }
  43
  44 static inline int iommu_nop_rw(struct iommu *iommu,
  45                                DeviceState *dev,
  46                                target_phys_addr_t addr,
  47                                uint8_t *buf,
  48                                int len,
  49                                int is_write)
  50 {
  51     cpu_physical_memory_rw(addr, buf, len, is_write);
  52
  53     return 0;
  54 }
  55
  56 static inline int iommu_register_device(struct iommu *iommu,
  57                                         DeviceState *dev)
  58 {
  59     if (iommu && iommu->register_device)
  60         iommu->register_device(iommu, dev);
  61
  62     return 0;
  63 }
  64
  65 #ifdef CONFIG_IOMMU
  66
  67 extern struct iommu *iommu_get(DeviceState *dev, DeviceState **real_dev);
  68
  69 /**
  70  * Translates an address for the given device and performs access checking.
  71  *
  72  * Defined in implementation-specific IOMMU code.
  73  *
  74  * @iommu   IOMMU
  75  * @dev     qdev device
  76  * @addr    address to be translated
  77  * @paddr   translated address
  78  * @len     number of bytes for which the translation is valid
  79  * @rw      read or write?
  80  *
  81  * Returns 0 iff translation and access checking succeeded.
  82  */
  83 static inline int iommu_translate(struct iommu *iommu,
  84                                   DeviceState *dev,
  85                                   target_phys_addr_t addr,
  86                                   target_phys_addr_t *paddr,
  87                                   int *len,
  88                                   unsigned perms)
  89 {
  90     if (iommu && iommu->translate)
  91         return iommu->translate(iommu, dev, addr, paddr, len, perms);
  92
  93     return iommu_nop_translate(iommu, dev, addr, paddr, len, perms);
  94 }
  95
  96 extern int __iommu_rw(struct iommu *iommu,
  97                       DeviceState *dev,
  98                       target_phys_addr_t addr,
  99                       uint8_t *buf,
 100                       int len,
 101                       int is_write);
 102
 103 /**
 104  * Performs I/O with address translation and access checking.
 105  *
 106  * Defined in generic IOMMU code.
 107  *
 108  * @iommu   IOMMU
 109  * @dev     qdev device
 110  * @addr    address where to perform I/O
 111  * @buf     buffer to read from or write to
 112  * @len     length of the operation
 113  * @rw      read or write?
 114  *
 115  * Returns 0 iff the I/O operation succeeded.
 116  */
 117 static inline int iommu_rw(struct iommu *iommu,
 118                            DeviceState *dev,
 119                            target_phys_addr_t addr,
 120                            uint8_t *buf,
 121                            int len,
 122                            int is_write)
 123 {
 124     if (iommu && iommu->translate)
 125         return __iommu_rw(iommu, dev, addr, buf, len, is_write);
 126
 127     return iommu_nop_rw(iommu, dev, addr, buf, len, is_write);
 128 }
 129
 130 static inline int iommu_start_transaction(struct iommu *iommu,
 131                                           DeviceState *dev)
 132 {
 133     if (iommu && iommu->start_transaction)
 134         return iommu->start_transaction(iommu, dev);
 135
 136     return 0;
 137 }
 138
 139 static inline void iommu_end_transaction(struct iommu *iommu,
 140                                          DeviceState *dev)
 141 {
 142     if (iommu && iommu->end_transaction)
 143         iommu->end_transaction(iommu, dev);
 144 }
 145
 146 #define DEFINE_LD_PHYS(suffix, size)                                        \
 147 static inline uint##size##_t iommu_ld##suffix(struct iommu *iommu,          \
 148                                              DeviceState *dev,              \
 149                                              target_phys_addr_t addr)       \
 150 {                                                                           \
 151     int len, err;                                                           \
 152     target_phys_addr_t paddr;                                               \
 153                                                                             \
 154     err = iommu_translate(iommu, dev, addr, &paddr, &len, IOMMU_PERM_READ); \
 155     if (err || (len < size / 8))                                            \
 156         return err;                                                         \
 157     return ld##suffix##_phys(paddr);                                        \
 158 }
 159
 160 #define DEFINE_ST_PHYS(suffix, size)                                        \
 161 static inline void iommu_st##suffix(struct iommu *iommu,                    \
 162                                     DeviceState *dev,                       \
 163                                     target_phys_addr_t addr,                \
 164                                     uint##size##_t val)                     \
 165 {                                                                           \
 166     int len, err;                                                           \
 167     target_phys_addr_t paddr;                                               \
 168                                                                             \
 169     err = iommu_translate(iommu, dev, addr, &paddr, &len, IOMMU_PERM_WRITE);\
 170     if (err || (len < size / 8))                                            \
 171         return;                                                             \
 172     st##suffix##_phys(paddr, val);                                          \
 173 }
 174
 175 #else /* CONFIG_IOMMU */
 176
 177 static inline struct iommu *iommu_get(DeviceState *dev, DeviceState **real_dev)
 178 {
 179     return NULL;
 180 }
 181
 182 static inline int iommu_translate(struct iommu *iommu,
 183                                   DeviceState *dev,
 184                                   target_phys_addr_t addr,
 185                                   target_phys_addr_t *paddr,
 186                                   int *len,
 187                                   unsigned perms)
 188 {
 189     return iommu_nop_translate(iommu, dev, addr, paddr, len, perms);
 190 }
 191
 192 static inline int iommu_rw(struct iommu *iommu,
 193                            DeviceState *dev,
 194                            target_phys_addr_t addr,
 195                            uint8_t *buf,
 196                            int len,
 197                            int is_write)
 198 {
 199     return iommu_nop_rw(iommu, dev, addr, buf, len, is_write);
 200 }
 201
 202 static inline int iommu_start_transaction(struct iommu *iommu,
 203                                           DeviceState *dev)
 204 {
 205     return 0;
 206 }
 207
 208 static inline void iommu_end_transaction(struct iommu *iommu,
 209                                          DeviceState *dev)
 210 {
 211 }
 212
 213 #define DEFINE_LD_PHYS(suffix, size)                                        \
 214 static inline uint##size##_t iommu_ld##suffix(struct iommu *iommu,          \
 215                                              DeviceState *dev,              \
 216                                              target_phys_addr_t addr)       \
 217 {                                                                           \
 218     return ld##suffix##_phys(addr);                                         \
 219 }
 220
 221 #define DEFINE_ST_PHYS(suffix, size)                                        \
 222 static inline void iommu_st##suffix(struct iommu *iommu,                    \
 223                                     DeviceState *dev,                       \
 224                                     target_phys_addr_t addr,                \
 225                                     uint##size##_t val)                     \
 226 {                                                                           \
 227     st##suffix##_phys(addr, val);                                           \
 228 }
 229
 230 #endif /* CONFIG_IOMMU */
 231
 232 static inline int iommu_read(struct iommu *iommu,
 233                              DeviceState *dev,
 234                              target_phys_addr_t addr,
 235                              uint8_t *buf,
 236                              int len)
 237 {
 238     return iommu_rw(iommu, dev, addr, buf, len, 0);
 239 }
 240
 241 static inline int iommu_write(struct iommu *iommu,
 242                               DeviceState *dev,
 243                               target_phys_addr_t addr,
 244                               const uint8_t *buf,
 245                               int len)
 246 {
 247     return iommu_rw(iommu, dev, addr, (uint8_t *) buf, len, 1);
 248 }
 249
 250 DEFINE_LD_PHYS(ub, 8)
 251 DEFINE_LD_PHYS(uw, 16)
 252 DEFINE_LD_PHYS(l, 32)
 253 DEFINE_LD_PHYS(q, 64)
 254
 255 DEFINE_ST_PHYS(b, 8)
 256 DEFINE_ST_PHYS(w, 16)
 257 DEFINE_ST_PHYS(l, 32)
 258 DEFINE_ST_PHYS(q, 64)
 259
 260 #endif