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ac97: IOMMU support
[qemu-kvm/amd-iommu.git] / hw / ac97.c
blob0e30d805084ba1f24bc25004a25298b4dd2e1d06
1 /*
2 * Copyright (C) 2006 InnoTek Systemberatung GmbH
3 *
4 * This file is part of VirtualBox Open Source Edition (OSE), as
5 * available from http://www.virtualbox.org. This file is free software;
6 * you can redistribute it and/or modify it under the terms of the GNU
7 * General Public License as published by the Free Software Foundation,
8 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
9 * distribution. VirtualBox OSE is distributed in the hope that it will
10 * be useful, but WITHOUT ANY WARRANTY of any kind.
11 *
12 * If you received this file as part of a commercial VirtualBox
13 * distribution, then only the terms of your commercial VirtualBox
14 * license agreement apply instead of the previous paragraph.
15 */
16
17 #include "hw.h"
18 #include "iommu.h"
19 #include "audiodev.h"
20 #include "audio/audio.h"
21 #include "pci.h"
22
23 enum {
24 AC97_Reset = 0x00,
25 AC97_Master_Volume_Mute = 0x02,
26 AC97_Headphone_Volume_Mute = 0x04,
27 AC97_Master_Volume_Mono_Mute = 0x06,
28 AC97_Master_Tone_RL = 0x08,
29 AC97_PC_BEEP_Volume_Mute = 0x0A,
30 AC97_Phone_Volume_Mute = 0x0C,
31 AC97_Mic_Volume_Mute = 0x0E,
32 AC97_Line_In_Volume_Mute = 0x10,
33 AC97_CD_Volume_Mute = 0x12,
34 AC97_Video_Volume_Mute = 0x14,
35 AC97_Aux_Volume_Mute = 0x16,
36 AC97_PCM_Out_Volume_Mute = 0x18,
37 AC97_Record_Select = 0x1A,
38 AC97_Record_Gain_Mute = 0x1C,
39 AC97_Record_Gain_Mic_Mute = 0x1E,
40 AC97_General_Purpose = 0x20,
41 AC97_3D_Control = 0x22,
42 AC97_AC_97_RESERVED = 0x24,
43 AC97_Powerdown_Ctrl_Stat = 0x26,
44 AC97_Extended_Audio_ID = 0x28,
45 AC97_Extended_Audio_Ctrl_Stat = 0x2A,
46 AC97_PCM_Front_DAC_Rate = 0x2C,
47 AC97_PCM_Surround_DAC_Rate = 0x2E,
48 AC97_PCM_LFE_DAC_Rate = 0x30,
49 AC97_PCM_LR_ADC_Rate = 0x32,
50 AC97_MIC_ADC_Rate = 0x34,
51 AC97_6Ch_Vol_C_LFE_Mute = 0x36,
52 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
53 AC97_Vendor_Reserved = 0x58,
54 AC97_Vendor_ID1 = 0x7c,
55 AC97_Vendor_ID2 = 0x7e
56 };
57
58 #define SOFT_VOLUME
59 #define SR_FIFOE 16 /* rwc */
60 #define SR_BCIS 8 /* rwc */
61 #define SR_LVBCI 4 /* rwc */
62 #define SR_CELV 2 /* ro */
63 #define SR_DCH 1 /* ro */
64 #define SR_VALID_MASK ((1 << 5) - 1)
65 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
66 #define SR_RO_MASK (SR_DCH | SR_CELV)
67 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
68
69 #define CR_IOCE 16 /* rw */
70 #define CR_FEIE 8 /* rw */
71 #define CR_LVBIE 4 /* rw */
72 #define CR_RR 2 /* rw */
73 #define CR_RPBM 1 /* rw */
74 #define CR_VALID_MASK ((1 << 5) - 1)
75 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
76
77 #define GC_WR 4 /* rw */
78 #define GC_CR 2 /* rw */
79 #define GC_VALID_MASK ((1 << 6) - 1)
80
81 #define GS_MD3 (1<<17) /* rw */
82 #define GS_AD3 (1<<16) /* rw */
83 #define GS_RCS (1<<15) /* rwc */
84 #define GS_B3S12 (1<<14) /* ro */
85 #define GS_B2S12 (1<<13) /* ro */
86 #define GS_B1S12 (1<<12) /* ro */
87 #define GS_S1R1 (1<<11) /* rwc */
88 #define GS_S0R1 (1<<10) /* rwc */
89 #define GS_S1CR (1<<9) /* ro */
90 #define GS_S0CR (1<<8) /* ro */
91 #define GS_MINT (1<<7) /* ro */
92 #define GS_POINT (1<<6) /* ro */
93 #define GS_PIINT (1<<5) /* ro */
94 #define GS_RSRVD ((1<<4)|(1<<3))
95 #define GS_MOINT (1<<2) /* ro */
96 #define GS_MIINT (1<<1) /* ro */
97 #define GS_GSCI 1 /* rwc */
98 #define GS_RO_MASK (GS_B3S12| \
99 GS_B2S12| \
100 GS_B1S12| \
101 GS_S1CR| \
102 GS_S0CR| \
103 GS_MINT| \
104 GS_POINT| \
105 GS_PIINT| \
106 GS_RSRVD| \
107 GS_MOINT| \
108 GS_MIINT)
109 #define GS_VALID_MASK ((1 << 18) - 1)
110 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
111
112 #define BD_IOC (1<<31)
113 #define BD_BUP (1<<30)
114
115 #define EACS_VRA 1
116 #define EACS_VRM 8
117
118 #define VOL_MASK 0x1f
119 #define MUTE_SHIFT 15
120
121 #define REC_MASK 7
122 enum {
123 REC_MIC = 0,
124 REC_CD,
125 REC_VIDEO,
126 REC_AUX,
127 REC_LINE_IN,
128 REC_STEREO_MIX,
129 REC_MONO_MIX,
130 REC_PHONE
131 };
132
133 typedef struct BD {
134 uint32_t addr;
135 uint32_t ctl_len;
136 } BD;
137
138 typedef struct AC97BusMasterRegs {
139 uint32_t bdbar; /* rw 0 */
140 uint8_t civ; /* ro 0 */
141 uint8_t lvi; /* rw 0 */
142 uint16_t sr; /* rw 1 */
143 uint16_t picb; /* ro 0 */
144 uint8_t piv; /* ro 0 */
145 uint8_t cr; /* rw 0 */
146 unsigned int bd_valid;
147 BD bd;
148 } AC97BusMasterRegs;
149
150 typedef struct AC97LinkState {
151 PCIDevice dev;
152 QEMUSoundCard card;
153 uint32_t glob_cnt;
154 uint32_t glob_sta;
155 uint32_t cas;
156 uint32_t last_samp;
157 AC97BusMasterRegs bm_regs[3];
158 uint8_t mixer_data[256];
159 SWVoiceIn *voice_pi;
160 SWVoiceOut *voice_po;
161 SWVoiceIn *voice_mc;
162 int invalid_freq[3];
163 uint8_t silence[128];
164 uint32_t base[2];
165 int bup_flag;
166 } AC97LinkState;
167
168 enum {
169 BUP_SET = 1,
170 BUP_LAST = 2
171 };
172
173 #ifdef DEBUG_AC97
174 #define dolog(...) AUD_log ("ac97", __VA_ARGS__)
175 #else
176 #define dolog(...)
177 #endif
178
179 #define MKREGS(prefix, start) \
180 enum { \
181 prefix ## _BDBAR = start, \
182 prefix ## _CIV = start + 4, \
183 prefix ## _LVI = start + 5, \
184 prefix ## _SR = start + 6, \
185 prefix ## _PICB = start + 8, \
186 prefix ## _PIV = start + 10, \
187 prefix ## _CR = start + 11 \
188 }
189
190 enum {
191 PI_INDEX = 0,
192 PO_INDEX,
193 MC_INDEX,
194 LAST_INDEX
195 };
196
197 MKREGS (PI, PI_INDEX * 16);
198 MKREGS (PO, PO_INDEX * 16);
199 MKREGS (MC, MC_INDEX * 16);
200
201 enum {
202 GLOB_CNT = 0x2c,
203 GLOB_STA = 0x30,
204 CAS = 0x34
205 };
206
207 #define GET_BM(index) (((index) >> 4) & 3)
208
209 static void po_callback (void *opaque, int free);
210 static void pi_callback (void *opaque, int avail);
211 static void mc_callback (void *opaque, int avail);
212
213 static void warm_reset (AC97LinkState *s)
214 {
215 (void) s;
216 }
217
218 static void cold_reset (AC97LinkState * s)
219 {
220 (void) s;
221 }
222
223 static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r)
224 {
225 struct iommu *iommu;
226 DeviceState *dev;
227 uint8_t b[8];
228
229 iommu = iommu_get(&s->dev.qdev, &dev);
230
231 iommu_read (iommu, dev, r->bdbar + r->civ * 8, b, 8);
232 r->bd_valid = 1;
233 r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3;
234 r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]);
235 r->picb = r->bd.ctl_len & 0xffff;
236 dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
237 r->civ, r->bd.addr, r->bd.ctl_len >> 16,
238 r->bd.ctl_len & 0xffff,
239 (r->bd.ctl_len & 0xffff) << 1);
240 }
241
242 static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
243 {
244 int event = 0;
245 int level = 0;
246 uint32_t new_mask = new_sr & SR_INT_MASK;
247 uint32_t old_mask = r->sr & SR_INT_MASK;
248 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};
249
250 if (new_mask ^ old_mask) {
251 /** @todo is IRQ deasserted when only one of status bits is cleared? */
252 if (!new_mask) {
253 event = 1;
254 level = 0;
255 }
256 else {
257 if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) {
258 event = 1;
259 level = 1;
260 }
261 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) {
262 event = 1;
263 level = 1;
264 }
265 }
266 }
267
268 r->sr = new_sr;
269
270 dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n",
271 r->sr & SR_BCIS, r->sr & SR_LVBCI,
272 r->sr,
273 event, level);
274
275 if (!event)
276 return;
277
278 if (level) {
279 s->glob_sta |= masks[r - s->bm_regs];
280 dolog ("set irq level=1\n");
281 qemu_set_irq (s->dev.irq[0], 1);
282 }
283 else {
284 s->glob_sta &= ~masks[r - s->bm_regs];
285 dolog ("set irq level=0\n");
286 qemu_set_irq (s->dev.irq[0], 0);
287 }
288 }
289
290 static void voice_set_active (AC97LinkState *s, int bm_index, int on)
291 {
292 switch (bm_index) {
293 case PI_INDEX:
294 AUD_set_active_in (s->voice_pi, on);
295 break;
296
297 case PO_INDEX:
298 AUD_set_active_out (s->voice_po, on);
299 break;
300
301 case MC_INDEX:
302 AUD_set_active_in (s->voice_mc, on);
303 break;
304
305 default:
306 AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index);
307 break;
308 }
309 }
310
311 static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r)
312 {
313 dolog ("reset_bm_regs\n");
314 r->bdbar = 0;
315 r->civ = 0;
316 r->lvi = 0;
317 /** todo do we need to do that? */
318 update_sr (s, r, SR_DCH);
319 r->picb = 0;
320 r->piv = 0;
321 r->cr = r->cr & CR_DONT_CLEAR_MASK;
322 r->bd_valid = 0;
323
324 voice_set_active (s, r - s->bm_regs, 0);
325 memset (s->silence, 0, sizeof (s->silence));
326 }
327
328 static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v)
329 {
330 if (i + 2 > sizeof (s->mixer_data)) {
331 dolog ("mixer_store: index %d out of bounds %zd\n",
332 i, sizeof (s->mixer_data));
333 return;
334 }
335
336 s->mixer_data[i + 0] = v & 0xff;
337 s->mixer_data[i + 1] = v >> 8;
338 }
339
340 static uint16_t mixer_load (AC97LinkState *s, uint32_t i)
341 {
342 uint16_t val = 0xffff;
343
344 if (i + 2 > sizeof (s->mixer_data)) {
345 dolog ("mixer_store: index %d out of bounds %zd\n",
346 i, sizeof (s->mixer_data));
347 }
348 else {
349 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8);
350 }
351
352 return val;
353 }
354
355 static void open_voice (AC97LinkState *s, int index, int freq)
356 {
357 struct audsettings as;
358
359 as.freq = freq;
360 as.nchannels = 2;
361 as.fmt = AUD_FMT_S16;
362 as.endianness = 0;
363
364 if (freq > 0) {
365 s->invalid_freq[index] = 0;
366 switch (index) {
367 case PI_INDEX:
368 s->voice_pi = AUD_open_in (
369 &s->card,
370 s->voice_pi,
371 "ac97.pi",
372 s,
373 pi_callback,
374 &as
375 );
376 break;
377
378 case PO_INDEX:
379 s->voice_po = AUD_open_out (
380 &s->card,
381 s->voice_po,
382 "ac97.po",
383 s,
384 po_callback,
385 &as
386 );
387 break;
388
389 case MC_INDEX:
390 s->voice_mc = AUD_open_in (
391 &s->card,
392 s->voice_mc,
393 "ac97.mc",
394 s,
395 mc_callback,
396 &as
397 );
398 break;
399 }
400 }
401 else {
402 s->invalid_freq[index] = freq;
403 switch (index) {
404 case PI_INDEX:
405 AUD_close_in (&s->card, s->voice_pi);
406 s->voice_pi = NULL;
407 break;
408
409 case PO_INDEX:
410 AUD_close_out (&s->card, s->voice_po);
411 s->voice_po = NULL;
412 break;
413
414 case MC_INDEX:
415 AUD_close_in (&s->card, s->voice_mc);
416 s->voice_mc = NULL;
417 break;
418 }
419 }
420 }
421
422 static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX])
423 {
424 uint16_t freq;
425
426 freq = mixer_load (s, AC97_PCM_LR_ADC_Rate);
427 open_voice (s, PI_INDEX, freq);
428 AUD_set_active_in (s->voice_pi, active[PI_INDEX]);
429
430 freq = mixer_load (s, AC97_PCM_Front_DAC_Rate);
431 open_voice (s, PO_INDEX, freq);
432 AUD_set_active_out (s->voice_po, active[PO_INDEX]);
433
434 freq = mixer_load (s, AC97_MIC_ADC_Rate);
435 open_voice (s, MC_INDEX, freq);
436 AUD_set_active_in (s->voice_mc, active[MC_INDEX]);
437 }
438
439 #ifdef USE_MIXER
440 static void set_volume (AC97LinkState *s, int index,
441 audmixerctl_t mt, uint32_t val)
442 {
443 int mute = (val >> MUTE_SHIFT) & 1;
444 uint8_t rvol = VOL_MASK - (val & VOL_MASK);
445 uint8_t lvol = VOL_MASK - ((val >> 8) & VOL_MASK);
446 rvol = 255 * rvol / VOL_MASK;
447 lvol = 255 * lvol / VOL_MASK;
448
449 #ifdef SOFT_VOLUME
450 if (index == AC97_Master_Volume_Mute) {
451 AUD_set_volume_out (s->voice_po, mute, lvol, rvol);
452 }
453 else {
454 AUD_set_volume (mt, &mute, &lvol, &rvol);
455 }
456 #else
457 AUD_set_volume (mt, &mute, &lvol, &rvol);
458 #endif
459
460 rvol = VOL_MASK - ((VOL_MASK * rvol) / 255);
461 lvol = VOL_MASK - ((VOL_MASK * lvol) / 255);
462 mixer_store (s, index, val);
463 }
464
465 static audrecsource_t ac97_to_aud_record_source (uint8_t i)
466 {
467 switch (i) {
468 case REC_MIC:
469 return AUD_REC_MIC;
470
471 case REC_CD:
472 return AUD_REC_CD;
473
474 case REC_VIDEO:
475 return AUD_REC_VIDEO;
476
477 case REC_AUX:
478 return AUD_REC_AUX;
479
480 case REC_LINE_IN:
481 return AUD_REC_LINE_IN;
482
483 case REC_PHONE:
484 return AUD_REC_PHONE;
485
486 default:
487 dolog ("Unknown record source %d, using MIC\n", i);
488 return AUD_REC_MIC;
489 }
490 }
491
492 static uint8_t aud_to_ac97_record_source (audrecsource_t rs)
493 {
494 switch (rs) {
495 case AUD_REC_MIC:
496 return REC_MIC;
497
498 case AUD_REC_CD:
499 return REC_CD;
500
501 case AUD_REC_VIDEO:
502 return REC_VIDEO;
503
504 case AUD_REC_AUX:
505 return REC_AUX;
506
507 case AUD_REC_LINE_IN:
508 return REC_LINE_IN;
509
510 case AUD_REC_PHONE:
511 return REC_PHONE;
512
513 default:
514 dolog ("Unknown audio recording source %d using MIC\n", rs);
515 return REC_MIC;
516 }
517 }
518
519 static void record_select (AC97LinkState *s, uint32_t val)
520 {
521 uint8_t rs = val & REC_MASK;
522 uint8_t ls = (val >> 8) & REC_MASK;
523 audrecsource_t ars = ac97_to_aud_record_source (rs);
524 audrecsource_t als = ac97_to_aud_record_source (ls);
525 AUD_set_record_source (&als, &ars);
526 rs = aud_to_ac97_record_source (ars);
527 ls = aud_to_ac97_record_source (als);
528 mixer_store (s, AC97_Record_Select, rs | (ls << 8));
529 }
530 #endif
531
532 static void mixer_reset (AC97LinkState *s)
533 {
534 uint8_t active[LAST_INDEX];
535
536 dolog ("mixer_reset\n");
537 memset (s->mixer_data, 0, sizeof (s->mixer_data));
538 memset (active, 0, sizeof (active));
539 mixer_store (s, AC97_Reset , 0x0000); /* 6940 */
540 mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x8000);
541 mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000);
542
543 mixer_store (s, AC97_Phone_Volume_Mute , 0x8008);
544 mixer_store (s, AC97_Mic_Volume_Mute , 0x8008);
545 mixer_store (s, AC97_CD_Volume_Mute , 0x8808);
546 mixer_store (s, AC97_Aux_Volume_Mute , 0x8808);
547 mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x8000);
548 mixer_store (s, AC97_General_Purpose , 0x0000);
549 mixer_store (s, AC97_3D_Control , 0x0000);
550 mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f);
551
552 /*
553 * Sigmatel 9700 (STAC9700)
554 */
555 mixer_store (s, AC97_Vendor_ID1 , 0x8384);
556 mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */
557
558 mixer_store (s, AC97_Extended_Audio_ID , 0x0809);
559 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
560 mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80);
561 mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80);
562 mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80);
563 mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80);
564 mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80);
565
566 #ifdef USE_MIXER
567 record_select (s, 0);
568 set_volume (s, AC97_Master_Volume_Mute, AUD_MIXER_VOLUME , 0x8000);
569 set_volume (s, AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM , 0x8808);
570 set_volume (s, AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN, 0x8808);
571 #endif
572 reset_voices (s, active);
573 }
574
575 /**
576 * Native audio mixer
577 * I/O Reads
578 */
579 static uint32_t nam_readb (void *opaque, uint32_t addr)
580 {
581 AC97LinkState *s = opaque;
582 dolog ("U nam readb %#x\n", addr);
583 s->cas = 0;
584 return ~0U;
585 }
586
587 static uint32_t nam_readw (void *opaque, uint32_t addr)
588 {
589 AC97LinkState *s = opaque;
590 uint32_t val = ~0U;
591 uint32_t index = addr - s->base[0];
592 s->cas = 0;
593 val = mixer_load (s, index);
594 return val;
595 }
596
597 static uint32_t nam_readl (void *opaque, uint32_t addr)
598 {
599 AC97LinkState *s = opaque;
600 dolog ("U nam readl %#x\n", addr);
601 s->cas = 0;
602 return ~0U;
603 }
604
605 /**
606 * Native audio mixer
607 * I/O Writes
608 */
609 static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)
610 {
611 AC97LinkState *s = opaque;
612 dolog ("U nam writeb %#x <- %#x\n", addr, val);
613 s->cas = 0;
614 }
615
616 static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
617 {
618 AC97LinkState *s = opaque;
619 uint32_t index = addr - s->base[0];
620 s->cas = 0;
621 switch (index) {
622 case AC97_Reset:
623 mixer_reset (s);
624 break;
625 case AC97_Powerdown_Ctrl_Stat:
626 val &= ~0xf;
627 val |= mixer_load (s, index) & 0xf;
628 mixer_store (s, index, val);
629 break;
630 #ifdef USE_MIXER
631 case AC97_Master_Volume_Mute:
632 set_volume (s, index, AUD_MIXER_VOLUME, val);
633 break;
634 case AC97_PCM_Out_Volume_Mute:
635 set_volume (s, index, AUD_MIXER_PCM, val);
636 break;
637 case AC97_Line_In_Volume_Mute:
638 set_volume (s, index, AUD_MIXER_LINE_IN, val);
639 break;
640 case AC97_Record_Select:
641 record_select (s, val);
642 break;
643 #endif
644 case AC97_Vendor_ID1:
645 case AC97_Vendor_ID2:
646 dolog ("Attempt to write vendor ID to %#x\n", val);
647 break;
648 case AC97_Extended_Audio_ID:
649 dolog ("Attempt to write extended audio ID to %#x\n", val);
650 break;
651 case AC97_Extended_Audio_Ctrl_Stat:
652 if (!(val & EACS_VRA)) {
653 mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80);
654 mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80);
655 open_voice (s, PI_INDEX, 48000);
656 open_voice (s, PO_INDEX, 48000);
657 }
658 if (!(val & EACS_VRM)) {
659 mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80);
660 open_voice (s, MC_INDEX, 48000);
661 }
662 dolog ("Setting extended audio control to %#x\n", val);
663 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val);
664 break;
665 case AC97_PCM_Front_DAC_Rate:
666 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
667 mixer_store (s, index, val);
668 dolog ("Set front DAC rate to %d\n", val);
669 open_voice (s, PO_INDEX, val);
670 }
671 else {
672 dolog ("Attempt to set front DAC rate to %d, "
673 "but VRA is not set\n",
674 val);
675 }
676 break;
677 case AC97_MIC_ADC_Rate:
678 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) {
679 mixer_store (s, index, val);
680 dolog ("Set MIC ADC rate to %d\n", val);
681 open_voice (s, MC_INDEX, val);
682 }
683 else {
684 dolog ("Attempt to set MIC ADC rate to %d, "
685 "but VRM is not set\n",
686 val);
687 }
688 break;
689 case AC97_PCM_LR_ADC_Rate:
690 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
691 mixer_store (s, index, val);
692 dolog ("Set front LR ADC rate to %d\n", val);
693 open_voice (s, PI_INDEX, val);
694 }
695 else {
696 dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n",
697 val);
698 }
699 break;
700 default:
701 dolog ("U nam writew %#x <- %#x\n", addr, val);
702 mixer_store (s, index, val);
703 break;
704 }
705 }
706
707 static void nam_writel (void *opaque, uint32_t addr, uint32_t val)
708 {
709 AC97LinkState *s = opaque;
710 dolog ("U nam writel %#x <- %#x\n", addr, val);
711 s->cas = 0;
712 }
713
714 /**
715 * Native audio bus master
716 * I/O Reads
717 */
718 static uint32_t nabm_readb (void *opaque, uint32_t addr)
719 {
720 AC97LinkState *s = opaque;
721 AC97BusMasterRegs *r = NULL;
722 uint32_t index = addr - s->base[1];
723 uint32_t val = ~0U;
724
725 switch (index) {
726 case CAS:
727 dolog ("CAS %d\n", s->cas);
728 val = s->cas;
729 s->cas = 1;
730 break;
731 case PI_CIV:
732 case PO_CIV:
733 case MC_CIV:
734 r = &s->bm_regs[GET_BM (index)];
735 val = r->civ;
736 dolog ("CIV[%d] -> %#x\n", GET_BM (index), val);
737 break;
738 case PI_LVI:
739 case PO_LVI:
740 case MC_LVI:
741 r = &s->bm_regs[GET_BM (index)];
742 val = r->lvi;
743 dolog ("LVI[%d] -> %#x\n", GET_BM (index), val);
744 break;
745 case PI_PIV:
746 case PO_PIV:
747 case MC_PIV:
748 r = &s->bm_regs[GET_BM (index)];
749 val = r->piv;
750 dolog ("PIV[%d] -> %#x\n", GET_BM (index), val);
751 break;
752 case PI_CR:
753 case PO_CR:
754 case MC_CR:
755 r = &s->bm_regs[GET_BM (index)];
756 val = r->cr;
757 dolog ("CR[%d] -> %#x\n", GET_BM (index), val);
758 break;
759 case PI_SR:
760 case PO_SR:
761 case MC_SR:
762 r = &s->bm_regs[GET_BM (index)];
763 val = r->sr & 0xff;
764 dolog ("SRb[%d] -> %#x\n", GET_BM (index), val);
765 break;
766 default:
767 dolog ("U nabm readb %#x -> %#x\n", addr, val);
768 break;
769 }
770 return val;
771 }
772
773 static uint32_t nabm_readw (void *opaque, uint32_t addr)
774 {
775 AC97LinkState *s = opaque;
776 AC97BusMasterRegs *r = NULL;
777 uint32_t index = addr - s->base[1];
778 uint32_t val = ~0U;
779
780 switch (index) {
781 case PI_SR:
782 case PO_SR:
783 case MC_SR:
784 r = &s->bm_regs[GET_BM (index)];
785 val = r->sr;
786 dolog ("SR[%d] -> %#x\n", GET_BM (index), val);
787 break;
788 case PI_PICB:
789 case PO_PICB:
790 case MC_PICB:
791 r = &s->bm_regs[GET_BM (index)];
792 val = r->picb;
793 dolog ("PICB[%d] -> %#x\n", GET_BM (index), val);
794 break;
795 default:
796 dolog ("U nabm readw %#x -> %#x\n", addr, val);
797 break;
798 }
799 return val;
800 }
801
802 static uint32_t nabm_readl (void *opaque, uint32_t addr)
803 {
804 AC97LinkState *s = opaque;
805 AC97BusMasterRegs *r = NULL;
806 uint32_t index = addr - s->base[1];
807 uint32_t val = ~0U;
808
809 switch (index) {
810 case PI_BDBAR:
811 case PO_BDBAR:
812 case MC_BDBAR:
813 r = &s->bm_regs[GET_BM (index)];
814 val = r->bdbar;
815 dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val);
816 break;
817 case PI_CIV:
818 case PO_CIV:
819 case MC_CIV:
820 r = &s->bm_regs[GET_BM (index)];
821 val = r->civ | (r->lvi << 8) | (r->sr << 16);
822 dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index),
823 r->civ, r->lvi, r->sr);
824 break;
825 case PI_PICB:
826 case PO_PICB:
827 case MC_PICB:
828 r = &s->bm_regs[GET_BM (index)];
829 val = r->picb | (r->piv << 16) | (r->cr << 24);
830 dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index),
831 val, r->picb, r->piv, r->cr);
832 break;
833 case GLOB_CNT:
834 val = s->glob_cnt;
835 dolog ("glob_cnt -> %#x\n", val);
836 break;
837 case GLOB_STA:
838 val = s->glob_sta | GS_S0CR;
839 dolog ("glob_sta -> %#x\n", val);
840 break;
841 default:
842 dolog ("U nabm readl %#x -> %#x\n", addr, val);
843 break;
844 }
845 return val;
846 }
847
848 /**
849 * Native audio bus master
850 * I/O Writes
851 */
852 static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
853 {
854 AC97LinkState *s = opaque;
855 AC97BusMasterRegs *r = NULL;
856 uint32_t index = addr - s->base[1];
857 switch (index) {
858 case PI_LVI:
859 case PO_LVI:
860 case MC_LVI:
861 r = &s->bm_regs[GET_BM (index)];
862 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) {
863 r->sr &= ~(SR_DCH | SR_CELV);
864 r->civ = r->piv;
865 r->piv = (r->piv + 1) % 32;
866 fetch_bd (s, r);
867 }
868 r->lvi = val % 32;
869 dolog ("LVI[%d] <- %#x\n", GET_BM (index), val);
870 break;
871 case PI_CR:
872 case PO_CR:
873 case MC_CR:
874 r = &s->bm_regs[GET_BM (index)];
875 if (val & CR_RR) {
876 reset_bm_regs (s, r);
877 }
878 else {
879 r->cr = val & CR_VALID_MASK;
880 if (!(r->cr & CR_RPBM)) {
881 voice_set_active (s, r - s->bm_regs, 0);
882 r->sr |= SR_DCH;
883 }
884 else {
885 r->civ = r->piv;
886 r->piv = (r->piv + 1) % 32;
887 fetch_bd (s, r);
888 r->sr &= ~SR_DCH;
889 voice_set_active (s, r - s->bm_regs, 1);
890 }
891 }
892 dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr);
893 break;
894 case PI_SR:
895 case PO_SR:
896 case MC_SR:
897 r = &s->bm_regs[GET_BM (index)];
898 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
899 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
900 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
901 break;
902 default:
903 dolog ("U nabm writeb %#x <- %#x\n", addr, val);
904 break;
905 }
906 }
907
908 static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
909 {
910 AC97LinkState *s = opaque;
911 AC97BusMasterRegs *r = NULL;
912 uint32_t index = addr - s->base[1];
913 switch (index) {
914 case PI_SR:
915 case PO_SR:
916 case MC_SR:
917 r = &s->bm_regs[GET_BM (index)];
918 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
919 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
920 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
921 break;
922 default:
923 dolog ("U nabm writew %#x <- %#x\n", addr, val);
924 break;
925 }
926 }
927
928 static void nabm_writel (void *opaque, uint32_t addr, uint32_t val)
929 {
930 AC97LinkState *s = opaque;
931 AC97BusMasterRegs *r = NULL;
932 uint32_t index = addr - s->base[1];
933 switch (index) {
934 case PI_BDBAR:
935 case PO_BDBAR:
936 case MC_BDBAR:
937 r = &s->bm_regs[GET_BM (index)];
938 r->bdbar = val & ~3;
939 dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n",
940 GET_BM (index), val, r->bdbar);
941 break;
942 case GLOB_CNT:
943 if (val & GC_WR)
944 warm_reset (s);
945 if (val & GC_CR)
946 cold_reset (s);
947 if (!(val & (GC_WR | GC_CR)))
948 s->glob_cnt = val & GC_VALID_MASK;
949 dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt);
950 break;
951 case GLOB_STA:
952 s->glob_sta &= ~(val & GS_WCLEAR_MASK);
953 s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
954 dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta);
955 break;
956 default:
957 dolog ("U nabm writel %#x <- %#x\n", addr, val);
958 break;
959 }
960 }
961
962 static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r,
963 int max, int *stop)
964 {
965 uint8_t tmpbuf[4096];
966 uint32_t addr = r->bd.addr;
967 uint32_t temp = r->picb << 1;
968 uint32_t written = 0;
969 int to_copy = 0;
970 struct iommu *iommu;
971 DeviceState *dev;
972
973 temp = audio_MIN (temp, max);
974
975 if (!temp) {
976 *stop = 1;
977 return 0;
978 }
979
980 iommu = iommu_get(&s->dev.qdev, &dev);
981
982 while (temp) {
983 int copied;
984 to_copy = audio_MIN (temp, sizeof (tmpbuf));
985 iommu_read (iommu, dev, addr, tmpbuf, to_copy);
986 copied = AUD_write (s->voice_po, tmpbuf, to_copy);
987 dolog ("write_audio max=%x to_copy=%x copied=%x\n",
988 max, to_copy, copied);
989 if (!copied) {
990 *stop = 1;
991 break;
992 }
993 temp -= copied;
994 addr += copied;
995 written += copied;
996 }
997
998 if (!temp) {
999 if (to_copy < 4) {
1000 dolog ("whoops\n");
1001 s->last_samp = 0;
1002 }
1003 else {
1004 s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4];
1005 }
1006 }
1007
1008 r->bd.addr = addr;
1009 return written;
1010 }
1011
1012 static void write_bup (AC97LinkState *s, int elapsed)
1013 {
1014 int written = 0;
1015
1016 dolog ("write_bup\n");
1017 if (!(s->bup_flag & BUP_SET)) {
1018 if (s->bup_flag & BUP_LAST) {
1019 int i;
1020 uint8_t *p = s->silence;
1021 for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) {
1022 *(uint32_t *) p = s->last_samp;
1023 }
1024 }
1025 else {
1026 memset (s->silence, 0, sizeof (s->silence));
1027 }
1028 s->bup_flag |= BUP_SET;
1029 }
1030
1031 while (elapsed) {
1032 int temp = audio_MIN (elapsed, sizeof (s->silence));
1033 while (temp) {
1034 int copied = AUD_write (s->voice_po, s->silence, temp);
1035 if (!copied)
1036 return;
1037 temp -= copied;
1038 elapsed -= copied;
1039 written += copied;
1040 }
1041 }
1042 }
1043
1044 static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r,
1045 int max, int *stop)
1046 {
1047 uint8_t tmpbuf[4096];
1048 uint32_t addr = r->bd.addr;
1049 uint32_t temp = r->picb << 1;
1050 uint32_t nread = 0;
1051 int to_copy = 0;
1052 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi;
1053 struct iommu *iommu;
1054 DeviceState *dev;
1055
1056 iommu = iommu_get(&s->dev.qdev, &dev);
1057
1058 temp = audio_MIN (temp, max);
1059
1060 if (!temp) {
1061 *stop = 1;
1062 return 0;
1063 }
1064
1065 while (temp) {
1066 int acquired;
1067 to_copy = audio_MIN (temp, sizeof (tmpbuf));
1068 acquired = AUD_read (voice, tmpbuf, to_copy);
1069 if (!acquired) {
1070 *stop = 1;
1071 break;
1072 }
1073 iommu_write (iommu, dev, addr, tmpbuf, acquired);
1074 temp -= acquired;
1075 addr += acquired;
1076 nread += acquired;
1077 }
1078
1079 r->bd.addr = addr;
1080 return nread;
1081 }
1082
1083 static void transfer_audio (AC97LinkState *s, int index, int elapsed)
1084 {
1085 AC97BusMasterRegs *r = &s->bm_regs[index];
1086 int written = 0, stop = 0;
1087
1088 if (s->invalid_freq[index]) {
1089 AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n",
1090 index, s->invalid_freq[index]);
1091 return;
1092 }
1093
1094 if (r->sr & SR_DCH) {
1095 if (r->cr & CR_RPBM) {
1096 switch (index) {
1097 case PO_INDEX:
1098 write_bup (s, elapsed);
1099 break;
1100 }
1101 }
1102 return;
1103 }
1104
1105 while ((elapsed >> 1) && !stop) {
1106 int temp;
1107
1108 if (!r->bd_valid) {
1109 dolog ("invalid bd\n");
1110 fetch_bd (s, r);
1111 }
1112
1113 if (!r->picb) {
1114 dolog ("fresh bd %d is empty %#x %#x\n",
1115 r->civ, r->bd.addr, r->bd.ctl_len);
1116 if (r->civ == r->lvi) {
1117 r->sr |= SR_DCH; /* CELV? */
1118 s->bup_flag = 0;
1119 break;
1120 }
1121 r->sr &= ~SR_CELV;
1122 r->civ = r->piv;
1123 r->piv = (r->piv + 1) % 32;
1124 fetch_bd (s, r);
1125 return;
1126 }
1127
1128 switch (index) {
1129 case PO_INDEX:
1130 temp = write_audio (s, r, elapsed, &stop);
1131 written += temp;
1132 elapsed -= temp;
1133 r->picb -= (temp >> 1);
1134 break;
1135
1136 case PI_INDEX:
1137 case MC_INDEX:
1138 temp = read_audio (s, r, elapsed, &stop);
1139 elapsed -= temp;
1140 r->picb -= (temp >> 1);
1141 break;
1142 }
1143
1144 if (!r->picb) {
1145 uint32_t new_sr = r->sr & ~SR_CELV;
1146
1147 if (r->bd.ctl_len & BD_IOC) {
1148 new_sr |= SR_BCIS;
1149 }
1150
1151 if (r->civ == r->lvi) {
1152 dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi);
1153
1154 new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
1155 stop = 1;
1156 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1157 }
1158 else {
1159 r->civ = r->piv;
1160 r->piv = (r->piv + 1) % 32;
1161 fetch_bd (s, r);
1162 }
1163
1164 update_sr (s, r, new_sr);
1165 }
1166 }
1167 }
1168
1169 static void pi_callback (void *opaque, int avail)
1170 {
1171 transfer_audio (opaque, PI_INDEX, avail);
1172 }
1173
1174 static void mc_callback (void *opaque, int avail)
1175 {
1176 transfer_audio (opaque, MC_INDEX, avail);
1177 }
1178
1179 static void po_callback (void *opaque, int free)
1180 {
1181 transfer_audio (opaque, PO_INDEX, free);
1182 }
1183
1184 static const VMStateDescription vmstate_ac97_bm_regs = {
1185 .name = "ac97_bm_regs",
1186 .version_id = 1,
1187 .minimum_version_id = 1,
1188 .minimum_version_id_old = 1,
1189 .fields = (VMStateField []) {
1190 VMSTATE_UINT32(bdbar, AC97BusMasterRegs),
1191 VMSTATE_UINT8(civ, AC97BusMasterRegs),
1192 VMSTATE_UINT8(lvi, AC97BusMasterRegs),
1193 VMSTATE_UINT16(sr, AC97BusMasterRegs),
1194 VMSTATE_UINT16(picb, AC97BusMasterRegs),
1195 VMSTATE_UINT8(piv, AC97BusMasterRegs),
1196 VMSTATE_UINT8(cr, AC97BusMasterRegs),
1197 VMSTATE_UINT32(bd_valid, AC97BusMasterRegs),
1198 VMSTATE_UINT32(bd.addr, AC97BusMasterRegs),
1199 VMSTATE_UINT32(bd.ctl_len, AC97BusMasterRegs),
1200 VMSTATE_END_OF_LIST()
1201 }
1202 };
1203
1204 static int ac97_post_load (void *opaque, int version_id)
1205 {
1206 uint8_t active[LAST_INDEX];
1207 AC97LinkState *s = opaque;
1208
1209 #ifdef USE_MIXER
1210 record_select (s, mixer_load (s, AC97_Record_Select));
1211 #define V_(a, b) set_volume (s, a, b, mixer_load (s, a))
1212 V_ (AC97_Master_Volume_Mute, AUD_MIXER_VOLUME);
1213 V_ (AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM);
1214 V_ (AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN);
1215 #undef V_
1216 #endif
1217 active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM);
1218 active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM);
1219 active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM);
1220 reset_voices (s, active);
1221
1222 s->bup_flag = 0;
1223 s->last_samp = 0;
1224 return 0;
1225 }
1226
1227 static bool is_version_2 (void *opaque, int version_id)
1228 {
1229 return version_id == 2;
1230 }
1231
1232 static const VMStateDescription vmstate_ac97 = {
1233 .name = "ac97",
1234 .version_id = 3,
1235 .minimum_version_id = 2,
1236 .minimum_version_id_old = 2,
1237 .post_load = ac97_post_load,
1238 .fields = (VMStateField []) {
1239 VMSTATE_PCI_DEVICE(dev, AC97LinkState),
1240 VMSTATE_UINT32(glob_cnt, AC97LinkState),
1241 VMSTATE_UINT32(glob_sta, AC97LinkState),
1242 VMSTATE_UINT32(cas, AC97LinkState),
1243 VMSTATE_STRUCT_ARRAY(bm_regs, AC97LinkState, 3, 1,
1244 vmstate_ac97_bm_regs, AC97BusMasterRegs),
1245 VMSTATE_BUFFER(mixer_data, AC97LinkState),
1246 VMSTATE_UNUSED_TEST(is_version_2, 3),
1247 VMSTATE_END_OF_LIST()
1248 }
1249 };
1250
1251 static void ac97_map (PCIDevice *pci_dev, int region_num,
1252 pcibus_t addr, pcibus_t size, int type)
1253 {
1254 AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, pci_dev);
1255 PCIDevice *d = &s->dev;
1256
1257 if (!region_num) {
1258 s->base[0] = addr;
1259 register_ioport_read (addr, 256 * 1, 1, nam_readb, d);
1260 register_ioport_read (addr, 256 * 2, 2, nam_readw, d);
1261 register_ioport_read (addr, 256 * 4, 4, nam_readl, d);
1262 register_ioport_write (addr, 256 * 1, 1, nam_writeb, d);
1263 register_ioport_write (addr, 256 * 2, 2, nam_writew, d);
1264 register_ioport_write (addr, 256 * 4, 4, nam_writel, d);
1265 }
1266 else {
1267 s->base[1] = addr;
1268 register_ioport_read (addr, 64 * 1, 1, nabm_readb, d);
1269 register_ioport_read (addr, 64 * 2, 2, nabm_readw, d);
1270 register_ioport_read (addr, 64 * 4, 4, nabm_readl, d);
1271 register_ioport_write (addr, 64 * 1, 1, nabm_writeb, d);
1272 register_ioport_write (addr, 64 * 2, 2, nabm_writew, d);
1273 register_ioport_write (addr, 64 * 4, 4, nabm_writel, d);
1274 }
1275 }
1276
1277 static void ac97_on_reset (void *opaque)
1278 {
1279 AC97LinkState *s = opaque;
1280
1281 reset_bm_regs (s, &s->bm_regs[0]);
1282 reset_bm_regs (s, &s->bm_regs[1]);
1283 reset_bm_regs (s, &s->bm_regs[2]);
1284
1285 /*
1286 * Reset the mixer too. The Windows XP driver seems to rely on
1287 * this. At least it wants to read the vendor id before it resets
1288 * the codec manually.
1289 */
1290 mixer_reset (s);
1291 }
1292
1293 static int ac97_initfn (PCIDevice *dev)
1294 {
1295 AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
1296 uint8_t *c = s->dev.config;
1297
1298 pci_config_set_vendor_id (c, PCI_VENDOR_ID_INTEL); /* ro */
1299 pci_config_set_device_id (c, PCI_DEVICE_ID_INTEL_82801AA_5); /* ro */
1300
1301 /* TODO: no need to override */
1302 c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
1303 c[PCI_COMMAND + 1] = 0x00;
1304
1305 /* TODO: */
1306 c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
1307 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
1308
1309 c[PCI_REVISION_ID] = 0x01; /* rid revision ro */
1310 c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
1311 pci_config_set_class (c, PCI_CLASS_MULTIMEDIA_AUDIO); /* ro */
1312 c[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* headtyp header type ro */
1313
1314 /* TODO set when bar is registered. no need to override. */
1315 /* nabmar native audio mixer base address rw */
1316 c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
1317 c[PCI_BASE_ADDRESS_0 + 1] = 0x00;
1318 c[PCI_BASE_ADDRESS_0 + 2] = 0x00;
1319 c[PCI_BASE_ADDRESS_0 + 3] = 0x00;
1320
1321 /* TODO set when bar is registered. no need to override. */
1322 /* nabmbar native audio bus mastering base address rw */
1323 c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO;
1324 c[PCI_BASE_ADDRESS_0 + 5] = 0x00;
1325 c[PCI_BASE_ADDRESS_0 + 6] = 0x00;
1326 c[PCI_BASE_ADDRESS_0 + 7] = 0x00;
1327
1328 c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86; /* svid subsystem vendor id rwo */
1329 c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80;
1330
1331 c[PCI_SUBSYSTEM_ID] = 0x00; /* sid subsystem id rwo */
1332 c[PCI_SUBSYSTEM_ID + 1] = 0x00;
1333
1334 c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
1335 /* TODO: RST# value should be 0. */
1336 c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
1337
1338 pci_register_bar (&s->dev, 0, 256 * 4, PCI_BASE_ADDRESS_SPACE_IO,
1339 ac97_map);
1340 pci_register_bar (&s->dev, 1, 64 * 4, PCI_BASE_ADDRESS_SPACE_IO, ac97_map);
1341 qemu_register_reset (ac97_on_reset, s);
1342 AUD_register_card ("ac97", &s->card);
1343 ac97_on_reset (s);
1344 return 0;
1345 }
1346
1347 int ac97_init (PCIBus *bus)
1348 {
1349 pci_create_simple (bus, -1, "AC97");
1350 return 0;
1351 }
1352
1353 static PCIDeviceInfo ac97_info = {
1354 .qdev.name = "AC97",
1355 .qdev.desc = "Intel 82801AA AC97 Audio",
1356 .qdev.size = sizeof (AC97LinkState),
1357 .qdev.vmsd = &vmstate_ac97,
1358 .init = ac97_initfn,
1359 };
1360
1361 static void ac97_register (void)
1362 {
1363 pci_qdev_register (&ac97_info);
1364 }
1365 device_init (ac97_register);
1366
AMD IOMMU emulation for KVM