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Add io memory to test device
[qemu-kvm/amd-iommu.git] / qemu-kvm-x86.c
blob5af9ce145d81c3b10a5bbd9026fc0bbccda78237
1 /*
2 * qemu/kvm integration, x86 specific code
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 *
6 * Licensed under the terms of the GNU GPL version 2 or higher.
7 */
8
9 #include "config.h"
10 #include "config-host.h"
11
12 #include <string.h>
13 #include "hw/hw.h"
14 #include "gdbstub.h"
15 #include <sys/io.h>
16
17 #include "qemu-kvm.h"
18 #include "libkvm.h"
19 #include <pthread.h>
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
22 #include <sys/ioctl.h>
23
24 #include "kvm.h"
25 #include "hw/pc.h"
26
27 #define MSR_IA32_TSC 0x10
28
29 static struct kvm_msr_list *kvm_msr_list;
30 extern unsigned int kvm_shadow_memory;
31 static int kvm_has_msr_star;
32 static int kvm_has_vm_hsave_pa;
33
34 static int lm_capable_kernel;
35
36 int kvm_set_tss_addr(kvm_context_t kvm, unsigned long addr)
37 {
38 #ifdef KVM_CAP_SET_TSS_ADDR
39 int r;
40
41 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
42 if (r > 0) {
43 r = kvm_vm_ioctl(kvm_state, KVM_SET_TSS_ADDR, addr);
44 if (r < 0) {
45 fprintf(stderr, "kvm_set_tss_addr: %m\n");
46 return r;
47 }
48 return 0;
49 }
50 #endif
51 return -ENOSYS;
52 }
53
54 static int kvm_init_tss(kvm_context_t kvm)
55 {
56 #ifdef KVM_CAP_SET_TSS_ADDR
57 int r;
58
59 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
60 if (r > 0) {
61 /*
62 * this address is 3 pages before the bios, and the bios should present
63 * as unavaible memory
64 */
65 r = kvm_set_tss_addr(kvm, 0xfeffd000);
66 if (r < 0) {
67 fprintf(stderr, "kvm_init_tss: unable to set tss addr\n");
68 return r;
69 }
70
71 }
72 #endif
73 return 0;
74 }
75
76 static int kvm_set_identity_map_addr(kvm_context_t kvm, uint64_t addr)
77 {
78 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
79 int r;
80
81 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
82 if (r > 0) {
83 r = kvm_vm_ioctl(kvm_state, KVM_SET_IDENTITY_MAP_ADDR, &addr);
84 if (r == -1) {
85 fprintf(stderr, "kvm_set_identity_map_addr: %m\n");
86 return -errno;
87 }
88 return 0;
89 }
90 #endif
91 return -ENOSYS;
92 }
93
94 static int kvm_init_identity_map_page(kvm_context_t kvm)
95 {
96 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
97 int r;
98
99 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_SET_IDENTITY_MAP_ADDR);
100 if (r > 0) {
101 /*
102 * this address is 4 pages before the bios, and the bios should present
103 * as unavaible memory
104 */
105 r = kvm_set_identity_map_addr(kvm, 0xfeffc000);
106 if (r < 0) {
107 fprintf(stderr, "kvm_init_identity_map_page: "
108 "unable to set identity mapping addr\n");
109 return r;
110 }
111
112 }
113 #endif
114 return 0;
115 }
116
117 static int kvm_create_pit(kvm_context_t kvm)
118 {
119 #ifdef KVM_CAP_PIT
120 int r;
121
122 kvm_state->pit_in_kernel = 0;
123 if (!kvm->no_pit_creation) {
124 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_PIT);
125 if (r > 0) {
126 r = kvm_vm_ioctl(kvm_state, KVM_CREATE_PIT);
127 if (r >= 0)
128 kvm_state->pit_in_kernel = 1;
129 else {
130 fprintf(stderr, "Create kernel PIC irqchip failed\n");
131 return r;
132 }
133 }
134 }
135 #endif
136 return 0;
137 }
138
139 int kvm_arch_create(kvm_context_t kvm, unsigned long phys_mem_bytes,
140 void **vm_mem)
141 {
142 int r = 0;
143
144 r = kvm_init_tss(kvm);
145 if (r < 0)
146 return r;
147
148 r = kvm_init_identity_map_page(kvm);
149 if (r < 0)
150 return r;
151
152 r = kvm_create_pit(kvm);
153 if (r < 0)
154 return r;
155
156 r = kvm_init_coalesced_mmio(kvm);
157 if (r < 0)
158 return r;
159
160 #ifdef KVM_EXIT_TPR_ACCESS
161 kvm_tpr_opt_setup();
162 #endif
163
164 return 0;
165 }
166
167 #ifdef KVM_EXIT_TPR_ACCESS
168
169 static int kvm_handle_tpr_access(CPUState *env)
170 {
171 struct kvm_run *run = env->kvm_run;
172 kvm_tpr_access_report(env,
173 run->tpr_access.rip,
174 run->tpr_access.is_write);
175 return 0;
176 }
177
178
179 int kvm_enable_vapic(CPUState *env, uint64_t vapic)
180 {
181 struct kvm_vapic_addr va = {
182 .vapic_addr = vapic,
183 };
184
185 return kvm_vcpu_ioctl(env, KVM_SET_VAPIC_ADDR, &va);
186 }
187
188 #endif
189
190 int kvm_arch_run(CPUState *env)
191 {
192 int r = 0;
193 struct kvm_run *run = env->kvm_run;
194
195
196 switch (run->exit_reason) {
197 #ifdef KVM_EXIT_SET_TPR
198 case KVM_EXIT_SET_TPR:
199 break;
200 #endif
201 #ifdef KVM_EXIT_TPR_ACCESS
202 case KVM_EXIT_TPR_ACCESS:
203 r = kvm_handle_tpr_access(env);
204 break;
205 #endif
206 default:
207 r = 1;
208 break;
209 }
210
211 return r;
212 }
213
214 #define MAX_ALIAS_SLOTS 4
215 static struct {
216 uint64_t start;
217 uint64_t len;
218 } kvm_aliases[MAX_ALIAS_SLOTS];
219
220 static int get_alias_slot(uint64_t start)
221 {
222 int i;
223
224 for (i=0; i<MAX_ALIAS_SLOTS; i++)
225 if (kvm_aliases[i].start == start)
226 return i;
227 return -1;
228 }
229 static int get_free_alias_slot(void)
230 {
231 int i;
232
233 for (i=0; i<MAX_ALIAS_SLOTS; i++)
234 if (kvm_aliases[i].len == 0)
235 return i;
236 return -1;
237 }
238
239 static void register_alias(int slot, uint64_t start, uint64_t len)
240 {
241 kvm_aliases[slot].start = start;
242 kvm_aliases[slot].len = len;
243 }
244
245 int kvm_create_memory_alias(kvm_context_t kvm,
246 uint64_t phys_start,
247 uint64_t len,
248 uint64_t target_phys)
249 {
250 struct kvm_memory_alias alias = {
251 .flags = 0,
252 .guest_phys_addr = phys_start,
253 .memory_size = len,
254 .target_phys_addr = target_phys,
255 };
256 int r;
257 int slot;
258
259 slot = get_alias_slot(phys_start);
260 if (slot < 0)
261 slot = get_free_alias_slot();
262 if (slot < 0)
263 return -EBUSY;
264 alias.slot = slot;
265
266 r = kvm_vm_ioctl(kvm_state, KVM_SET_MEMORY_ALIAS, &alias);
267 if (r == -1)
268 return -errno;
269
270 register_alias(slot, phys_start, len);
271 return 0;
272 }
273
274 int kvm_destroy_memory_alias(kvm_context_t kvm, uint64_t phys_start)
275 {
276 return kvm_create_memory_alias(kvm, phys_start, 0, 0);
277 }
278
279 #ifdef KVM_CAP_IRQCHIP
280
281 int kvm_get_lapic(CPUState *env, struct kvm_lapic_state *s)
282 {
283 int r = 0;
284
285 if (!kvm_irqchip_in_kernel())
286 return r;
287
288 r = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, s);
289 if (r < 0)
290 fprintf(stderr, "KVM_GET_LAPIC failed\n");
291 return r;
292 }
293
294 int kvm_set_lapic(CPUState *env, struct kvm_lapic_state *s)
295 {
296 int r = 0;
297
298 if (!kvm_irqchip_in_kernel())
299 return 0;
300
301 r = kvm_vcpu_ioctl(env, KVM_SET_LAPIC, s);
302
303 if (r < 0)
304 fprintf(stderr, "KVM_SET_LAPIC failed\n");
305 return r;
306 }
307
308 #endif
309
310 #ifdef KVM_CAP_PIT
311
312 int kvm_get_pit(kvm_context_t kvm, struct kvm_pit_state *s)
313 {
314 if (!kvm_pit_in_kernel())
315 return 0;
316 return kvm_vm_ioctl(kvm_state, KVM_GET_PIT, s);
317 }
318
319 int kvm_set_pit(kvm_context_t kvm, struct kvm_pit_state *s)
320 {
321 if (!kvm_pit_in_kernel())
322 return 0;
323 return kvm_vm_ioctl(kvm_state, KVM_SET_PIT, s);
324 }
325
326 #ifdef KVM_CAP_PIT_STATE2
327 int kvm_get_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
328 {
329 if (!kvm_pit_in_kernel())
330 return 0;
331 return kvm_vm_ioctl(kvm_state, KVM_GET_PIT2, ps2);
332 }
333
334 int kvm_set_pit2(kvm_context_t kvm, struct kvm_pit_state2 *ps2)
335 {
336 if (!kvm_pit_in_kernel())
337 return 0;
338 return kvm_vm_ioctl(kvm_state, KVM_SET_PIT2, ps2);
339 }
340
341 #endif
342 #endif
343
344 int kvm_has_pit_state2(kvm_context_t kvm)
345 {
346 int r = 0;
347
348 #ifdef KVM_CAP_PIT_STATE2
349 r = kvm_check_extension(kvm_state, KVM_CAP_PIT_STATE2);
350 #endif
351 return r;
352 }
353
354 void kvm_show_code(CPUState *env)
355 {
356 #define SHOW_CODE_LEN 50
357 struct kvm_regs regs;
358 struct kvm_sregs sregs;
359 int r, n;
360 int back_offset;
361 unsigned char code;
362 char code_str[SHOW_CODE_LEN * 3 + 1];
363 unsigned long rip;
364
365 r = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
366 if (r < 0 ) {
367 perror("KVM_GET_SREGS");
368 return;
369 }
370 r = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
371 if (r < 0) {
372 perror("KVM_GET_REGS");
373 return;
374 }
375 rip = sregs.cs.base + regs.rip;
376 back_offset = regs.rip;
377 if (back_offset > 20)
378 back_offset = 20;
379 *code_str = 0;
380 for (n = -back_offset; n < SHOW_CODE_LEN-back_offset; ++n) {
381 if (n == 0)
382 strcat(code_str, " -->");
383 cpu_physical_memory_rw(rip + n, &code, 1, 1);
384 sprintf(code_str + strlen(code_str), " %02x", code);
385 }
386 fprintf(stderr, "code:%s\n", code_str);
387 }
388
389
390 /*
391 * Returns available msr list. User must free.
392 */
393 struct kvm_msr_list *kvm_get_msr_list(kvm_context_t kvm)
394 {
395 struct kvm_msr_list sizer, *msrs;
396 int r;
397
398 sizer.nmsrs = 0;
399 r = kvm_ioctl(kvm_state, KVM_GET_MSR_INDEX_LIST, &sizer);
400 if (r < 0 && r != -E2BIG)
401 return NULL;
402 /* Old kernel modules had a bug and could write beyond the provided
403 memory. Allocate at least a safe amount of 1K. */
404 msrs = qemu_malloc(MAX(1024, sizeof(*msrs) +
405 sizer.nmsrs * sizeof(*msrs->indices)));
406
407 msrs->nmsrs = sizer.nmsrs;
408 r = kvm_ioctl(kvm_state, KVM_GET_MSR_INDEX_LIST, msrs);
409 if (r < 0) {
410 free(msrs);
411 errno = r;
412 return NULL;
413 }
414 return msrs;
415 }
416
417 int kvm_get_msrs(CPUState *env, struct kvm_msr_entry *msrs, int n)
418 {
419 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
420 int r;
421
422 kmsrs->nmsrs = n;
423 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
424 r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
425 memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
426 free(kmsrs);
427 return r;
428 }
429
430 int kvm_set_msrs(CPUState *env, struct kvm_msr_entry *msrs, int n)
431 {
432 struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
433 int r;
434
435 kmsrs->nmsrs = n;
436 memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
437 r = kvm_vcpu_ioctl(env, KVM_SET_MSRS, kmsrs);
438 free(kmsrs);
439 return r;
440 }
441
442 int kvm_get_mce_cap_supported(kvm_context_t kvm, uint64_t *mce_cap,
443 int *max_banks)
444 {
445 #ifdef KVM_CAP_MCE
446 int r;
447
448 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_MCE);
449 if (r > 0) {
450 *max_banks = r;
451 return kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
452 }
453 #endif
454 return -ENOSYS;
455 }
456
457 int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
458 {
459 #ifdef KVM_CAP_MCE
460 return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
461 #else
462 return -ENOSYS;
463 #endif
464 }
465
466 int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
467 {
468 #ifdef KVM_CAP_MCE
469 return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
470 #else
471 return -ENOSYS;
472 #endif
473 }
474
475 static void print_seg(FILE *file, const char *name, struct kvm_segment *seg)
476 {
477 fprintf(stderr,
478 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
479 " g %d avl %d)\n",
480 name, seg->selector, seg->base, seg->limit, seg->present,
481 seg->dpl, seg->db, seg->s, seg->type, seg->l, seg->g,
482 seg->avl);
483 }
484
485 static void print_dt(FILE *file, const char *name, struct kvm_dtable *dt)
486 {
487 fprintf(stderr, "%s %llx/%x\n", name, dt->base, dt->limit);
488 }
489
490 void kvm_show_regs(CPUState *env)
491 {
492 struct kvm_regs regs;
493 struct kvm_sregs sregs;
494 int r;
495
496 r = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
497 if (r < 0) {
498 perror("KVM_GET_REGS");
499 return;
500 }
501 fprintf(stderr,
502 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
503 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
504 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
505 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
506 "rip %016llx rflags %08llx\n",
507 regs.rax, regs.rbx, regs.rcx, regs.rdx,
508 regs.rsi, regs.rdi, regs.rsp, regs.rbp,
509 regs.r8, regs.r9, regs.r10, regs.r11,
510 regs.r12, regs.r13, regs.r14, regs.r15,
511 regs.rip, regs.rflags);
512 r = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
513 if (r < 0) {
514 perror("KVM_GET_SREGS");
515 return;
516 }
517 print_seg(stderr, "cs", &sregs.cs);
518 print_seg(stderr, "ds", &sregs.ds);
519 print_seg(stderr, "es", &sregs.es);
520 print_seg(stderr, "ss", &sregs.ss);
521 print_seg(stderr, "fs", &sregs.fs);
522 print_seg(stderr, "gs", &sregs.gs);
523 print_seg(stderr, "tr", &sregs.tr);
524 print_seg(stderr, "ldt", &sregs.ldt);
525 print_dt(stderr, "gdt", &sregs.gdt);
526 print_dt(stderr, "idt", &sregs.idt);
527 fprintf(stderr, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
528 " efer %llx\n",
529 sregs.cr0, sregs.cr2, sregs.cr3, sregs.cr4, sregs.cr8,
530 sregs.efer);
531 }
532
533 static void kvm_set_cr8(CPUState *env, uint64_t cr8)
534 {
535 env->kvm_run->cr8 = cr8;
536 }
537
538 int kvm_setup_cpuid(CPUState *env, int nent,
539 struct kvm_cpuid_entry *entries)
540 {
541 struct kvm_cpuid *cpuid;
542 int r;
543
544 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
545
546 cpuid->nent = nent;
547 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
548 r = kvm_vcpu_ioctl(env, KVM_SET_CPUID, cpuid);
549
550 free(cpuid);
551 return r;
552 }
553
554 int kvm_setup_cpuid2(CPUState *env, int nent,
555 struct kvm_cpuid_entry2 *entries)
556 {
557 struct kvm_cpuid2 *cpuid;
558 int r;
559
560 cpuid = qemu_malloc(sizeof(*cpuid) + nent * sizeof(*entries));
561
562 cpuid->nent = nent;
563 memcpy(cpuid->entries, entries, nent * sizeof(*entries));
564 r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, cpuid);
565 free(cpuid);
566 return r;
567 }
568
569 int kvm_set_shadow_pages(kvm_context_t kvm, unsigned int nrshadow_pages)
570 {
571 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
572 int r;
573
574 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION,
575 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
576 if (r > 0) {
577 r = kvm_vm_ioctl(kvm_state, KVM_SET_NR_MMU_PAGES, nrshadow_pages);
578 if (r < 0) {
579 fprintf(stderr, "kvm_set_shadow_pages: %m\n");
580 return r;
581 }
582 return 0;
583 }
584 #endif
585 return -1;
586 }
587
588 int kvm_get_shadow_pages(kvm_context_t kvm, unsigned int *nrshadow_pages)
589 {
590 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
591 int r;
592
593 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION,
594 KVM_CAP_MMU_SHADOW_CACHE_CONTROL);
595 if (r > 0) {
596 *nrshadow_pages = kvm_vm_ioctl(kvm_state, KVM_GET_NR_MMU_PAGES);
597 return 0;
598 }
599 #endif
600 return -1;
601 }
602
603 #ifdef KVM_CAP_VAPIC
604
605 static int tpr_access_reporting(CPUState *env, int enabled)
606 {
607 int r;
608 struct kvm_tpr_access_ctl tac = {
609 .enabled = enabled,
610 };
611
612 r = kvm_ioctl(kvm_state, KVM_CHECK_EXTENSION, KVM_CAP_VAPIC);
613 if (r <= 0)
614 return -ENOSYS;
615 return kvm_vcpu_ioctl(env, KVM_TPR_ACCESS_REPORTING, &tac);
616 }
617
618 int kvm_enable_tpr_access_reporting(CPUState *env)
619 {
620 return tpr_access_reporting(env, 1);
621 }
622
623 int kvm_disable_tpr_access_reporting(CPUState *env)
624 {
625 return tpr_access_reporting(env, 0);
626 }
627
628 #endif
629
630 int kvm_qemu_create_memory_alias(uint64_t phys_start,
631 uint64_t len,
632 uint64_t target_phys)
633 {
634 return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
635 }
636
637 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
638 {
639 return kvm_destroy_memory_alias(kvm_context, phys_start);
640 }
641
642 #ifdef KVM_CAP_ADJUST_CLOCK
643 static struct kvm_clock_data kvmclock_data;
644
645 static void kvmclock_pre_save(void *opaque)
646 {
647 struct kvm_clock_data *cl = opaque;
648
649 kvm_vm_ioctl(kvm_state, KVM_GET_CLOCK, cl);
650 }
651
652 static int kvmclock_post_load(void *opaque, int version_id)
653 {
654 struct kvm_clock_data *cl = opaque;
655
656 return kvm_vm_ioctl(kvm_state, KVM_SET_CLOCK, cl);
657 }
658
659 static const VMStateDescription vmstate_kvmclock= {
660 .name = "kvmclock",
661 .version_id = 1,
662 .minimum_version_id = 1,
663 .minimum_version_id_old = 1,
664 .pre_save = kvmclock_pre_save,
665 .post_load = kvmclock_post_load,
666 .fields = (VMStateField []) {
667 VMSTATE_U64(clock, struct kvm_clock_data),
668 VMSTATE_END_OF_LIST()
669 }
670 };
671 #endif
672
673 int kvm_arch_qemu_create_context(void)
674 {
675 int i;
676 struct utsname utsname;
677
678 uname(&utsname);
679 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
680
681 if (kvm_shadow_memory)
682 kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
683
684 kvm_msr_list = kvm_get_msr_list(kvm_context);
685 if (!kvm_msr_list)
686 return -1;
687 for (i = 0; i < kvm_msr_list->nmsrs; ++i) {
688 if (kvm_msr_list->indices[i] == MSR_STAR)
689 kvm_has_msr_star = 1;
690 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA)
691 kvm_has_vm_hsave_pa = 1;
692 }
693
694 #ifdef KVM_CAP_ADJUST_CLOCK
695 if (kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK))
696 vmstate_register(0, &vmstate_kvmclock, &kvmclock_data);
697 #endif
698 return 0;
699 }
700
701 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
702 uint64_t data)
703 {
704 entry->index = index;
705 entry->data = data;
706 }
707
708 /* returns 0 on success, non-0 on failure */
709 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
710 {
711 switch (entry->index) {
712 case MSR_IA32_SYSENTER_CS:
713 env->sysenter_cs = entry->data;
714 break;
715 case MSR_IA32_SYSENTER_ESP:
716 env->sysenter_esp = entry->data;
717 break;
718 case MSR_IA32_SYSENTER_EIP:
719 env->sysenter_eip = entry->data;
720 break;
721 case MSR_STAR:
722 env->star = entry->data;
723 break;
724 #ifdef TARGET_X86_64
725 case MSR_CSTAR:
726 env->cstar = entry->data;
727 break;
728 case MSR_KERNELGSBASE:
729 env->kernelgsbase = entry->data;
730 break;
731 case MSR_FMASK:
732 env->fmask = entry->data;
733 break;
734 case MSR_LSTAR:
735 env->lstar = entry->data;
736 break;
737 #endif
738 case MSR_IA32_TSC:
739 env->tsc = entry->data;
740 break;
741 case MSR_VM_HSAVE_PA:
742 env->vm_hsave = entry->data;
743 break;
744 case MSR_KVM_SYSTEM_TIME:
745 env->system_time_msr = entry->data;
746 break;
747 case MSR_KVM_WALL_CLOCK:
748 env->wall_clock_msr = entry->data;
749 break;
750 default:
751 printf("Warning unknown msr index 0x%x\n", entry->index);
752 return 1;
753 }
754 return 0;
755 }
756
757 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
758 {
759 lhs->selector = rhs->selector;
760 lhs->base = rhs->base;
761 lhs->limit = rhs->limit;
762 lhs->type = 3;
763 lhs->present = 1;
764 lhs->dpl = 3;
765 lhs->db = 0;
766 lhs->s = 1;
767 lhs->l = 0;
768 lhs->g = 0;
769 lhs->avl = 0;
770 lhs->unusable = 0;
771 }
772
773 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
774 {
775 unsigned flags = rhs->flags;
776 lhs->selector = rhs->selector;
777 lhs->base = rhs->base;
778 lhs->limit = rhs->limit;
779 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
780 lhs->present = (flags & DESC_P_MASK) != 0;
781 lhs->dpl = rhs->selector & 3;
782 lhs->db = (flags >> DESC_B_SHIFT) & 1;
783 lhs->s = (flags & DESC_S_MASK) != 0;
784 lhs->l = (flags >> DESC_L_SHIFT) & 1;
785 lhs->g = (flags & DESC_G_MASK) != 0;
786 lhs->avl = (flags & DESC_AVL_MASK) != 0;
787 lhs->unusable = 0;
788 }
789
790 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
791 {
792 lhs->selector = rhs->selector;
793 lhs->base = rhs->base;
794 lhs->limit = rhs->limit;
795 lhs->flags =
796 (rhs->type << DESC_TYPE_SHIFT)
797 | (rhs->present * DESC_P_MASK)
798 | (rhs->dpl << DESC_DPL_SHIFT)
799 | (rhs->db << DESC_B_SHIFT)
800 | (rhs->s * DESC_S_MASK)
801 | (rhs->l << DESC_L_SHIFT)
802 | (rhs->g * DESC_G_MASK)
803 | (rhs->avl * DESC_AVL_MASK);
804 }
805
806 void kvm_arch_load_regs(CPUState *env)
807 {
808 struct kvm_regs regs;
809 struct kvm_fpu fpu;
810 struct kvm_sregs sregs;
811 struct kvm_msr_entry msrs[100];
812 int rc, n, i;
813
814 assert(kvm_cpu_is_stopped(env) || env->thread_id == kvm_get_thread_id());
815
816 regs.rax = env->regs[R_EAX];
817 regs.rbx = env->regs[R_EBX];
818 regs.rcx = env->regs[R_ECX];
819 regs.rdx = env->regs[R_EDX];
820 regs.rsi = env->regs[R_ESI];
821 regs.rdi = env->regs[R_EDI];
822 regs.rsp = env->regs[R_ESP];
823 regs.rbp = env->regs[R_EBP];
824 #ifdef TARGET_X86_64
825 regs.r8 = env->regs[8];
826 regs.r9 = env->regs[9];
827 regs.r10 = env->regs[10];
828 regs.r11 = env->regs[11];
829 regs.r12 = env->regs[12];
830 regs.r13 = env->regs[13];
831 regs.r14 = env->regs[14];
832 regs.r15 = env->regs[15];
833 #endif
834
835 regs.rflags = env->eflags;
836 regs.rip = env->eip;
837
838 kvm_set_regs(env, &regs);
839
840 memset(&fpu, 0, sizeof fpu);
841 fpu.fsw = env->fpus & ~(7 << 11);
842 fpu.fsw |= (env->fpstt & 7) << 11;
843 fpu.fcw = env->fpuc;
844 for (i = 0; i < 8; ++i)
845 fpu.ftwx |= (!env->fptags[i]) << i;
846 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
847 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
848 fpu.mxcsr = env->mxcsr;
849 kvm_set_fpu(env, &fpu);
850
851 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
852 if (env->interrupt_injected >= 0) {
853 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
854 (uint64_t)1 << (env->interrupt_injected % 64);
855 }
856
857 if ((env->eflags & VM_MASK)) {
858 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
859 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
860 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
861 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
862 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
863 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
864 } else {
865 set_seg(&sregs.cs, &env->segs[R_CS]);
866 set_seg(&sregs.ds, &env->segs[R_DS]);
867 set_seg(&sregs.es, &env->segs[R_ES]);
868 set_seg(&sregs.fs, &env->segs[R_FS]);
869 set_seg(&sregs.gs, &env->segs[R_GS]);
870 set_seg(&sregs.ss, &env->segs[R_SS]);
871
872 if (env->cr[0] & CR0_PE_MASK) {
873 /* force ss cpl to cs cpl */
874 sregs.ss.selector = (sregs.ss.selector & ~3) |
875 (sregs.cs.selector & 3);
876 sregs.ss.dpl = sregs.ss.selector & 3;
877 }
878 }
879
880 set_seg(&sregs.tr, &env->tr);
881 set_seg(&sregs.ldt, &env->ldt);
882
883 sregs.idt.limit = env->idt.limit;
884 sregs.idt.base = env->idt.base;
885 sregs.gdt.limit = env->gdt.limit;
886 sregs.gdt.base = env->gdt.base;
887
888 sregs.cr0 = env->cr[0];
889 sregs.cr2 = env->cr[2];
890 sregs.cr3 = env->cr[3];
891 sregs.cr4 = env->cr[4];
892
893 sregs.cr8 = cpu_get_apic_tpr(env);
894 sregs.apic_base = cpu_get_apic_base(env);
895
896 sregs.efer = env->efer;
897
898 kvm_set_sregs(env, &sregs);
899
900 /* msrs */
901 n = 0;
902 /* Remember to increase msrs size if you add new registers below */
903 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
904 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
905 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
906 if (kvm_has_msr_star)
907 set_msr_entry(&msrs[n++], MSR_STAR, env->star);
908 if (kvm_has_vm_hsave_pa)
909 set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
910 #ifdef TARGET_X86_64
911 if (lm_capable_kernel) {
912 set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar);
913 set_msr_entry(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
914 set_msr_entry(&msrs[n++], MSR_FMASK, env->fmask);
915 set_msr_entry(&msrs[n++], MSR_LSTAR , env->lstar);
916 }
917 #endif
918 set_msr_entry(&msrs[n++], MSR_KVM_SYSTEM_TIME, env->system_time_msr);
919 set_msr_entry(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
920
921 rc = kvm_set_msrs(env, msrs, n);
922 if (rc == -1)
923 perror("kvm_set_msrs FAILED");
924
925 /*
926 * Kernels before 2.6.33 (which correlates with !kvm_has_vcpu_events())
927 * overwrote flags.TF injected via SET_GUEST_DEBUG while updating GP regs.
928 * Work around this by updating the debug state once again if
929 * single-stepping is on.
930 * Another reason to call kvm_update_guest_debug here is a pending debug
931 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
932 * reinject them via SET_GUEST_DEBUG.
933 */
934 if (!kvm_has_vcpu_events() &&
935 (env->exception_injected != -1 || env->singlestep_enabled)) {
936 unsigned long reinject_trap = 0;
937
938 if (env->exception_injected == 1) {
939 reinject_trap = KVM_GUESTDBG_INJECT_DB;
940 } else if (env->exception_injected == 3) {
941 reinject_trap = KVM_GUESTDBG_INJECT_BP;
942 }
943 env->exception_injected = -1;
944
945 rc = kvm_update_guest_debug(env, reinject_trap);
946 if (rc < 0) {
947 perror("kvm_update_guest_debug FAILED");
948 }
949 }
950 }
951
952 void kvm_load_tsc(CPUState *env)
953 {
954 int rc;
955 struct kvm_msr_entry msr;
956
957 set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
958
959 rc = kvm_set_msrs(env, &msr, 1);
960 if (rc == -1)
961 perror("kvm_set_tsc FAILED.\n");
962 }
963
964 void kvm_arch_save_mpstate(CPUState *env)
965 {
966 #ifdef KVM_CAP_MP_STATE
967 int r;
968 struct kvm_mp_state mp_state;
969
970 r = kvm_get_mpstate(env, &mp_state);
971 if (r < 0)
972 env->mp_state = -1;
973 else
974 env->mp_state = mp_state.mp_state;
975 #else
976 env->mp_state = -1;
977 #endif
978 }
979
980 void kvm_arch_load_mpstate(CPUState *env)
981 {
982 #ifdef KVM_CAP_MP_STATE
983 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
984
985 /*
986 * -1 indicates that the host did not support GET_MP_STATE ioctl,
987 * so don't touch it.
988 */
989 if (env->mp_state != -1)
990 kvm_set_mpstate(env, &mp_state);
991 #endif
992 }
993
994 void kvm_arch_save_regs(CPUState *env)
995 {
996 struct kvm_regs regs;
997 struct kvm_fpu fpu;
998 struct kvm_sregs sregs;
999 struct kvm_msr_entry msrs[100];
1000 uint32_t hflags;
1001 uint32_t i, n, rc, bit;
1002
1003 assert(kvm_cpu_is_stopped(env) || env->thread_id == kvm_get_thread_id());
1004
1005 kvm_get_regs(env, &regs);
1006
1007 env->regs[R_EAX] = regs.rax;
1008 env->regs[R_EBX] = regs.rbx;
1009 env->regs[R_ECX] = regs.rcx;
1010 env->regs[R_EDX] = regs.rdx;
1011 env->regs[R_ESI] = regs.rsi;
1012 env->regs[R_EDI] = regs.rdi;
1013 env->regs[R_ESP] = regs.rsp;
1014 env->regs[R_EBP] = regs.rbp;
1015 #ifdef TARGET_X86_64
1016 env->regs[8] = regs.r8;
1017 env->regs[9] = regs.r9;
1018 env->regs[10] = regs.r10;
1019 env->regs[11] = regs.r11;
1020 env->regs[12] = regs.r12;
1021 env->regs[13] = regs.r13;
1022 env->regs[14] = regs.r14;
1023 env->regs[15] = regs.r15;
1024 #endif
1025
1026 env->eflags = regs.rflags;
1027 env->eip = regs.rip;
1028
1029 kvm_get_fpu(env, &fpu);
1030 env->fpstt = (fpu.fsw >> 11) & 7;
1031 env->fpus = fpu.fsw;
1032 env->fpuc = fpu.fcw;
1033 for (i = 0; i < 8; ++i)
1034 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1035 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1036 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1037 env->mxcsr = fpu.mxcsr;
1038
1039 kvm_get_sregs(env, &sregs);
1040
1041 /* There can only be one pending IRQ set in the bitmap at a time, so try
1042 to find it and save its number instead (-1 for none). */
1043 env->interrupt_injected = -1;
1044 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1045 if (sregs.interrupt_bitmap[i]) {
1046 bit = ctz64(sregs.interrupt_bitmap[i]);
1047 env->interrupt_injected = i * 64 + bit;
1048 break;
1049 }
1050 }
1051
1052 get_seg(&env->segs[R_CS], &sregs.cs);
1053 get_seg(&env->segs[R_DS], &sregs.ds);
1054 get_seg(&env->segs[R_ES], &sregs.es);
1055 get_seg(&env->segs[R_FS], &sregs.fs);
1056 get_seg(&env->segs[R_GS], &sregs.gs);
1057 get_seg(&env->segs[R_SS], &sregs.ss);
1058
1059 get_seg(&env->tr, &sregs.tr);
1060 get_seg(&env->ldt, &sregs.ldt);
1061
1062 env->idt.limit = sregs.idt.limit;
1063 env->idt.base = sregs.idt.base;
1064 env->gdt.limit = sregs.gdt.limit;
1065 env->gdt.base = sregs.gdt.base;
1066
1067 env->cr[0] = sregs.cr0;
1068 env->cr[2] = sregs.cr2;
1069 env->cr[3] = sregs.cr3;
1070 env->cr[4] = sregs.cr4;
1071
1072 cpu_set_apic_base(env, sregs.apic_base);
1073
1074 env->efer = sregs.efer;
1075 //cpu_set_apic_tpr(env, sregs.cr8);
1076
1077 #define HFLAG_COPY_MASK ~( \
1078 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1079 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1080 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1081 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1082
1083
1084
1085 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1086 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1087 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1088 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1089 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1090 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1091 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1092
1093 if (env->efer & MSR_EFER_LMA) {
1094 hflags |= HF_LMA_MASK;
1095 }
1096
1097 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1098 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1099 } else {
1100 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1101 (DESC_B_SHIFT - HF_CS32_SHIFT);
1102 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1103 (DESC_B_SHIFT - HF_SS32_SHIFT);
1104 if (!(env->cr[0] & CR0_PE_MASK) ||
1105 (env->eflags & VM_MASK) ||
1106 !(hflags & HF_CS32_MASK)) {
1107 hflags |= HF_ADDSEG_MASK;
1108 } else {
1109 hflags |= ((env->segs[R_DS].base |
1110 env->segs[R_ES].base |
1111 env->segs[R_SS].base) != 0) <<
1112 HF_ADDSEG_SHIFT;
1113 }
1114 }
1115 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1116
1117 /* msrs */
1118 n = 0;
1119 /* Remember to increase msrs size if you add new registers below */
1120 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1121 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1122 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1123 if (kvm_has_msr_star)
1124 msrs[n++].index = MSR_STAR;
1125 msrs[n++].index = MSR_IA32_TSC;
1126 if (kvm_has_vm_hsave_pa)
1127 msrs[n++].index = MSR_VM_HSAVE_PA;
1128 #ifdef TARGET_X86_64
1129 if (lm_capable_kernel) {
1130 msrs[n++].index = MSR_CSTAR;
1131 msrs[n++].index = MSR_KERNELGSBASE;
1132 msrs[n++].index = MSR_FMASK;
1133 msrs[n++].index = MSR_LSTAR;
1134 }
1135 #endif
1136 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1137 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1138
1139 rc = kvm_get_msrs(env, msrs, n);
1140 if (rc == -1) {
1141 perror("kvm_get_msrs FAILED");
1142 }
1143 else {
1144 n = rc; /* actual number of MSRs */
1145 for (i=0 ; i<n; i++) {
1146 if (get_msr_entry(&msrs[i], env))
1147 return;
1148 }
1149 }
1150 kvm_arch_save_mpstate(env);
1151 }
1152
1153 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
1154 uint32_t count, CPUState *env)
1155 {
1156 env->regs[R_EAX] = function;
1157 env->regs[R_ECX] = count;
1158 qemu_kvm_cpuid_on_env(env);
1159 e->function = function;
1160 e->flags = 0;
1161 e->index = 0;
1162 e->eax = env->regs[R_EAX];
1163 e->ebx = env->regs[R_EBX];
1164 e->ecx = env->regs[R_ECX];
1165 e->edx = env->regs[R_EDX];
1166 }
1167
1168 struct kvm_para_features {
1169 int cap;
1170 int feature;
1171 } para_features[] = {
1172 #ifdef KVM_CAP_CLOCKSOURCE
1173 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
1174 #endif
1175 #ifdef KVM_CAP_NOP_IO_DELAY
1176 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
1177 #endif
1178 #ifdef KVM_CAP_PV_MMU
1179 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
1180 #endif
1181 { -1, -1 }
1182 };
1183
1184 static int get_para_features(kvm_context_t kvm_context)
1185 {
1186 int i, features = 0;
1187
1188 for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
1189 if (kvm_check_extension(kvm_state, para_features[i].cap))
1190 features |= (1 << para_features[i].feature);
1191 }
1192
1193 return features;
1194 }
1195
1196 static void kvm_trim_features(uint32_t *features, uint32_t supported)
1197 {
1198 int i;
1199 uint32_t mask;
1200
1201 for (i = 0; i < 32; ++i) {
1202 mask = 1U << i;
1203 if ((*features & mask) && !(supported & mask)) {
1204 *features &= ~mask;
1205 }
1206 }
1207 }
1208
1209 int kvm_arch_init_vcpu(CPUState *cenv)
1210 {
1211 struct kvm_cpuid_entry2 cpuid_ent[100];
1212 #ifdef KVM_CPUID_SIGNATURE
1213 struct kvm_cpuid_entry2 *pv_ent;
1214 uint32_t signature[3];
1215 #endif
1216 int cpuid_nent = 0;
1217 CPUState copy;
1218 uint32_t i, j, limit;
1219
1220 qemu_kvm_load_lapic(cenv);
1221
1222 cenv->interrupt_injected = -1;
1223
1224 #ifdef KVM_CPUID_SIGNATURE
1225 /* Paravirtualization CPUIDs */
1226 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1227 pv_ent = &cpuid_ent[cpuid_nent++];
1228 memset(pv_ent, 0, sizeof(*pv_ent));
1229 pv_ent->function = KVM_CPUID_SIGNATURE;
1230 pv_ent->eax = 0;
1231 pv_ent->ebx = signature[0];
1232 pv_ent->ecx = signature[1];
1233 pv_ent->edx = signature[2];
1234
1235 pv_ent = &cpuid_ent[cpuid_nent++];
1236 memset(pv_ent, 0, sizeof(*pv_ent));
1237 pv_ent->function = KVM_CPUID_FEATURES;
1238 pv_ent->eax = get_para_features(kvm_context);
1239 #endif
1240
1241 kvm_trim_features(&cenv->cpuid_features,
1242 kvm_arch_get_supported_cpuid(cenv, 1, R_EDX));
1243
1244 /* prevent the hypervisor bit from being cleared by the kernel */
1245 i = cenv->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
1246 kvm_trim_features(&cenv->cpuid_ext_features,
1247 kvm_arch_get_supported_cpuid(cenv, 1, R_ECX));
1248 cenv->cpuid_ext_features |= i;
1249
1250 kvm_trim_features(&cenv->cpuid_ext2_features,
1251 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_EDX));
1252 kvm_trim_features(&cenv->cpuid_ext3_features,
1253 kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_ECX));
1254
1255 copy = *cenv;
1256
1257 copy.regs[R_EAX] = 0;
1258 qemu_kvm_cpuid_on_env(&copy);
1259 limit = copy.regs[R_EAX];
1260
1261 for (i = 0; i <= limit; ++i) {
1262 if (i == 4 || i == 0xb || i == 0xd) {
1263 for (j = 0; ; ++j) {
1264 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
1265
1266 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1267 cpuid_ent[cpuid_nent].index = j;
1268
1269 cpuid_nent++;
1270
1271 if (i == 4 && copy.regs[R_EAX] == 0)
1272 break;
1273 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
1274 break;
1275 if (i == 0xd && copy.regs[R_EAX] == 0)
1276 break;
1277 }
1278 } else
1279 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1280 }
1281
1282 copy.regs[R_EAX] = 0x80000000;
1283 qemu_kvm_cpuid_on_env(&copy);
1284 limit = copy.regs[R_EAX];
1285
1286 for (i = 0x80000000; i <= limit; ++i)
1287 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
1288
1289 kvm_setup_cpuid2(cenv, cpuid_nent, cpuid_ent);
1290
1291 #ifdef KVM_CAP_MCE
1292 if (((cenv->cpuid_version >> 8)&0xF) >= 6
1293 && (cenv->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
1294 && kvm_check_extension(kvm_state, KVM_CAP_MCE) > 0) {
1295 uint64_t mcg_cap;
1296 int banks;
1297
1298 if (kvm_get_mce_cap_supported(kvm_context, &mcg_cap, &banks))
1299 perror("kvm_get_mce_cap_supported FAILED");
1300 else {
1301 if (banks > MCE_BANKS_DEF)
1302 banks = MCE_BANKS_DEF;
1303 mcg_cap &= MCE_CAP_DEF;
1304 mcg_cap |= banks;
1305 if (kvm_setup_mce(cenv, &mcg_cap))
1306 perror("kvm_setup_mce FAILED");
1307 else
1308 cenv->mcg_cap = mcg_cap;
1309 }
1310 }
1311 #endif
1312
1313 #ifdef KVM_EXIT_TPR_ACCESS
1314 kvm_tpr_vcpu_start(cenv);
1315 #endif
1316 return 0;
1317 }
1318
1319 int kvm_arch_halt(CPUState *env)
1320 {
1321
1322 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1323 (env->eflags & IF_MASK)) &&
1324 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1325 env->halted = 1;
1326 }
1327 return 1;
1328 }
1329
1330 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1331 {
1332 if (env->update_vapic) {
1333 kvm_tpr_enable_vapic(env);
1334 }
1335 if (!kvm_irqchip_in_kernel())
1336 kvm_set_cr8(env, cpu_get_apic_tpr(env));
1337 return 0;
1338 }
1339
1340 int kvm_arch_has_work(CPUState *env)
1341 {
1342 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1343 (env->eflags & IF_MASK)) ||
1344 (env->interrupt_request & CPU_INTERRUPT_NMI))
1345 return 1;
1346 return 0;
1347 }
1348
1349 int kvm_arch_try_push_interrupts(void *opaque)
1350 {
1351 CPUState *env = cpu_single_env;
1352 int r, irq;
1353
1354 if (kvm_is_ready_for_interrupt_injection(env) &&
1355 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1356 (env->eflags & IF_MASK)) {
1357 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1358 irq = cpu_get_pic_interrupt(env);
1359 if (irq >= 0) {
1360 r = kvm_inject_irq(env, irq);
1361 if (r < 0)
1362 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
1363 }
1364 }
1365
1366 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
1367 }
1368
1369 #ifdef KVM_CAP_USER_NMI
1370 void kvm_arch_push_nmi(void *opaque)
1371 {
1372 CPUState *env = cpu_single_env;
1373 int r;
1374
1375 if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
1376 return;
1377
1378 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1379 r = kvm_inject_nmi(env);
1380 if (r < 0)
1381 printf("cpu %d fail inject NMI\n", env->cpu_index);
1382 }
1383 #endif /* KVM_CAP_USER_NMI */
1384
1385 void kvm_arch_cpu_reset(CPUState *env)
1386 {
1387 kvm_arch_reset_vcpu(env);
1388 kvm_arch_load_regs(env);
1389 kvm_put_vcpu_events(env);
1390 if (!cpu_is_bsp(env)) {
1391 if (kvm_irqchip_in_kernel()) {
1392 #ifdef KVM_CAP_MP_STATE
1393 kvm_reset_mpstate(env);
1394 #endif
1395 } else {
1396 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1397 env->halted = 1;
1398 }
1399 }
1400 }
1401
1402 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
1403 void kvm_arch_do_ioperm(void *_data)
1404 {
1405 struct ioperm_data *data = _data;
1406 ioperm(data->start_port, data->num, data->turn_on);
1407 }
1408 #endif
1409
1410 /*
1411 * Setup x86 specific IRQ routing
1412 */
1413 int kvm_arch_init_irq_routing(void)
1414 {
1415 int i, r;
1416
1417 if (kvm_irqchip && kvm_has_gsi_routing(kvm_context)) {
1418 kvm_clear_gsi_routes(kvm_context);
1419 for (i = 0; i < 8; ++i) {
1420 if (i == 2)
1421 continue;
1422 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_MASTER, i);
1423 if (r < 0)
1424 return r;
1425 }
1426 for (i = 8; i < 16; ++i) {
1427 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
1428 if (r < 0)
1429 return r;
1430 }
1431 for (i = 0; i < 24; ++i) {
1432 if (i == 0) {
1433 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, 2);
1434 } else if (i != 2) {
1435 r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i);
1436 }
1437 if (r < 0)
1438 return r;
1439 }
1440 kvm_commit_irq_routes(kvm_context);
1441 }
1442 return 0;
1443 }
1444
1445 void kvm_arch_process_irqchip_events(CPUState *env)
1446 {
1447 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1448 kvm_cpu_synchronize_state(env);
1449 do_cpu_init(env);
1450 }
1451 if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1452 kvm_cpu_synchronize_state(env);
1453 do_cpu_sipi(env);
1454 }
1455 }
AMD IOMMU emulation for KVM