hw/unin_pci.c

   1 /*
   2  * QEMU Uninorth PCI host (for all Mac99 and newer machines)
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc_mac.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28
  29 /* debug UniNorth */
  30 //#define DEBUG_UNIN
  31
  32 #ifdef DEBUG_UNIN
  33 #define UNIN_DPRINTF(fmt, ...)                                  \
  34     do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define UNIN_DPRINTF(fmt, ...)
  37 #endif
  38
  39 static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
  40
  41 typedef struct UNINState {
  42     SysBusDevice busdev;
  43     PCIHostState host_state;
  44     ReadWriteHandler data_handler;
  45 } UNINState;
  46
  47 static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
  48 {
  49     int retval;
  50     int devfn = pci_dev->devfn & 0x00FFFFFF;
  51
  52     retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
  53
  54     return retval;
  55 }
  56
  57 static void pci_unin_set_irq(void *opaque, int irq_num, int level)
  58 {
  59     qemu_irq *pic = opaque;
  60
  61     UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
  62                  unin_irq_line[irq_num], level);
  63     qemu_set_irq(pic[unin_irq_line[irq_num]], level);
  64 }
  65
  66 static void pci_unin_save(QEMUFile* f, void *opaque)
  67 {
  68     PCIDevice *d = opaque;
  69
  70     pci_device_save(d, f);
  71 }
  72
  73 static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
  74 {
  75     PCIDevice *d = opaque;
  76
  77     if (version_id != 1)
  78         return -EINVAL;
  79
  80     return pci_device_load(d, f);
  81 }
  82
  83 static void pci_unin_reset(void *opaque)
  84 {
  85 }
  86
  87 static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
  88 {
  89     uint32_t retval;
  90
  91     if (reg & (1u << 31)) {
  92         /* XXX OpenBIOS compatibility hack */
  93         retval = reg | (addr & 3);
  94     } else if (reg & 1) {
  95         /* CFA1 style */
  96         retval = (reg & ~7u) | (addr & 7);
  97     } else {
  98         uint32_t slot, func;
  99
 100         /* Grab CFA0 style values */
 101         slot = ffs(reg & 0xfffff800) - 1;
 102         func = (reg >> 8) & 7;
 103
 104         /* ... and then convert them to x86 format */
 105         /* config pointer */
 106         retval = (reg & (0xff - 7)) | (addr & 7);
 107         /* slot */
 108         retval |= slot << 11;
 109         /* fn */
 110         retval |= func << 8;
 111     }
 112
 113
 114     UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
 115                  reg, addr, retval);
 116
 117     return retval;
 118 }
 119
 120 static void unin_data_write(ReadWriteHandler *handler,
 121                             pcibus_t addr, uint32_t val, int len)
 122 {
 123     UNINState *s = container_of(handler, UNINState, data_handler);
 124     val = qemu_bswap_len(val, len);
 125     UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
 126     pci_data_write(s->host_state.bus,
 127                    unin_get_config_reg(s->host_state.config_reg, addr),
 128                    val, len);
 129 }
 130
 131 static uint32_t unin_data_read(ReadWriteHandler *handler,
 132                                pcibus_t addr, int len)
 133 {
 134     UNINState *s = container_of(handler, UNINState, data_handler);
 135     uint32_t val;
 136
 137     val = pci_data_read(s->host_state.bus,
 138                         unin_get_config_reg(s->host_state.config_reg, addr),
 139                         len);
 140     UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
 141     val = qemu_bswap_len(val, len);
 142     return val;
 143 }
 144
 145 static int pci_unin_main_init_device(SysBusDevice *dev)
 146 {
 147     UNINState *s;
 148     int pci_mem_config, pci_mem_data;
 149
 150     /* Use values found on a real PowerMac */
 151     /* Uninorth main bus */
 152     s = FROM_SYSBUS(UNINState, dev);
 153
 154     pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
 155     s->data_handler.read = unin_data_read;
 156     s->data_handler.write = unin_data_write;
 157     pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
 158     sysbus_init_mmio(dev, 0x1000, pci_mem_config);
 159     sysbus_init_mmio(dev, 0x1000, pci_mem_data);
 160
 161     register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
 162     qemu_register_reset(pci_unin_reset, &s->host_state);
 163     return 0;
 164 }
 165
 166 static int pci_u3_agp_init_device(SysBusDevice *dev)
 167 {
 168     UNINState *s;
 169     int pci_mem_config, pci_mem_data;
 170
 171     /* Uninorth U3 AGP bus */
 172     s = FROM_SYSBUS(UNINState, dev);
 173
 174     pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
 175     s->data_handler.read = unin_data_read;
 176     s->data_handler.write = unin_data_write;
 177     pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
 178     sysbus_init_mmio(dev, 0x1000, pci_mem_config);
 179     sysbus_init_mmio(dev, 0x1000, pci_mem_data);
 180
 181     register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
 182     qemu_register_reset(pci_unin_reset, &s->host_state);
 183
 184     return 0;
 185 }
 186
 187 static int pci_unin_agp_init_device(SysBusDevice *dev)
 188 {
 189     UNINState *s;
 190     int pci_mem_config, pci_mem_data;
 191
 192     /* Uninorth AGP bus */
 193     s = FROM_SYSBUS(UNINState, dev);
 194
 195     pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
 196     pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
 197     sysbus_init_mmio(dev, 0x1000, pci_mem_config);
 198     sysbus_init_mmio(dev, 0x1000, pci_mem_data);
 199     return 0;
 200 }
 201
 202 static int pci_unin_internal_init_device(SysBusDevice *dev)
 203 {
 204     UNINState *s;
 205     int pci_mem_config, pci_mem_data;
 206
 207     /* Uninorth internal bus */
 208     s = FROM_SYSBUS(UNINState, dev);
 209
 210     pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
 211     pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
 212     sysbus_init_mmio(dev, 0x1000, pci_mem_config);
 213     sysbus_init_mmio(dev, 0x1000, pci_mem_data);
 214     return 0;
 215 }
 216
 217 PCIBus *pci_pmac_init(qemu_irq *pic)
 218 {
 219     DeviceState *dev;
 220     SysBusDevice *s;
 221     UNINState *d;
 222
 223     /* Use values found on a real PowerMac */
 224     /* Uninorth main bus */
 225     dev = qdev_create(NULL, "uni-north");
 226     qdev_init_nofail(dev);
 227     s = sysbus_from_qdev(dev);
 228     d = FROM_SYSBUS(UNINState, s);
 229     d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
 230                                          pci_unin_set_irq, pci_unin_map_irq,
 231                                          pic, 11 << 3, 4);
 232
 233 #if 0
 234     pci_create_simple(d->host_state.bus, 11 << 3, "uni-north");
 235 #endif
 236
 237     sysbus_mmio_map(s, 0, 0xf2800000);
 238     sysbus_mmio_map(s, 1, 0xf2c00000);
 239
 240     /* DEC 21154 bridge */
 241 #if 0
 242     /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
 243     pci_create_simple(d->host_state.bus, 12 << 3, "dec-21154");
 244 #endif
 245
 246     /* Uninorth AGP bus */
 247     pci_create_simple(d->host_state.bus, 11 << 3, "uni-north-agp");
 248     dev = qdev_create(NULL, "uni-north-agp");
 249     qdev_init_nofail(dev);
 250     s = sysbus_from_qdev(dev);
 251     sysbus_mmio_map(s, 0, 0xf0800000);
 252     sysbus_mmio_map(s, 1, 0xf0c00000);
 253
 254     /* Uninorth internal bus */
 255 #if 0
 256     /* XXX: not needed for now */
 257     pci_create_simple(d->host_state.bus, 14 << 3, "uni-north-pci");
 258     dev = qdev_create(NULL, "uni-north-pci");
 259     qdev_init_nofail(dev);
 260     s = sysbus_from_qdev(dev);
 261     sysbus_mmio_map(s, 0, 0xf4800000);
 262     sysbus_mmio_map(s, 1, 0xf4c00000);
 263 #endif
 264
 265     return d->host_state.bus;
 266 }
 267
 268 PCIBus *pci_pmac_u3_init(qemu_irq *pic)
 269 {
 270     DeviceState *dev;
 271     SysBusDevice *s;
 272     UNINState *d;
 273
 274     /* Uninorth AGP bus */
 275
 276     dev = qdev_create(NULL, "u3-agp");
 277     qdev_init_nofail(dev);
 278     s = sysbus_from_qdev(dev);
 279     d = FROM_SYSBUS(UNINState, s);
 280
 281     d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
 282                                          pci_unin_set_irq, pci_unin_map_irq,
 283                                          pic, 11 << 3, 4);
 284
 285     sysbus_mmio_map(s, 0, 0xf0800000);
 286     sysbus_mmio_map(s, 1, 0xf0c00000);
 287
 288     pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");
 289
 290     return d->host_state.bus;
 291 }
 292
 293 static int unin_main_pci_host_init(PCIDevice *d)
 294 {
 295     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
 296     pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
 297     d->config[0x08] = 0x00; // revision
 298     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 299     d->config[0x0C] = 0x08; // cache_line_size
 300     d->config[0x0D] = 0x10; // latency_timer
 301     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 302     d->config[0x34] = 0x00; // capabilities_pointer
 303     return 0;
 304 }
 305
 306 static int unin_agp_pci_host_init(PCIDevice *d)
 307 {
 308     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
 309     pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
 310     d->config[0x08] = 0x00; // revision
 311     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 312     d->config[0x0C] = 0x08; // cache_line_size
 313     d->config[0x0D] = 0x10; // latency_timer
 314     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 315     //    d->config[0x34] = 0x80; // capabilities_pointer
 316     return 0;
 317 }
 318
 319 static int u3_agp_pci_host_init(PCIDevice *d)
 320 {
 321     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
 322     pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_U3_AGP);
 323     /* revision */
 324     d->config[0x08] = 0x00;
 325     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 326     /* cache line size */
 327     d->config[0x0C] = 0x08;
 328     /* latency timer */
 329     d->config[0x0D] = 0x10;
 330     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
 331     return 0;
 332 }
 333
 334 static int unin_internal_pci_host_init(PCIDevice *d)
 335 {
 336     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
 337     pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
 338     d->config[0x08] = 0x00; // revision
 339     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 340     d->config[0x0C] = 0x08; // cache_line_size
 341     d->config[0x0D] = 0x10; // latency_timer
 342     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 343     d->config[0x34] = 0x00; // capabilities_pointer
 344     return 0;
 345 }
 346
 347 static PCIDeviceInfo unin_main_pci_host_info = {
 348     .qdev.name = "uni-north",
 349     .qdev.size = sizeof(PCIDevice),
 350     .init      = unin_main_pci_host_init,
 351 };
 352
 353 static PCIDeviceInfo u3_agp_pci_host_info = {
 354     .qdev.name = "u3-agp",
 355     .qdev.size = sizeof(PCIDevice),
 356     .init      = u3_agp_pci_host_init,
 357 };
 358
 359 static PCIDeviceInfo unin_agp_pci_host_info = {
 360     .qdev.name = "uni-north-agp",
 361     .qdev.size = sizeof(PCIDevice),
 362     .init      = unin_agp_pci_host_init,
 363 };
 364
 365 static PCIDeviceInfo unin_internal_pci_host_info = {
 366     .qdev.name = "uni-north-pci",
 367     .qdev.size = sizeof(PCIDevice),
 368     .init      = unin_internal_pci_host_init,
 369 };
 370
 371 static void unin_register_devices(void)
 372 {
 373     sysbus_register_dev("uni-north", sizeof(UNINState),
 374                         pci_unin_main_init_device);
 375     pci_qdev_register(&unin_main_pci_host_info);
 376     sysbus_register_dev("u3-agp", sizeof(UNINState),
 377                         pci_u3_agp_init_device);
 378     pci_qdev_register(&u3_agp_pci_host_info);
 379     sysbus_register_dev("uni-north-agp", sizeof(UNINState),
 380                         pci_unin_agp_init_device);
 381     pci_qdev_register(&unin_agp_pci_host_info);
 382     sysbus_register_dev("uni-north-pci", sizeof(UNINState),
 383                         pci_unin_internal_init_device);
 384     pci_qdev_register(&unin_internal_pci_host_info);
 385 }
 386
 387 device_init(unin_register_devices)