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Merge commit 'ca35f780ac4654bfa086613c72b011448afff327' into upstream-merge
[qemu-kvm/amd-iommu.git] / hw / pxa2xx.c
blob909538653c5e2286ea770e32b97f95e99e9d32f2
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licenced under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "pxa.h"
12 #include "sysemu.h"
13 #include "pc.h"
14 #include "i2c.h"
15 #include "ssi.h"
16 #include "qemu-timer.h"
17 #include "qemu-char.h"
18
19 static struct {
20 target_phys_addr_t io_base;
21 int irqn;
22 } pxa255_serial[] = {
23 { 0x40100000, PXA2XX_PIC_FFUART },
24 { 0x40200000, PXA2XX_PIC_BTUART },
25 { 0x40700000, PXA2XX_PIC_STUART },
26 { 0x41600000, PXA25X_PIC_HWUART },
27 { 0, 0 }
28 }, pxa270_serial[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART },
30 { 0x40200000, PXA2XX_PIC_BTUART },
31 { 0x40700000, PXA2XX_PIC_STUART },
32 { 0, 0 }
33 };
34
35 typedef struct PXASSPDef {
36 target_phys_addr_t io_base;
37 int irqn;
38 } PXASSPDef;
39
40 #if 0
41 static PXASSPDef pxa250_ssp[] = {
42 { 0x41000000, PXA2XX_PIC_SSP },
43 { 0, 0 }
44 };
45 #endif
46
47 static PXASSPDef pxa255_ssp[] = {
48 { 0x41000000, PXA2XX_PIC_SSP },
49 { 0x41400000, PXA25X_PIC_NSSP },
50 { 0, 0 }
51 };
52
53 #if 0
54 static PXASSPDef pxa26x_ssp[] = {
55 { 0x41000000, PXA2XX_PIC_SSP },
56 { 0x41400000, PXA25X_PIC_NSSP },
57 { 0x41500000, PXA26X_PIC_ASSP },
58 { 0, 0 }
59 };
60 #endif
61
62 static PXASSPDef pxa27x_ssp[] = {
63 { 0x41000000, PXA2XX_PIC_SSP },
64 { 0x41700000, PXA27X_PIC_SSP2 },
65 { 0x41900000, PXA2XX_PIC_SSP3 },
66 { 0, 0 }
67 };
68
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90
91 static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
92 {
93 PXA2xxState *s = (PXA2xxState *) opaque;
94
95 switch (addr) {
96 case PMCR ... PCMD31:
97 if (addr & 3)
98 goto fail;
99
100 return s->pm_regs[addr >> 2];
101 default:
102 fail:
103 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
104 break;
105 }
106 return 0;
107 }
108
109 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
110 uint32_t value)
111 {
112 PXA2xxState *s = (PXA2xxState *) opaque;
113
114 switch (addr) {
115 case PMCR:
116 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
117 s->pm_regs[addr >> 2] |= value & 0x15;
118 break;
119
120 case PSSR: /* Read-clean registers */
121 case RCSR:
122 case PKSR:
123 s->pm_regs[addr >> 2] &= ~value;
124 break;
125
126 default: /* Read-write registers */
127 if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) {
128 s->pm_regs[addr >> 2] = value;
129 break;
130 }
131
132 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
133 break;
134 }
135 }
136
137 static CPUReadMemoryFunc * const pxa2xx_pm_readfn[] = {
138 pxa2xx_pm_read,
139 pxa2xx_pm_read,
140 pxa2xx_pm_read,
141 };
142
143 static CPUWriteMemoryFunc * const pxa2xx_pm_writefn[] = {
144 pxa2xx_pm_write,
145 pxa2xx_pm_write,
146 pxa2xx_pm_write,
147 };
148
149 static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
150 {
151 PXA2xxState *s = (PXA2xxState *) opaque;
152 int i;
153
154 for (i = 0; i < 0x40; i ++)
155 qemu_put_be32s(f, &s->pm_regs[i]);
156 }
157
158 static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
159 {
160 PXA2xxState *s = (PXA2xxState *) opaque;
161 int i;
162
163 for (i = 0; i < 0x40; i ++)
164 qemu_get_be32s(f, &s->pm_regs[i]);
165
166 return 0;
167 }
168
169 #define CCCR 0x00 /* Core Clock Configuration register */
170 #define CKEN 0x04 /* Clock Enable register */
171 #define OSCC 0x08 /* Oscillator Configuration register */
172 #define CCSR 0x0c /* Core Clock Status register */
173
174 static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
175 {
176 PXA2xxState *s = (PXA2xxState *) opaque;
177
178 switch (addr) {
179 case CCCR:
180 case CKEN:
181 case OSCC:
182 return s->cm_regs[addr >> 2];
183
184 case CCSR:
185 return s->cm_regs[CCCR >> 2] | (3 << 28);
186
187 default:
188 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
189 break;
190 }
191 return 0;
192 }
193
194 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
195 uint32_t value)
196 {
197 PXA2xxState *s = (PXA2xxState *) opaque;
198
199 switch (addr) {
200 case CCCR:
201 case CKEN:
202 s->cm_regs[addr >> 2] = value;
203 break;
204
205 case OSCC:
206 s->cm_regs[addr >> 2] &= ~0x6c;
207 s->cm_regs[addr >> 2] |= value & 0x6e;
208 if ((value >> 1) & 1) /* OON */
209 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
210 break;
211
212 default:
213 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
214 break;
215 }
216 }
217
218 static CPUReadMemoryFunc * const pxa2xx_cm_readfn[] = {
219 pxa2xx_cm_read,
220 pxa2xx_cm_read,
221 pxa2xx_cm_read,
222 };
223
224 static CPUWriteMemoryFunc * const pxa2xx_cm_writefn[] = {
225 pxa2xx_cm_write,
226 pxa2xx_cm_write,
227 pxa2xx_cm_write,
228 };
229
230 static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
231 {
232 PXA2xxState *s = (PXA2xxState *) opaque;
233 int i;
234
235 for (i = 0; i < 4; i ++)
236 qemu_put_be32s(f, &s->cm_regs[i]);
237 qemu_put_be32s(f, &s->clkcfg);
238 qemu_put_be32s(f, &s->pmnc);
239 }
240
241 static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
242 {
243 PXA2xxState *s = (PXA2xxState *) opaque;
244 int i;
245
246 for (i = 0; i < 4; i ++)
247 qemu_get_be32s(f, &s->cm_regs[i]);
248 qemu_get_be32s(f, &s->clkcfg);
249 qemu_get_be32s(f, &s->pmnc);
250
251 return 0;
252 }
253
254 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
255 {
256 PXA2xxState *s = (PXA2xxState *) opaque;
257
258 switch (reg) {
259 case 6: /* Clock Configuration register */
260 return s->clkcfg;
261
262 case 7: /* Power Mode register */
263 return 0;
264
265 default:
266 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
267 break;
268 }
269 return 0;
270 }
271
272 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
273 uint32_t value)
274 {
275 PXA2xxState *s = (PXA2xxState *) opaque;
276 static const char *pwrmode[8] = {
277 "Normal", "Idle", "Deep-idle", "Standby",
278 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
279 };
280
281 switch (reg) {
282 case 6: /* Clock Configuration register */
283 s->clkcfg = value & 0xf;
284 if (value & 2)
285 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
286 break;
287
288 case 7: /* Power Mode register */
289 if (value & 8)
290 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
291 switch (value & 7) {
292 case 0:
293 /* Do nothing */
294 break;
295
296 case 1:
297 /* Idle */
298 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
299 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
300 break;
301 }
302 /* Fall through. */
303
304 case 2:
305 /* Deep-Idle */
306 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
307 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
308 goto message;
309
310 case 3:
311 s->env->uncached_cpsr =
312 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
313 s->env->cp15.c1_sys = 0;
314 s->env->cp15.c1_coproc = 0;
315 s->env->cp15.c2_base0 = 0;
316 s->env->cp15.c3 = 0;
317 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
318 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
319
320 /*
321 * The scratch-pad register is almost universally used
322 * for storing the return address on suspend. For the
323 * lack of a resuming bootloader, perform a jump
324 * directly to that address.
325 */
326 memset(s->env->regs, 0, 4 * 15);
327 s->env->regs[15] = s->pm_regs[PSPR >> 2];
328
329 #if 0
330 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
331 cpu_physical_memory_write(0, &buffer, 4);
332 buffer = s->pm_regs[PSPR >> 2];
333 cpu_physical_memory_write(8, &buffer, 4);
334 #endif
335
336 /* Suspend */
337 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
338
339 goto message;
340
341 default:
342 message:
343 printf("%s: machine entered %s mode\n", __FUNCTION__,
344 pwrmode[value & 7]);
345 }
346 break;
347
348 default:
349 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
350 break;
351 }
352 }
353
354 /* Performace Monitoring Registers */
355 #define CPPMNC 0 /* Performance Monitor Control register */
356 #define CPCCNT 1 /* Clock Counter register */
357 #define CPINTEN 4 /* Interrupt Enable register */
358 #define CPFLAG 5 /* Overflow Flag register */
359 #define CPEVTSEL 8 /* Event Selection register */
360
361 #define CPPMN0 0 /* Performance Count register 0 */
362 #define CPPMN1 1 /* Performance Count register 1 */
363 #define CPPMN2 2 /* Performance Count register 2 */
364 #define CPPMN3 3 /* Performance Count register 3 */
365
366 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
367 {
368 PXA2xxState *s = (PXA2xxState *) opaque;
369
370 switch (reg) {
371 case CPPMNC:
372 return s->pmnc;
373 case CPCCNT:
374 if (s->pmnc & 1)
375 return qemu_get_clock(vm_clock);
376 else
377 return 0;
378 case CPINTEN:
379 case CPFLAG:
380 case CPEVTSEL:
381 return 0;
382
383 default:
384 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
385 break;
386 }
387 return 0;
388 }
389
390 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
391 uint32_t value)
392 {
393 PXA2xxState *s = (PXA2xxState *) opaque;
394
395 switch (reg) {
396 case CPPMNC:
397 s->pmnc = value;
398 break;
399
400 case CPCCNT:
401 case CPINTEN:
402 case CPFLAG:
403 case CPEVTSEL:
404 break;
405
406 default:
407 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
408 break;
409 }
410 }
411
412 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
413 {
414 switch (crm) {
415 case 0:
416 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
417 case 1:
418 return pxa2xx_perf_read(opaque, op2, reg, crm);
419 case 2:
420 switch (reg) {
421 case CPPMN0:
422 case CPPMN1:
423 case CPPMN2:
424 case CPPMN3:
425 return 0;
426 }
427 /* Fall through */
428 default:
429 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
430 break;
431 }
432 return 0;
433 }
434
435 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
436 uint32_t value)
437 {
438 switch (crm) {
439 case 0:
440 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
441 break;
442 case 1:
443 pxa2xx_perf_write(opaque, op2, reg, crm, value);
444 break;
445 case 2:
446 switch (reg) {
447 case CPPMN0:
448 case CPPMN1:
449 case CPPMN2:
450 case CPPMN3:
451 return;
452 }
453 /* Fall through */
454 default:
455 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
456 break;
457 }
458 }
459
460 #define MDCNFG 0x00 /* SDRAM Configuration register */
461 #define MDREFR 0x04 /* SDRAM Refresh Control register */
462 #define MSC0 0x08 /* Static Memory Control register 0 */
463 #define MSC1 0x0c /* Static Memory Control register 1 */
464 #define MSC2 0x10 /* Static Memory Control register 2 */
465 #define MECR 0x14 /* Expansion Memory Bus Config register */
466 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
467 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
468 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
469 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
470 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
471 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
472 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
473 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
474 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
475 #define ARB_CNTL 0x48 /* Arbiter Control register */
476 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
477 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
478 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
479 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
480 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
481 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
482 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
483
484 static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
485 {
486 PXA2xxState *s = (PXA2xxState *) opaque;
487
488 switch (addr) {
489 case MDCNFG ... SA1110:
490 if ((addr & 3) == 0)
491 return s->mm_regs[addr >> 2];
492
493 default:
494 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
495 break;
496 }
497 return 0;
498 }
499
500 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
501 uint32_t value)
502 {
503 PXA2xxState *s = (PXA2xxState *) opaque;
504
505 switch (addr) {
506 case MDCNFG ... SA1110:
507 if ((addr & 3) == 0) {
508 s->mm_regs[addr >> 2] = value;
509 break;
510 }
511
512 default:
513 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
514 break;
515 }
516 }
517
518 static CPUReadMemoryFunc * const pxa2xx_mm_readfn[] = {
519 pxa2xx_mm_read,
520 pxa2xx_mm_read,
521 pxa2xx_mm_read,
522 };
523
524 static CPUWriteMemoryFunc * const pxa2xx_mm_writefn[] = {
525 pxa2xx_mm_write,
526 pxa2xx_mm_write,
527 pxa2xx_mm_write,
528 };
529
530 static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
531 {
532 PXA2xxState *s = (PXA2xxState *) opaque;
533 int i;
534
535 for (i = 0; i < 0x1a; i ++)
536 qemu_put_be32s(f, &s->mm_regs[i]);
537 }
538
539 static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
540 {
541 PXA2xxState *s = (PXA2xxState *) opaque;
542 int i;
543
544 for (i = 0; i < 0x1a; i ++)
545 qemu_get_be32s(f, &s->mm_regs[i]);
546
547 return 0;
548 }
549
550 /* Synchronous Serial Ports */
551 typedef struct {
552 SysBusDevice busdev;
553 qemu_irq irq;
554 int enable;
555 SSIBus *bus;
556
557 uint32_t sscr[2];
558 uint32_t sspsp;
559 uint32_t ssto;
560 uint32_t ssitr;
561 uint32_t sssr;
562 uint8_t sstsa;
563 uint8_t ssrsa;
564 uint8_t ssacd;
565
566 uint32_t rx_fifo[16];
567 int rx_level;
568 int rx_start;
569 } PXA2xxSSPState;
570
571 #define SSCR0 0x00 /* SSP Control register 0 */
572 #define SSCR1 0x04 /* SSP Control register 1 */
573 #define SSSR 0x08 /* SSP Status register */
574 #define SSITR 0x0c /* SSP Interrupt Test register */
575 #define SSDR 0x10 /* SSP Data register */
576 #define SSTO 0x28 /* SSP Time-Out register */
577 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
578 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
579 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
580 #define SSTSS 0x38 /* SSP Time Slot Status register */
581 #define SSACD 0x3c /* SSP Audio Clock Divider register */
582
583 /* Bitfields for above registers */
584 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
585 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
586 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
587 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
588 #define SSCR0_SSE (1 << 7)
589 #define SSCR0_RIM (1 << 22)
590 #define SSCR0_TIM (1 << 23)
591 #define SSCR0_MOD (1 << 31)
592 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
593 #define SSCR1_RIE (1 << 0)
594 #define SSCR1_TIE (1 << 1)
595 #define SSCR1_LBM (1 << 2)
596 #define SSCR1_MWDS (1 << 5)
597 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
598 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
599 #define SSCR1_EFWR (1 << 14)
600 #define SSCR1_PINTE (1 << 18)
601 #define SSCR1_TINTE (1 << 19)
602 #define SSCR1_RSRE (1 << 20)
603 #define SSCR1_TSRE (1 << 21)
604 #define SSCR1_EBCEI (1 << 29)
605 #define SSITR_INT (7 << 5)
606 #define SSSR_TNF (1 << 2)
607 #define SSSR_RNE (1 << 3)
608 #define SSSR_TFS (1 << 5)
609 #define SSSR_RFS (1 << 6)
610 #define SSSR_ROR (1 << 7)
611 #define SSSR_PINT (1 << 18)
612 #define SSSR_TINT (1 << 19)
613 #define SSSR_EOC (1 << 20)
614 #define SSSR_TUR (1 << 21)
615 #define SSSR_BCE (1 << 23)
616 #define SSSR_RW 0x00bc0080
617
618 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
619 {
620 int level = 0;
621
622 level |= s->ssitr & SSITR_INT;
623 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
624 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
625 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
626 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
627 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
628 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
629 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
630 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
631 qemu_set_irq(s->irq, !!level);
632 }
633
634 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
635 {
636 s->sssr &= ~(0xf << 12); /* Clear RFL */
637 s->sssr &= ~(0xf << 8); /* Clear TFL */
638 s->sssr &= ~SSSR_TNF;
639 if (s->enable) {
640 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
641 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
642 s->sssr |= SSSR_RFS;
643 else
644 s->sssr &= ~SSSR_RFS;
645 if (0 <= SSCR1_TFT(s->sscr[1]))
646 s->sssr |= SSSR_TFS;
647 else
648 s->sssr &= ~SSSR_TFS;
649 if (s->rx_level)
650 s->sssr |= SSSR_RNE;
651 else
652 s->sssr &= ~SSSR_RNE;
653 s->sssr |= SSSR_TNF;
654 }
655
656 pxa2xx_ssp_int_update(s);
657 }
658
659 static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
660 {
661 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
662 uint32_t retval;
663
664 switch (addr) {
665 case SSCR0:
666 return s->sscr[0];
667 case SSCR1:
668 return s->sscr[1];
669 case SSPSP:
670 return s->sspsp;
671 case SSTO:
672 return s->ssto;
673 case SSITR:
674 return s->ssitr;
675 case SSSR:
676 return s->sssr | s->ssitr;
677 case SSDR:
678 if (!s->enable)
679 return 0xffffffff;
680 if (s->rx_level < 1) {
681 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
682 return 0xffffffff;
683 }
684 s->rx_level --;
685 retval = s->rx_fifo[s->rx_start ++];
686 s->rx_start &= 0xf;
687 pxa2xx_ssp_fifo_update(s);
688 return retval;
689 case SSTSA:
690 return s->sstsa;
691 case SSRSA:
692 return s->ssrsa;
693 case SSTSS:
694 return 0;
695 case SSACD:
696 return s->ssacd;
697 default:
698 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
699 break;
700 }
701 return 0;
702 }
703
704 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
705 uint32_t value)
706 {
707 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
708
709 switch (addr) {
710 case SSCR0:
711 s->sscr[0] = value & 0xc7ffffff;
712 s->enable = value & SSCR0_SSE;
713 if (value & SSCR0_MOD)
714 printf("%s: Attempt to use network mode\n", __FUNCTION__);
715 if (s->enable && SSCR0_DSS(value) < 4)
716 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
717 SSCR0_DSS(value));
718 if (!(value & SSCR0_SSE)) {
719 s->sssr = 0;
720 s->ssitr = 0;
721 s->rx_level = 0;
722 }
723 pxa2xx_ssp_fifo_update(s);
724 break;
725
726 case SSCR1:
727 s->sscr[1] = value;
728 if (value & (SSCR1_LBM | SSCR1_EFWR))
729 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
730 pxa2xx_ssp_fifo_update(s);
731 break;
732
733 case SSPSP:
734 s->sspsp = value;
735 break;
736
737 case SSTO:
738 s->ssto = value;
739 break;
740
741 case SSITR:
742 s->ssitr = value & SSITR_INT;
743 pxa2xx_ssp_int_update(s);
744 break;
745
746 case SSSR:
747 s->sssr &= ~(value & SSSR_RW);
748 pxa2xx_ssp_int_update(s);
749 break;
750
751 case SSDR:
752 if (SSCR0_UWIRE(s->sscr[0])) {
753 if (s->sscr[1] & SSCR1_MWDS)
754 value &= 0xffff;
755 else
756 value &= 0xff;
757 } else
758 /* Note how 32bits overflow does no harm here */
759 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
760
761 /* Data goes from here to the Tx FIFO and is shifted out from
762 * there directly to the slave, no need to buffer it.
763 */
764 if (s->enable) {
765 uint32_t readval;
766 readval = ssi_transfer(s->bus, value);
767 if (s->rx_level < 0x10) {
768 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
769 } else {
770 s->sssr |= SSSR_ROR;
771 }
772 }
773 pxa2xx_ssp_fifo_update(s);
774 break;
775
776 case SSTSA:
777 s->sstsa = value;
778 break;
779
780 case SSRSA:
781 s->ssrsa = value;
782 break;
783
784 case SSACD:
785 s->ssacd = value;
786 break;
787
788 default:
789 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
790 break;
791 }
792 }
793
794 static CPUReadMemoryFunc * const pxa2xx_ssp_readfn[] = {
795 pxa2xx_ssp_read,
796 pxa2xx_ssp_read,
797 pxa2xx_ssp_read,
798 };
799
800 static CPUWriteMemoryFunc * const pxa2xx_ssp_writefn[] = {
801 pxa2xx_ssp_write,
802 pxa2xx_ssp_write,
803 pxa2xx_ssp_write,
804 };
805
806 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
807 {
808 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
809 int i;
810
811 qemu_put_be32(f, s->enable);
812
813 qemu_put_be32s(f, &s->sscr[0]);
814 qemu_put_be32s(f, &s->sscr[1]);
815 qemu_put_be32s(f, &s->sspsp);
816 qemu_put_be32s(f, &s->ssto);
817 qemu_put_be32s(f, &s->ssitr);
818 qemu_put_be32s(f, &s->sssr);
819 qemu_put_8s(f, &s->sstsa);
820 qemu_put_8s(f, &s->ssrsa);
821 qemu_put_8s(f, &s->ssacd);
822
823 qemu_put_byte(f, s->rx_level);
824 for (i = 0; i < s->rx_level; i ++)
825 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
826 }
827
828 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
829 {
830 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
831 int i;
832
833 s->enable = qemu_get_be32(f);
834
835 qemu_get_be32s(f, &s->sscr[0]);
836 qemu_get_be32s(f, &s->sscr[1]);
837 qemu_get_be32s(f, &s->sspsp);
838 qemu_get_be32s(f, &s->ssto);
839 qemu_get_be32s(f, &s->ssitr);
840 qemu_get_be32s(f, &s->sssr);
841 qemu_get_8s(f, &s->sstsa);
842 qemu_get_8s(f, &s->ssrsa);
843 qemu_get_8s(f, &s->ssacd);
844
845 s->rx_level = qemu_get_byte(f);
846 s->rx_start = 0;
847 for (i = 0; i < s->rx_level; i ++)
848 s->rx_fifo[i] = qemu_get_byte(f);
849
850 return 0;
851 }
852
853 static int pxa2xx_ssp_init(SysBusDevice *dev)
854 {
855 int iomemtype;
856 PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
857
858 sysbus_init_irq(dev, &s->irq);
859
860 iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,
861 pxa2xx_ssp_writefn, s);
862 sysbus_init_mmio(dev, 0x1000, iomemtype);
863 register_savevm("pxa2xx_ssp", -1, 0,
864 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
865
866 s->bus = ssi_create_bus(&dev->qdev, "ssi");
867 return 0;
868 }
869
870 /* Real-Time Clock */
871 #define RCNR 0x00 /* RTC Counter register */
872 #define RTAR 0x04 /* RTC Alarm register */
873 #define RTSR 0x08 /* RTC Status register */
874 #define RTTR 0x0c /* RTC Timer Trim register */
875 #define RDCR 0x10 /* RTC Day Counter register */
876 #define RYCR 0x14 /* RTC Year Counter register */
877 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
878 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
879 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
880 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
881 #define SWCR 0x28 /* RTC Stopwatch Counter register */
882 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
883 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
884 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
885 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
886
887 static inline void pxa2xx_rtc_int_update(PXA2xxState *s)
888 {
889 qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
890 }
891
892 static void pxa2xx_rtc_hzupdate(PXA2xxState *s)
893 {
894 int64_t rt = qemu_get_clock(rt_clock);
895 s->last_rcnr += ((rt - s->last_hz) << 15) /
896 (1000 * ((s->rttr & 0xffff) + 1));
897 s->last_rdcr += ((rt - s->last_hz) << 15) /
898 (1000 * ((s->rttr & 0xffff) + 1));
899 s->last_hz = rt;
900 }
901
902 static void pxa2xx_rtc_swupdate(PXA2xxState *s)
903 {
904 int64_t rt = qemu_get_clock(rt_clock);
905 if (s->rtsr & (1 << 12))
906 s->last_swcr += (rt - s->last_sw) / 10;
907 s->last_sw = rt;
908 }
909
910 static void pxa2xx_rtc_piupdate(PXA2xxState *s)
911 {
912 int64_t rt = qemu_get_clock(rt_clock);
913 if (s->rtsr & (1 << 15))
914 s->last_swcr += rt - s->last_pi;
915 s->last_pi = rt;
916 }
917
918 static inline void pxa2xx_rtc_alarm_update(PXA2xxState *s,
919 uint32_t rtsr)
920 {
921 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
922 qemu_mod_timer(s->rtc_hz, s->last_hz +
923 (((s->rtar - s->last_rcnr) * 1000 *
924 ((s->rttr & 0xffff) + 1)) >> 15));
925 else
926 qemu_del_timer(s->rtc_hz);
927
928 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
929 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
930 (((s->rdar1 - s->last_rdcr) * 1000 *
931 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
932 else
933 qemu_del_timer(s->rtc_rdal1);
934
935 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
936 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
937 (((s->rdar2 - s->last_rdcr) * 1000 *
938 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
939 else
940 qemu_del_timer(s->rtc_rdal2);
941
942 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
943 qemu_mod_timer(s->rtc_swal1, s->last_sw +
944 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
945 else
946 qemu_del_timer(s->rtc_swal1);
947
948 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
949 qemu_mod_timer(s->rtc_swal2, s->last_sw +
950 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
951 else
952 qemu_del_timer(s->rtc_swal2);
953
954 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
955 qemu_mod_timer(s->rtc_pi, s->last_pi +
956 (s->piar & 0xffff) - s->last_rtcpicr);
957 else
958 qemu_del_timer(s->rtc_pi);
959 }
960
961 static inline void pxa2xx_rtc_hz_tick(void *opaque)
962 {
963 PXA2xxState *s = (PXA2xxState *) opaque;
964 s->rtsr |= (1 << 0);
965 pxa2xx_rtc_alarm_update(s, s->rtsr);
966 pxa2xx_rtc_int_update(s);
967 }
968
969 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
970 {
971 PXA2xxState *s = (PXA2xxState *) opaque;
972 s->rtsr |= (1 << 4);
973 pxa2xx_rtc_alarm_update(s, s->rtsr);
974 pxa2xx_rtc_int_update(s);
975 }
976
977 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
978 {
979 PXA2xxState *s = (PXA2xxState *) opaque;
980 s->rtsr |= (1 << 6);
981 pxa2xx_rtc_alarm_update(s, s->rtsr);
982 pxa2xx_rtc_int_update(s);
983 }
984
985 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
986 {
987 PXA2xxState *s = (PXA2xxState *) opaque;
988 s->rtsr |= (1 << 8);
989 pxa2xx_rtc_alarm_update(s, s->rtsr);
990 pxa2xx_rtc_int_update(s);
991 }
992
993 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
994 {
995 PXA2xxState *s = (PXA2xxState *) opaque;
996 s->rtsr |= (1 << 10);
997 pxa2xx_rtc_alarm_update(s, s->rtsr);
998 pxa2xx_rtc_int_update(s);
999 }
1000
1001 static inline void pxa2xx_rtc_pi_tick(void *opaque)
1002 {
1003 PXA2xxState *s = (PXA2xxState *) opaque;
1004 s->rtsr |= (1 << 13);
1005 pxa2xx_rtc_piupdate(s);
1006 s->last_rtcpicr = 0;
1007 pxa2xx_rtc_alarm_update(s, s->rtsr);
1008 pxa2xx_rtc_int_update(s);
1009 }
1010
1011 static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1012 {
1013 PXA2xxState *s = (PXA2xxState *) opaque;
1014
1015 switch (addr) {
1016 case RTTR:
1017 return s->rttr;
1018 case RTSR:
1019 return s->rtsr;
1020 case RTAR:
1021 return s->rtar;
1022 case RDAR1:
1023 return s->rdar1;
1024 case RDAR2:
1025 return s->rdar2;
1026 case RYAR1:
1027 return s->ryar1;
1028 case RYAR2:
1029 return s->ryar2;
1030 case SWAR1:
1031 return s->swar1;
1032 case SWAR2:
1033 return s->swar2;
1034 case PIAR:
1035 return s->piar;
1036 case RCNR:
1037 return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1038 (1000 * ((s->rttr & 0xffff) + 1));
1039 case RDCR:
1040 return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1041 (1000 * ((s->rttr & 0xffff) + 1));
1042 case RYCR:
1043 return s->last_rycr;
1044 case SWCR:
1045 if (s->rtsr & (1 << 12))
1046 return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;
1047 else
1048 return s->last_swcr;
1049 default:
1050 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1051 break;
1052 }
1053 return 0;
1054 }
1055
1056 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1057 uint32_t value)
1058 {
1059 PXA2xxState *s = (PXA2xxState *) opaque;
1060
1061 switch (addr) {
1062 case RTTR:
1063 if (!(s->rttr & (1 << 31))) {
1064 pxa2xx_rtc_hzupdate(s);
1065 s->rttr = value;
1066 pxa2xx_rtc_alarm_update(s, s->rtsr);
1067 }
1068 break;
1069
1070 case RTSR:
1071 if ((s->rtsr ^ value) & (1 << 15))
1072 pxa2xx_rtc_piupdate(s);
1073
1074 if ((s->rtsr ^ value) & (1 << 12))
1075 pxa2xx_rtc_swupdate(s);
1076
1077 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1078 pxa2xx_rtc_alarm_update(s, value);
1079
1080 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1081 pxa2xx_rtc_int_update(s);
1082 break;
1083
1084 case RTAR:
1085 s->rtar = value;
1086 pxa2xx_rtc_alarm_update(s, s->rtsr);
1087 break;
1088
1089 case RDAR1:
1090 s->rdar1 = value;
1091 pxa2xx_rtc_alarm_update(s, s->rtsr);
1092 break;
1093
1094 case RDAR2:
1095 s->rdar2 = value;
1096 pxa2xx_rtc_alarm_update(s, s->rtsr);
1097 break;
1098
1099 case RYAR1:
1100 s->ryar1 = value;
1101 pxa2xx_rtc_alarm_update(s, s->rtsr);
1102 break;
1103
1104 case RYAR2:
1105 s->ryar2 = value;
1106 pxa2xx_rtc_alarm_update(s, s->rtsr);
1107 break;
1108
1109 case SWAR1:
1110 pxa2xx_rtc_swupdate(s);
1111 s->swar1 = value;
1112 s->last_swcr = 0;
1113 pxa2xx_rtc_alarm_update(s, s->rtsr);
1114 break;
1115
1116 case SWAR2:
1117 s->swar2 = value;
1118 pxa2xx_rtc_alarm_update(s, s->rtsr);
1119 break;
1120
1121 case PIAR:
1122 s->piar = value;
1123 pxa2xx_rtc_alarm_update(s, s->rtsr);
1124 break;
1125
1126 case RCNR:
1127 pxa2xx_rtc_hzupdate(s);
1128 s->last_rcnr = value;
1129 pxa2xx_rtc_alarm_update(s, s->rtsr);
1130 break;
1131
1132 case RDCR:
1133 pxa2xx_rtc_hzupdate(s);
1134 s->last_rdcr = value;
1135 pxa2xx_rtc_alarm_update(s, s->rtsr);
1136 break;
1137
1138 case RYCR:
1139 s->last_rycr = value;
1140 break;
1141
1142 case SWCR:
1143 pxa2xx_rtc_swupdate(s);
1144 s->last_swcr = value;
1145 pxa2xx_rtc_alarm_update(s, s->rtsr);
1146 break;
1147
1148 case RTCPICR:
1149 pxa2xx_rtc_piupdate(s);
1150 s->last_rtcpicr = value & 0xffff;
1151 pxa2xx_rtc_alarm_update(s, s->rtsr);
1152 break;
1153
1154 default:
1155 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1156 }
1157 }
1158
1159 static CPUReadMemoryFunc * const pxa2xx_rtc_readfn[] = {
1160 pxa2xx_rtc_read,
1161 pxa2xx_rtc_read,
1162 pxa2xx_rtc_read,
1163 };
1164
1165 static CPUWriteMemoryFunc * const pxa2xx_rtc_writefn[] = {
1166 pxa2xx_rtc_write,
1167 pxa2xx_rtc_write,
1168 pxa2xx_rtc_write,
1169 };
1170
1171 static void pxa2xx_rtc_init(PXA2xxState *s)
1172 {
1173 struct tm tm;
1174 int wom;
1175
1176 s->rttr = 0x7fff;
1177 s->rtsr = 0;
1178
1179 qemu_get_timedate(&tm, 0);
1180 wom = ((tm.tm_mday - 1) / 7) + 1;
1181
1182 s->last_rcnr = (uint32_t) mktimegm(&tm);
1183 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1184 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1185 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1186 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1187 s->last_swcr = (tm.tm_hour << 19) |
1188 (tm.tm_min << 13) | (tm.tm_sec << 7);
1189 s->last_rtcpicr = 0;
1190 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
1191
1192 s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s);
1193 s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1194 s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1195 s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
1196 s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
1197 s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
1198 }
1199
1200 static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
1201 {
1202 PXA2xxState *s = (PXA2xxState *) opaque;
1203
1204 pxa2xx_rtc_hzupdate(s);
1205 pxa2xx_rtc_piupdate(s);
1206 pxa2xx_rtc_swupdate(s);
1207
1208 qemu_put_be32s(f, &s->rttr);
1209 qemu_put_be32s(f, &s->rtsr);
1210 qemu_put_be32s(f, &s->rtar);
1211 qemu_put_be32s(f, &s->rdar1);
1212 qemu_put_be32s(f, &s->rdar2);
1213 qemu_put_be32s(f, &s->ryar1);
1214 qemu_put_be32s(f, &s->ryar2);
1215 qemu_put_be32s(f, &s->swar1);
1216 qemu_put_be32s(f, &s->swar2);
1217 qemu_put_be32s(f, &s->piar);
1218 qemu_put_be32s(f, &s->last_rcnr);
1219 qemu_put_be32s(f, &s->last_rdcr);
1220 qemu_put_be32s(f, &s->last_rycr);
1221 qemu_put_be32s(f, &s->last_swcr);
1222 qemu_put_be32s(f, &s->last_rtcpicr);
1223 qemu_put_sbe64s(f, &s->last_hz);
1224 qemu_put_sbe64s(f, &s->last_sw);
1225 qemu_put_sbe64s(f, &s->last_pi);
1226 }
1227
1228 static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
1229 {
1230 PXA2xxState *s = (PXA2xxState *) opaque;
1231
1232 qemu_get_be32s(f, &s->rttr);
1233 qemu_get_be32s(f, &s->rtsr);
1234 qemu_get_be32s(f, &s->rtar);
1235 qemu_get_be32s(f, &s->rdar1);
1236 qemu_get_be32s(f, &s->rdar2);
1237 qemu_get_be32s(f, &s->ryar1);
1238 qemu_get_be32s(f, &s->ryar2);
1239 qemu_get_be32s(f, &s->swar1);
1240 qemu_get_be32s(f, &s->swar2);
1241 qemu_get_be32s(f, &s->piar);
1242 qemu_get_be32s(f, &s->last_rcnr);
1243 qemu_get_be32s(f, &s->last_rdcr);
1244 qemu_get_be32s(f, &s->last_rycr);
1245 qemu_get_be32s(f, &s->last_swcr);
1246 qemu_get_be32s(f, &s->last_rtcpicr);
1247 qemu_get_sbe64s(f, &s->last_hz);
1248 qemu_get_sbe64s(f, &s->last_sw);
1249 qemu_get_sbe64s(f, &s->last_pi);
1250
1251 pxa2xx_rtc_alarm_update(s, s->rtsr);
1252
1253 return 0;
1254 }
1255
1256 /* I2C Interface */
1257 typedef struct {
1258 i2c_slave i2c;
1259 PXA2xxI2CState *host;
1260 } PXA2xxI2CSlaveState;
1261
1262 struct PXA2xxI2CState {
1263 PXA2xxI2CSlaveState *slave;
1264 i2c_bus *bus;
1265 qemu_irq irq;
1266 target_phys_addr_t offset;
1267
1268 uint16_t control;
1269 uint16_t status;
1270 uint8_t ibmr;
1271 uint8_t data;
1272 };
1273
1274 #define IBMR 0x80 /* I2C Bus Monitor register */
1275 #define IDBR 0x88 /* I2C Data Buffer register */
1276 #define ICR 0x90 /* I2C Control register */
1277 #define ISR 0x98 /* I2C Status register */
1278 #define ISAR 0xa0 /* I2C Slave Address register */
1279
1280 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1281 {
1282 uint16_t level = 0;
1283 level |= s->status & s->control & (1 << 10); /* BED */
1284 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1285 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1286 level |= s->status & (1 << 9); /* SAD */
1287 qemu_set_irq(s->irq, !!level);
1288 }
1289
1290 /* These are only stubs now. */
1291 static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1292 {
1293 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1294 PXA2xxI2CState *s = slave->host;
1295
1296 switch (event) {
1297 case I2C_START_SEND:
1298 s->status |= (1 << 9); /* set SAD */
1299 s->status &= ~(1 << 0); /* clear RWM */
1300 break;
1301 case I2C_START_RECV:
1302 s->status |= (1 << 9); /* set SAD */
1303 s->status |= 1 << 0; /* set RWM */
1304 break;
1305 case I2C_FINISH:
1306 s->status |= (1 << 4); /* set SSD */
1307 break;
1308 case I2C_NACK:
1309 s->status |= 1 << 1; /* set ACKNAK */
1310 break;
1311 }
1312 pxa2xx_i2c_update(s);
1313 }
1314
1315 static int pxa2xx_i2c_rx(i2c_slave *i2c)
1316 {
1317 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1318 PXA2xxI2CState *s = slave->host;
1319 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1320 return 0;
1321
1322 if (s->status & (1 << 0)) { /* RWM */
1323 s->status |= 1 << 6; /* set ITE */
1324 }
1325 pxa2xx_i2c_update(s);
1326
1327 return s->data;
1328 }
1329
1330 static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1331 {
1332 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1333 PXA2xxI2CState *s = slave->host;
1334 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1335 return 1;
1336
1337 if (!(s->status & (1 << 0))) { /* RWM */
1338 s->status |= 1 << 7; /* set IRF */
1339 s->data = data;
1340 }
1341 pxa2xx_i2c_update(s);
1342
1343 return 1;
1344 }
1345
1346 static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1347 {
1348 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1349
1350 addr -= s->offset;
1351 switch (addr) {
1352 case ICR:
1353 return s->control;
1354 case ISR:
1355 return s->status | (i2c_bus_busy(s->bus) << 2);
1356 case ISAR:
1357 return s->slave->i2c.address;
1358 case IDBR:
1359 return s->data;
1360 case IBMR:
1361 if (s->status & (1 << 2))
1362 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1363 else
1364 s->ibmr = 0;
1365 return s->ibmr;
1366 default:
1367 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1368 break;
1369 }
1370 return 0;
1371 }
1372
1373 static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1374 uint32_t value)
1375 {
1376 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1377 int ack;
1378
1379 addr -= s->offset;
1380 switch (addr) {
1381 case ICR:
1382 s->control = value & 0xfff7;
1383 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1384 /* TODO: slave mode */
1385 if (value & (1 << 0)) { /* START condition */
1386 if (s->data & 1)
1387 s->status |= 1 << 0; /* set RWM */
1388 else
1389 s->status &= ~(1 << 0); /* clear RWM */
1390 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1391 } else {
1392 if (s->status & (1 << 0)) { /* RWM */
1393 s->data = i2c_recv(s->bus);
1394 if (value & (1 << 2)) /* ACKNAK */
1395 i2c_nack(s->bus);
1396 ack = 1;
1397 } else
1398 ack = !i2c_send(s->bus, s->data);
1399 }
1400
1401 if (value & (1 << 1)) /* STOP condition */
1402 i2c_end_transfer(s->bus);
1403
1404 if (ack) {
1405 if (value & (1 << 0)) /* START condition */
1406 s->status |= 1 << 6; /* set ITE */
1407 else
1408 if (s->status & (1 << 0)) /* RWM */
1409 s->status |= 1 << 7; /* set IRF */
1410 else
1411 s->status |= 1 << 6; /* set ITE */
1412 s->status &= ~(1 << 1); /* clear ACKNAK */
1413 } else {
1414 s->status |= 1 << 6; /* set ITE */
1415 s->status |= 1 << 10; /* set BED */
1416 s->status |= 1 << 1; /* set ACKNAK */
1417 }
1418 }
1419 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1420 if (value & (1 << 4)) /* MA */
1421 i2c_end_transfer(s->bus);
1422 pxa2xx_i2c_update(s);
1423 break;
1424
1425 case ISR:
1426 s->status &= ~(value & 0x07f0);
1427 pxa2xx_i2c_update(s);
1428 break;
1429
1430 case ISAR:
1431 i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1432 break;
1433
1434 case IDBR:
1435 s->data = value & 0xff;
1436 break;
1437
1438 default:
1439 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1440 }
1441 }
1442
1443 static CPUReadMemoryFunc * const pxa2xx_i2c_readfn[] = {
1444 pxa2xx_i2c_read,
1445 pxa2xx_i2c_read,
1446 pxa2xx_i2c_read,
1447 };
1448
1449 static CPUWriteMemoryFunc * const pxa2xx_i2c_writefn[] = {
1450 pxa2xx_i2c_write,
1451 pxa2xx_i2c_write,
1452 pxa2xx_i2c_write,
1453 };
1454
1455 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1456 .name = "pxa2xx_i2c_slave",
1457 .version_id = 1,
1458 .minimum_version_id = 1,
1459 .minimum_version_id_old = 1,
1460 .fields = (VMStateField []) {
1461 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
1462 VMSTATE_END_OF_LIST()
1463 }
1464 };
1465
1466 static const VMStateDescription vmstate_pxa2xx_i2c = {
1467 .name = "pxa2xx_i2c",
1468 .version_id = 1,
1469 .minimum_version_id = 1,
1470 .minimum_version_id_old = 1,
1471 .fields = (VMStateField []) {
1472 VMSTATE_UINT16(control, PXA2xxI2CState),
1473 VMSTATE_UINT16(status, PXA2xxI2CState),
1474 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1475 VMSTATE_UINT8(data, PXA2xxI2CState),
1476 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1477 vmstate_pxa2xx_i2c, PXA2xxI2CSlaveState *),
1478 VMSTATE_END_OF_LIST()
1479 }
1480 };
1481
1482 static int pxa2xx_i2c_slave_init(i2c_slave *i2c)
1483 {
1484 /* Nothing to do. */
1485 return 0;
1486 }
1487
1488 static I2CSlaveInfo pxa2xx_i2c_slave_info = {
1489 .qdev.name = "pxa2xx-i2c-slave",
1490 .qdev.size = sizeof(PXA2xxI2CSlaveState),
1491 .init = pxa2xx_i2c_slave_init,
1492 .event = pxa2xx_i2c_event,
1493 .recv = pxa2xx_i2c_rx,
1494 .send = pxa2xx_i2c_tx
1495 };
1496
1497 PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
1498 qemu_irq irq, uint32_t region_size)
1499 {
1500 int iomemtype;
1501 DeviceState *dev;
1502 PXA2xxI2CState *s = qemu_mallocz(sizeof(PXA2xxI2CState));
1503
1504 /* FIXME: Should the slave device really be on a separate bus? */
1505 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
1506 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));
1507 s->slave->host = s;
1508
1509 s->irq = irq;
1510 s->bus = i2c_init_bus(NULL, "i2c");
1511 s->offset = base - (base & (~region_size) & TARGET_PAGE_MASK);
1512
1513 iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn,
1514 pxa2xx_i2c_writefn, s);
1515 cpu_register_physical_memory(base & ~region_size,
1516 region_size + 1, iomemtype);
1517
1518 vmstate_register(base, &vmstate_pxa2xx_i2c, s);
1519
1520 return s;
1521 }
1522
1523 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1524 {
1525 return s->bus;
1526 }
1527
1528 /* PXA Inter-IC Sound Controller */
1529 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1530 {
1531 i2s->rx_len = 0;
1532 i2s->tx_len = 0;
1533 i2s->fifo_len = 0;
1534 i2s->clk = 0x1a;
1535 i2s->control[0] = 0x00;
1536 i2s->control[1] = 0x00;
1537 i2s->status = 0x00;
1538 i2s->mask = 0x00;
1539 }
1540
1541 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1542 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1543 #define SACR_DREC(val) (val & (1 << 3))
1544 #define SACR_DPRL(val) (val & (1 << 4))
1545
1546 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1547 {
1548 int rfs, tfs;
1549 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1550 !SACR_DREC(i2s->control[1]);
1551 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1552 i2s->enable && !SACR_DPRL(i2s->control[1]);
1553
1554 pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
1555 pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
1556
1557 i2s->status &= 0xe0;
1558 if (i2s->fifo_len < 16 || !i2s->enable)
1559 i2s->status |= 1 << 0; /* TNF */
1560 if (i2s->rx_len)
1561 i2s->status |= 1 << 1; /* RNE */
1562 if (i2s->enable)
1563 i2s->status |= 1 << 2; /* BSY */
1564 if (tfs)
1565 i2s->status |= 1 << 3; /* TFS */
1566 if (rfs)
1567 i2s->status |= 1 << 4; /* RFS */
1568 if (!(i2s->tx_len && i2s->enable))
1569 i2s->status |= i2s->fifo_len << 8; /* TFL */
1570 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1571
1572 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1573 }
1574
1575 #define SACR0 0x00 /* Serial Audio Global Control register */
1576 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1577 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1578 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1579 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1580 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1581 #define SADR 0x80 /* Serial Audio Data register */
1582
1583 static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1584 {
1585 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1586
1587 switch (addr) {
1588 case SACR0:
1589 return s->control[0];
1590 case SACR1:
1591 return s->control[1];
1592 case SASR0:
1593 return s->status;
1594 case SAIMR:
1595 return s->mask;
1596 case SAICR:
1597 return 0;
1598 case SADIV:
1599 return s->clk;
1600 case SADR:
1601 if (s->rx_len > 0) {
1602 s->rx_len --;
1603 pxa2xx_i2s_update(s);
1604 return s->codec_in(s->opaque);
1605 }
1606 return 0;
1607 default:
1608 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1609 break;
1610 }
1611 return 0;
1612 }
1613
1614 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1615 uint32_t value)
1616 {
1617 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1618 uint32_t *sample;
1619
1620 switch (addr) {
1621 case SACR0:
1622 if (value & (1 << 3)) /* RST */
1623 pxa2xx_i2s_reset(s);
1624 s->control[0] = value & 0xff3d;
1625 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1626 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1627 s->codec_out(s->opaque, *sample);
1628 s->status &= ~(1 << 7); /* I2SOFF */
1629 }
1630 if (value & (1 << 4)) /* EFWR */
1631 printf("%s: Attempt to use special function\n", __FUNCTION__);
1632 s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/
1633 pxa2xx_i2s_update(s);
1634 break;
1635 case SACR1:
1636 s->control[1] = value & 0x0039;
1637 if (value & (1 << 5)) /* ENLBF */
1638 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1639 if (value & (1 << 4)) /* DPRL */
1640 s->fifo_len = 0;
1641 pxa2xx_i2s_update(s);
1642 break;
1643 case SAIMR:
1644 s->mask = value & 0x0078;
1645 pxa2xx_i2s_update(s);
1646 break;
1647 case SAICR:
1648 s->status &= ~(value & (3 << 5));
1649 pxa2xx_i2s_update(s);
1650 break;
1651 case SADIV:
1652 s->clk = value & 0x007f;
1653 break;
1654 case SADR:
1655 if (s->tx_len && s->enable) {
1656 s->tx_len --;
1657 pxa2xx_i2s_update(s);
1658 s->codec_out(s->opaque, value);
1659 } else if (s->fifo_len < 16) {
1660 s->fifo[s->fifo_len ++] = value;
1661 pxa2xx_i2s_update(s);
1662 }
1663 break;
1664 default:
1665 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1666 }
1667 }
1668
1669 static CPUReadMemoryFunc * const pxa2xx_i2s_readfn[] = {
1670 pxa2xx_i2s_read,
1671 pxa2xx_i2s_read,
1672 pxa2xx_i2s_read,
1673 };
1674
1675 static CPUWriteMemoryFunc * const pxa2xx_i2s_writefn[] = {
1676 pxa2xx_i2s_write,
1677 pxa2xx_i2s_write,
1678 pxa2xx_i2s_write,
1679 };
1680
1681 static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
1682 {
1683 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1684
1685 qemu_put_be32s(f, &s->control[0]);
1686 qemu_put_be32s(f, &s->control[1]);
1687 qemu_put_be32s(f, &s->status);
1688 qemu_put_be32s(f, &s->mask);
1689 qemu_put_be32s(f, &s->clk);
1690
1691 qemu_put_be32(f, s->enable);
1692 qemu_put_be32(f, s->rx_len);
1693 qemu_put_be32(f, s->tx_len);
1694 qemu_put_be32(f, s->fifo_len);
1695 }
1696
1697 static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
1698 {
1699 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1700
1701 qemu_get_be32s(f, &s->control[0]);
1702 qemu_get_be32s(f, &s->control[1]);
1703 qemu_get_be32s(f, &s->status);
1704 qemu_get_be32s(f, &s->mask);
1705 qemu_get_be32s(f, &s->clk);
1706
1707 s->enable = qemu_get_be32(f);
1708 s->rx_len = qemu_get_be32(f);
1709 s->tx_len = qemu_get_be32(f);
1710 s->fifo_len = qemu_get_be32(f);
1711
1712 return 0;
1713 }
1714
1715 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1716 {
1717 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1718 uint32_t *sample;
1719
1720 /* Signal FIFO errors */
1721 if (s->enable && s->tx_len)
1722 s->status |= 1 << 5; /* TUR */
1723 if (s->enable && s->rx_len)
1724 s->status |= 1 << 6; /* ROR */
1725
1726 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1727 * handle the cases where it makes a difference. */
1728 s->tx_len = tx - s->fifo_len;
1729 s->rx_len = rx;
1730 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1731 if (s->enable)
1732 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1733 s->codec_out(s->opaque, *sample);
1734 pxa2xx_i2s_update(s);
1735 }
1736
1737 static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
1738 qemu_irq irq, PXA2xxDMAState *dma)
1739 {
1740 int iomemtype;
1741 PXA2xxI2SState *s = (PXA2xxI2SState *)
1742 qemu_mallocz(sizeof(PXA2xxI2SState));
1743
1744 s->irq = irq;
1745 s->dma = dma;
1746 s->data_req = pxa2xx_i2s_data_req;
1747
1748 pxa2xx_i2s_reset(s);
1749
1750 iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn,
1751 pxa2xx_i2s_writefn, s);
1752 cpu_register_physical_memory(base, 0x100000, iomemtype);
1753
1754 register_savevm("pxa2xx_i2s", base, 0,
1755 pxa2xx_i2s_save, pxa2xx_i2s_load, s);
1756
1757 return s;
1758 }
1759
1760 /* PXA Fast Infra-red Communications Port */
1761 struct PXA2xxFIrState {
1762 qemu_irq irq;
1763 PXA2xxDMAState *dma;
1764 int enable;
1765 CharDriverState *chr;
1766
1767 uint8_t control[3];
1768 uint8_t status[2];
1769
1770 int rx_len;
1771 int rx_start;
1772 uint8_t rx_fifo[64];
1773 };
1774
1775 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1776 {
1777 s->control[0] = 0x00;
1778 s->control[1] = 0x00;
1779 s->control[2] = 0x00;
1780 s->status[0] = 0x00;
1781 s->status[1] = 0x00;
1782 s->enable = 0;
1783 }
1784
1785 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1786 {
1787 static const int tresh[4] = { 8, 16, 32, 0 };
1788 int intr = 0;
1789 if ((s->control[0] & (1 << 4)) && /* RXE */
1790 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1791 s->status[0] |= 1 << 4; /* RFS */
1792 else
1793 s->status[0] &= ~(1 << 4); /* RFS */
1794 if (s->control[0] & (1 << 3)) /* TXE */
1795 s->status[0] |= 1 << 3; /* TFS */
1796 else
1797 s->status[0] &= ~(1 << 3); /* TFS */
1798 if (s->rx_len)
1799 s->status[1] |= 1 << 2; /* RNE */
1800 else
1801 s->status[1] &= ~(1 << 2); /* RNE */
1802 if (s->control[0] & (1 << 4)) /* RXE */
1803 s->status[1] |= 1 << 0; /* RSY */
1804 else
1805 s->status[1] &= ~(1 << 0); /* RSY */
1806
1807 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1808 (s->status[0] & (1 << 4)); /* RFS */
1809 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1810 (s->status[0] & (1 << 3)); /* TFS */
1811 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1812 (s->status[0] & (1 << 6)); /* EOC */
1813 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1814 (s->status[0] & (1 << 1)); /* TUR */
1815 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1816
1817 pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
1818 pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
1819
1820 qemu_set_irq(s->irq, intr && s->enable);
1821 }
1822
1823 #define ICCR0 0x00 /* FICP Control register 0 */
1824 #define ICCR1 0x04 /* FICP Control register 1 */
1825 #define ICCR2 0x08 /* FICP Control register 2 */
1826 #define ICDR 0x0c /* FICP Data register */
1827 #define ICSR0 0x14 /* FICP Status register 0 */
1828 #define ICSR1 0x18 /* FICP Status register 1 */
1829 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1830
1831 static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1832 {
1833 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1834 uint8_t ret;
1835
1836 switch (addr) {
1837 case ICCR0:
1838 return s->control[0];
1839 case ICCR1:
1840 return s->control[1];
1841 case ICCR2:
1842 return s->control[2];
1843 case ICDR:
1844 s->status[0] &= ~0x01;
1845 s->status[1] &= ~0x72;
1846 if (s->rx_len) {
1847 s->rx_len --;
1848 ret = s->rx_fifo[s->rx_start ++];
1849 s->rx_start &= 63;
1850 pxa2xx_fir_update(s);
1851 return ret;
1852 }
1853 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1854 break;
1855 case ICSR0:
1856 return s->status[0];
1857 case ICSR1:
1858 return s->status[1] | (1 << 3); /* TNF */
1859 case ICFOR:
1860 return s->rx_len;
1861 default:
1862 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1863 break;
1864 }
1865 return 0;
1866 }
1867
1868 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1869 uint32_t value)
1870 {
1871 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1872 uint8_t ch;
1873
1874 switch (addr) {
1875 case ICCR0:
1876 s->control[0] = value;
1877 if (!(value & (1 << 4))) /* RXE */
1878 s->rx_len = s->rx_start = 0;
1879 if (!(value & (1 << 3))) /* TXE */
1880 /* Nop */;
1881 s->enable = value & 1; /* ITR */
1882 if (!s->enable)
1883 s->status[0] = 0;
1884 pxa2xx_fir_update(s);
1885 break;
1886 case ICCR1:
1887 s->control[1] = value;
1888 break;
1889 case ICCR2:
1890 s->control[2] = value & 0x3f;
1891 pxa2xx_fir_update(s);
1892 break;
1893 case ICDR:
1894 if (s->control[2] & (1 << 2)) /* TXP */
1895 ch = value;
1896 else
1897 ch = ~value;
1898 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1899 qemu_chr_write(s->chr, &ch, 1);
1900 break;
1901 case ICSR0:
1902 s->status[0] &= ~(value & 0x66);
1903 pxa2xx_fir_update(s);
1904 break;
1905 case ICFOR:
1906 break;
1907 default:
1908 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1909 }
1910 }
1911
1912 static CPUReadMemoryFunc * const pxa2xx_fir_readfn[] = {
1913 pxa2xx_fir_read,
1914 pxa2xx_fir_read,
1915 pxa2xx_fir_read,
1916 };
1917
1918 static CPUWriteMemoryFunc * const pxa2xx_fir_writefn[] = {
1919 pxa2xx_fir_write,
1920 pxa2xx_fir_write,
1921 pxa2xx_fir_write,
1922 };
1923
1924 static int pxa2xx_fir_is_empty(void *opaque)
1925 {
1926 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1927 return (s->rx_len < 64);
1928 }
1929
1930 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1931 {
1932 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1933 if (!(s->control[0] & (1 << 4))) /* RXE */
1934 return;
1935
1936 while (size --) {
1937 s->status[1] |= 1 << 4; /* EOF */
1938 if (s->rx_len >= 64) {
1939 s->status[1] |= 1 << 6; /* ROR */
1940 break;
1941 }
1942
1943 if (s->control[2] & (1 << 3)) /* RXP */
1944 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1945 else
1946 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1947 }
1948
1949 pxa2xx_fir_update(s);
1950 }
1951
1952 static void pxa2xx_fir_event(void *opaque, int event)
1953 {
1954 }
1955
1956 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1957 {
1958 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1959 int i;
1960
1961 qemu_put_be32(f, s->enable);
1962
1963 qemu_put_8s(f, &s->control[0]);
1964 qemu_put_8s(f, &s->control[1]);
1965 qemu_put_8s(f, &s->control[2]);
1966 qemu_put_8s(f, &s->status[0]);
1967 qemu_put_8s(f, &s->status[1]);
1968
1969 qemu_put_byte(f, s->rx_len);
1970 for (i = 0; i < s->rx_len; i ++)
1971 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1972 }
1973
1974 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1975 {
1976 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1977 int i;
1978
1979 s->enable = qemu_get_be32(f);
1980
1981 qemu_get_8s(f, &s->control[0]);
1982 qemu_get_8s(f, &s->control[1]);
1983 qemu_get_8s(f, &s->control[2]);
1984 qemu_get_8s(f, &s->status[0]);
1985 qemu_get_8s(f, &s->status[1]);
1986
1987 s->rx_len = qemu_get_byte(f);
1988 s->rx_start = 0;
1989 for (i = 0; i < s->rx_len; i ++)
1990 s->rx_fifo[i] = qemu_get_byte(f);
1991
1992 return 0;
1993 }
1994
1995 static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
1996 qemu_irq irq, PXA2xxDMAState *dma,
1997 CharDriverState *chr)
1998 {
1999 int iomemtype;
2000 PXA2xxFIrState *s = (PXA2xxFIrState *)
2001 qemu_mallocz(sizeof(PXA2xxFIrState));
2002
2003 s->irq = irq;
2004 s->dma = dma;
2005 s->chr = chr;
2006
2007 pxa2xx_fir_reset(s);
2008
2009 iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn,
2010 pxa2xx_fir_writefn, s);
2011 cpu_register_physical_memory(base, 0x1000, iomemtype);
2012
2013 if (chr)
2014 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2015 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2016
2017 register_savevm("pxa2xx_fir", 0, 0, pxa2xx_fir_save, pxa2xx_fir_load, s);
2018
2019 return s;
2020 }
2021
2022 static void pxa2xx_reset(void *opaque, int line, int level)
2023 {
2024 PXA2xxState *s = (PXA2xxState *) opaque;
2025
2026 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2027 cpu_reset(s->env);
2028 /* TODO: reset peripherals */
2029 }
2030 }
2031
2032 /* Initialise a PXA270 integrated chip (ARM based core). */
2033 PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
2034 {
2035 PXA2xxState *s;
2036 int iomemtype, i;
2037 DriveInfo *dinfo;
2038 s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2039
2040 if (revision && strncmp(revision, "pxa27", 5)) {
2041 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2042 exit(1);
2043 }
2044 if (!revision)
2045 revision = "pxa270";
2046
2047 s->env = cpu_init(revision);
2048 if (!s->env) {
2049 fprintf(stderr, "Unable to find CPU definition\n");
2050 exit(1);
2051 }
2052 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2053
2054 /* SDRAM & Internal Memory Storage */
2055 cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2056 sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2057 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2058 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM);
2059
2060 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2061
2062 s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2063
2064 pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
2065 s->pic[PXA27X_PIC_OST_4_11]);
2066
2067 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2068
2069 dinfo = drive_get(IF_SD, 0, 0);
2070 if (!dinfo) {
2071 fprintf(stderr, "qemu: missing SecureDigital device\n");
2072 exit(1);
2073 }
2074 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2075 s->pic[PXA2XX_PIC_MMC], s->dma);
2076
2077 for (i = 0; pxa270_serial[i].io_base; i ++)
2078 if (serial_hds[i])
2079 #ifdef TARGET_WORDS_BIGENDIAN
2080 serial_mm_init(pxa270_serial[i].io_base, 2,
2081 s->pic[pxa270_serial[i].irqn], 14857000/16,
2082 serial_hds[i], 1, 1);
2083 #else
2084 serial_mm_init(pxa270_serial[i].io_base, 2,
2085 s->pic[pxa270_serial[i].irqn], 14857000/16,
2086 serial_hds[i], 1, 0);
2087 #endif
2088 else
2089 break;
2090 if (serial_hds[i])
2091 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2092 s->dma, serial_hds[i]);
2093
2094 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
2095
2096 s->cm_base = 0x41300000;
2097 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2098 s->clkcfg = 0x00000009; /* Turbo mode active */
2099 iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2100 pxa2xx_cm_writefn, s);
2101 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2102 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2103
2104 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2105
2106 s->mm_base = 0x48000000;
2107 s->mm_regs[MDMRS >> 2] = 0x00020002;
2108 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2109 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2110 iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2111 pxa2xx_mm_writefn, s);
2112 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2113 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2114
2115 s->pm_base = 0x40f00000;
2116 iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2117 pxa2xx_pm_writefn, s);
2118 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2119 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2120
2121 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2122 s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
2123 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2124 DeviceState *dev;
2125 dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
2126 s->pic[pxa27x_ssp[i].irqn]);
2127 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2128 }
2129
2130 if (usb_enabled) {
2131 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2132 s->pic[PXA2XX_PIC_USBH1]);
2133 }
2134
2135 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2136 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2137
2138 s->rtc_base = 0x40900000;
2139 iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
2140 pxa2xx_rtc_writefn, s);
2141 cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2142 pxa2xx_rtc_init(s);
2143 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
2144
2145 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2146 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
2147
2148 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2149
2150 s->kp = pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC_KEYPAD]);
2151
2152 /* GPIO1 resets the processor */
2153 /* The handler can be overridden by board-specific code */
2154 pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
2155 return s;
2156 }
2157
2158 /* Initialise a PXA255 integrated chip (ARM based core). */
2159 PXA2xxState *pxa255_init(unsigned int sdram_size)
2160 {
2161 PXA2xxState *s;
2162 int iomemtype, i;
2163 DriveInfo *dinfo;
2164
2165 s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2166
2167 s->env = cpu_init("pxa255");
2168 if (!s->env) {
2169 fprintf(stderr, "Unable to find CPU definition\n");
2170 exit(1);
2171 }
2172 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2173
2174 /* SDRAM & Internal Memory Storage */
2175 cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2176 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
2177 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2178 qemu_ram_alloc(PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
2179
2180 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2181
2182 s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2183
2184 pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
2185
2186 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
2187
2188 dinfo = drive_get(IF_SD, 0, 0);
2189 if (!dinfo) {
2190 fprintf(stderr, "qemu: missing SecureDigital device\n");
2191 exit(1);
2192 }
2193 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2194 s->pic[PXA2XX_PIC_MMC], s->dma);
2195
2196 for (i = 0; pxa255_serial[i].io_base; i ++)
2197 if (serial_hds[i]) {
2198 #ifdef TARGET_WORDS_BIGENDIAN
2199 serial_mm_init(pxa255_serial[i].io_base, 2,
2200 s->pic[pxa255_serial[i].irqn], 14745600/16,
2201 serial_hds[i], 1, 1);
2202 #else
2203 serial_mm_init(pxa255_serial[i].io_base, 2,
2204 s->pic[pxa255_serial[i].irqn], 14745600/16,
2205 serial_hds[i], 1, 0);
2206 #endif
2207 } else {
2208 break;
2209 }
2210 if (serial_hds[i])
2211 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2212 s->dma, serial_hds[i]);
2213
2214 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
2215
2216 s->cm_base = 0x41300000;
2217 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2218 s->clkcfg = 0x00000009; /* Turbo mode active */
2219 iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2220 pxa2xx_cm_writefn, s);
2221 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2222 register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2223
2224 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2225
2226 s->mm_base = 0x48000000;
2227 s->mm_regs[MDMRS >> 2] = 0x00020002;
2228 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2229 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2230 iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2231 pxa2xx_mm_writefn, s);
2232 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2233 register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2234
2235 s->pm_base = 0x40f00000;
2236 iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2237 pxa2xx_pm_writefn, s);
2238 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2239 register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2240
2241 for (i = 0; pxa255_ssp[i].io_base; i ++);
2242 s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
2243 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2244 DeviceState *dev;
2245 dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
2246 s->pic[pxa255_ssp[i].irqn]);
2247 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2248 }
2249
2250 if (usb_enabled) {
2251 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2252 s->pic[PXA2XX_PIC_USBH1]);
2253 }
2254
2255 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2256 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2257
2258 s->rtc_base = 0x40900000;
2259 iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
2260 pxa2xx_rtc_writefn, s);
2261 cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2262 pxa2xx_rtc_init(s);
2263 register_savevm("pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, pxa2xx_rtc_load, s);
2264
2265 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2266 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
2267
2268 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2269
2270 /* GPIO1 resets the processor */
2271 /* The handler can be overridden by board-specific code */
2272 pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
2273 return s;
2274 }
2275
2276 static void pxa2xx_register_devices(void)
2277 {
2278 i2c_register_slave(&pxa2xx_i2c_slave_info);
2279 sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState), pxa2xx_ssp_init);
2280 }
2281
2282 device_init(pxa2xx_register_devices)
AMD IOMMU emulation for KVM