hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "pc.h"
  21 #include "apic.h"
  22 #include "pci.h"
  23 #include "msix.h"
  24 #include "qemu-timer.h"
  25 #include "host-utils.h"
  26 #include "kvm.h"
  27
  28 //#define DEBUG_APIC
  29 //#define DEBUG_COALESCING
  30
  31 #ifdef DEBUG_APIC
  32 #define DPRINTF(fmt, ...)                                       \
  33     do { printf("apic: " fmt , ## __VA_ARGS__); } while (0)
  34 #else
  35 #define DPRINTF(fmt, ...)
  36 #endif
  37
  38 #ifdef DEBUG_COALESCING
  39 #define DPRINTF_C(fmt, ...)                                     \
  40     do { printf("apic: " fmt , ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF_C(fmt, ...)
  43 #endif
  44
  45 /* APIC Local Vector Table */
  46 #define APIC_LVT_TIMER   0
  47 #define APIC_LVT_THERMAL 1
  48 #define APIC_LVT_PERFORM 2
  49 #define APIC_LVT_LINT0   3
  50 #define APIC_LVT_LINT1   4
  51 #define APIC_LVT_ERROR   5
  52 #define APIC_LVT_NB      6
  53
  54 /* APIC delivery modes */
  55 #define APIC_DM_FIXED   0
  56 #define APIC_DM_LOWPRI  1
  57 #define APIC_DM_SMI     2
  58 #define APIC_DM_NMI     4
  59 #define APIC_DM_INIT    5
  60 #define APIC_DM_SIPI    6
  61 #define APIC_DM_EXTINT  7
  62
  63 /* APIC destination mode */
  64 #define APIC_DESTMODE_FLAT      0xf
  65 #define APIC_DESTMODE_CLUSTER   1
  66
  67 #define APIC_TRIGGER_EDGE  0
  68 #define APIC_TRIGGER_LEVEL 1
  69
  70 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  71 #define APIC_LVT_MASKED                 (1<<16)
  72 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  73 #define APIC_LVT_REMOTE_IRR             (1<<14)
  74 #define APIC_INPUT_POLARITY             (1<<13)
  75 #define APIC_SEND_PENDING               (1<<12)
  76
  77 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  78
  79 #define APIC_SV_ENABLE (1 << 8)
  80
  81 #define MAX_APICS 255
  82 #define MAX_APIC_WORDS 8
  83
  84 /* Intel APIC constants: from include/asm/msidef.h */
  85 #define MSI_DATA_VECTOR_SHIFT           0
  86 #define MSI_DATA_VECTOR_MASK            0x000000ff
  87 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  88 #define MSI_DATA_TRIGGER_SHIFT          15
  89 #define MSI_DATA_LEVEL_SHIFT            14
  90 #define MSI_ADDR_DEST_MODE_SHIFT        2
  91 #define MSI_ADDR_DEST_ID_SHIFT          12
  92 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  93
  94 #define MSI_ADDR_BASE                   0xfee00000
  95 #define MSI_ADDR_SIZE                   0x100000
  96
  97 typedef struct APICState {
  98     CPUState *cpu_env;
  99     uint32_t apicbase;
 100     uint8_t id;
 101     uint8_t arb_id;
 102     uint8_t tpr;
 103     uint32_t spurious_vec;
 104     uint8_t log_dest;
 105     uint8_t dest_mode;
 106     uint32_t isr[8];  /* in service register */
 107     uint32_t tmr[8];  /* trigger mode register */
 108     uint32_t irr[8]; /* interrupt request register */
 109     uint32_t lvt[APIC_LVT_NB];
 110     uint32_t esr; /* error register */
 111     uint32_t icr[2];
 112
 113     uint32_t divide_conf;
 114     int count_shift;
 115     uint32_t initial_count;
 116     int64_t initial_count_load_time, next_time;
 117     uint32_t idx;
 118     QEMUTimer *timer;
 119     int sipi_vector;
 120     int wait_for_sipi;
 121 } APICState;
 122
 123 static int apic_io_memory;
 124 static APICState *local_apics[MAX_APICS + 1];
 125 static int last_apic_idx = 0;
 126 static int apic_irq_delivered;
 127
 128
 129 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 130 static void apic_update_irq(APICState *s);
 131 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 132                                       uint8_t dest, uint8_t dest_mode);
 133
 134 /* Find first bit starting from msb */
 135 static int fls_bit(uint32_t value)
 136 {
 137     return 31 - clz32(value);
 138 }
 139
 140 /* Find first bit starting from lsb */
 141 static int ffs_bit(uint32_t value)
 142 {
 143     return ctz32(value);
 144 }
 145
 146 static inline void set_bit(uint32_t *tab, int index)
 147 {
 148     int i, mask;
 149     i = index >> 5;
 150     mask = 1 << (index & 0x1f);
 151     tab[i] |= mask;
 152 }
 153
 154 static inline void reset_bit(uint32_t *tab, int index)
 155 {
 156     int i, mask;
 157     i = index >> 5;
 158     mask = 1 << (index & 0x1f);
 159     tab[i] &= ~mask;
 160 }
 161
 162 static inline int get_bit(uint32_t *tab, int index)
 163 {
 164     int i, mask;
 165     i = index >> 5;
 166     mask = 1 << (index & 0x1f);
 167     return !!(tab[i] & mask);
 168 }
 169
 170 static void apic_local_deliver(CPUState *env, int vector)
 171 {
 172     APICState *s = env->apic_state;
 173     uint32_t lvt = s->lvt[vector];
 174     int trigger_mode;
 175
 176     DPRINTF("%s: vector %d delivery mode %d\n", __func__, vector,
 177             (lvt >> 8) & 7);
 178     if (lvt & APIC_LVT_MASKED)
 179         return;
 180
 181     switch ((lvt >> 8) & 7) {
 182     case APIC_DM_SMI:
 183         cpu_interrupt(env, CPU_INTERRUPT_SMI);
 184         break;
 185
 186     case APIC_DM_NMI:
 187         cpu_interrupt(env, CPU_INTERRUPT_NMI);
 188         break;
 189
 190     case APIC_DM_EXTINT:
 191         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 192         break;
 193
 194     case APIC_DM_FIXED:
 195         trigger_mode = APIC_TRIGGER_EDGE;
 196         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 197             (lvt & APIC_LVT_LEVEL_TRIGGER))
 198             trigger_mode = APIC_TRIGGER_LEVEL;
 199         apic_set_irq(s, lvt & 0xff, trigger_mode);
 200     }
 201 }
 202
 203 void apic_deliver_pic_intr(CPUState *env, int level)
 204 {
 205     if (level)
 206         apic_local_deliver(env, APIC_LVT_LINT0);
 207     else {
 208         APICState *s = env->apic_state;
 209         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 210
 211         switch ((lvt >> 8) & 7) {
 212         case APIC_DM_FIXED:
 213             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 214                 break;
 215             reset_bit(s->irr, lvt & 0xff);
 216             /* fall through */
 217         case APIC_DM_EXTINT:
 218             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 219             break;
 220         }
 221     }
 222 }
 223
 224 #define foreach_apic(apic, deliver_bitmask, code) \
 225 {\
 226     int __i, __j, __mask;\
 227     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 228         __mask = deliver_bitmask[__i];\
 229         if (__mask) {\
 230             for(__j = 0; __j < 32; __j++) {\
 231                 if (__mask & (1 << __j)) {\
 232                     apic = local_apics[__i * 32 + __j];\
 233                     if (apic) {\
 234                         code;\
 235                     }\
 236                 }\
 237             }\
 238         }\
 239     }\
 240 }
 241
 242 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 243                              uint8_t delivery_mode,
 244                              uint8_t vector_num, uint8_t polarity,
 245                              uint8_t trigger_mode)
 246 {
 247     APICState *apic_iter;
 248
 249     switch (delivery_mode) {
 250         case APIC_DM_LOWPRI:
 251             /* XXX: search for focus processor, arbitration */
 252             {
 253                 int i, d;
 254                 d = -1;
 255                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 256                     if (deliver_bitmask[i]) {
 257                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 258                         break;
 259                     }
 260                 }
 261                 if (d >= 0) {
 262                     apic_iter = local_apics[d];
 263                     if (apic_iter) {
 264                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 265                     }
 266                 }
 267             }
 268             return;
 269
 270         case APIC_DM_FIXED:
 271             break;
 272
 273         case APIC_DM_SMI:
 274             foreach_apic(apic_iter, deliver_bitmask,
 275                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 276             return;
 277
 278         case APIC_DM_NMI:
 279             foreach_apic(apic_iter, deliver_bitmask,
 280                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 281             return;
 282
 283         case APIC_DM_INIT:
 284             /* normal INIT IPI sent to processors */
 285             foreach_apic(apic_iter, deliver_bitmask,
 286                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 287             return;
 288
 289         case APIC_DM_EXTINT:
 290             /* handled in I/O APIC code */
 291             break;
 292
 293         default:
 294             return;
 295     }
 296
 297     foreach_apic(apic_iter, deliver_bitmask,
 298                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 299 }
 300
 301 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 302                       uint8_t delivery_mode, uint8_t vector_num,
 303                       uint8_t polarity, uint8_t trigger_mode)
 304 {
 305     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 306
 307     DPRINTF("%s: dest %d dest_mode %d delivery_mode %d vector %d"
 308             " polarity %d trigger_mode %d\n", __func__, dest, dest_mode,
 309             delivery_mode, vector_num, polarity, trigger_mode);
 310     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 311     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 312                      trigger_mode);
 313 }
 314
 315 void cpu_set_apic_base(CPUState *env, uint64_t val)
 316 {
 317     APICState *s = env->apic_state;
 318
 319     DPRINTF("cpu_set_apic_base: %016" PRIx64 "\n", val);
 320     if (!s)
 321         return;
 322     if (kvm_enabled() && kvm_irqchip_in_kernel())
 323         s->apicbase = val;
 324     else
 325         s->apicbase = (val & 0xfffff000) |
 326             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 327     /* if disabled, cannot be enabled again */
 328     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 329         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 330         env->cpuid_features &= ~CPUID_APIC;
 331         s->spurious_vec &= ~APIC_SV_ENABLE;
 332     }
 333 }
 334
 335 uint64_t cpu_get_apic_base(CPUState *env)
 336 {
 337     APICState *s = env->apic_state;
 338
 339     DPRINTF("cpu_get_apic_base: %016" PRIx64 "\n",
 340             s ? (uint64_t)s->apicbase: 0);
 341     return s ? s->apicbase : 0;
 342 }
 343
 344 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 345 {
 346     APICState *s = env->apic_state;
 347     if (!s)
 348         return;
 349     s->tpr = (val & 0x0f) << 4;
 350     apic_update_irq(s);
 351 }
 352
 353 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 354 {
 355     APICState *s = env->apic_state;
 356     return s ? s->tpr >> 4 : 0;
 357 }
 358
 359 /* return -1 if no bit is set */
 360 static int get_highest_priority_int(uint32_t *tab)
 361 {
 362     int i;
 363     for(i = 7; i >= 0; i--) {
 364         if (tab[i] != 0) {
 365             return i * 32 + fls_bit(tab[i]);
 366         }
 367     }
 368     return -1;
 369 }
 370
 371 static int apic_get_ppr(APICState *s)
 372 {
 373     int tpr, isrv, ppr;
 374
 375     tpr = (s->tpr >> 4);
 376     isrv = get_highest_priority_int(s->isr);
 377     if (isrv < 0)
 378         isrv = 0;
 379     isrv >>= 4;
 380     if (tpr >= isrv)
 381         ppr = s->tpr;
 382     else
 383         ppr = isrv << 4;
 384     return ppr;
 385 }
 386
 387 static int apic_get_arb_pri(APICState *s)
 388 {
 389     /* XXX: arbitration */
 390     return 0;
 391 }
 392
 393 /* signal the CPU if an irq is pending */
 394 static void apic_update_irq(APICState *s)
 395 {
 396     int irrv, ppr;
 397     if (!(s->spurious_vec & APIC_SV_ENABLE))
 398         return;
 399     irrv = get_highest_priority_int(s->irr);
 400     if (irrv < 0)
 401         return;
 402     ppr = apic_get_ppr(s);
 403     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 404         return;
 405     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 406 }
 407
 408 void apic_reset_irq_delivered(void)
 409 {
 410     DPRINTF_C("%s: old coalescing %d\n", __func__, apic_irq_delivered);
 411     apic_irq_delivered = 0;
 412 }
 413
 414 int apic_get_irq_delivered(void)
 415 {
 416     DPRINTF_C("%s: returning coalescing %d\n", __func__, apic_irq_delivered);
 417     return apic_irq_delivered;
 418 }
 419
 420 void apic_set_irq_delivered(void)
 421 {
 422     apic_irq_delivered = 1;
 423 }
 424
 425 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 426 {
 427     apic_irq_delivered += !get_bit(s->irr, vector_num);
 428     DPRINTF_C("%s: coalescing %d\n", __func__, apic_irq_delivered);
 429
 430     set_bit(s->irr, vector_num);
 431     if (trigger_mode)
 432         set_bit(s->tmr, vector_num);
 433     else
 434         reset_bit(s->tmr, vector_num);
 435     apic_update_irq(s);
 436 }
 437
 438 static void apic_eoi(APICState *s)
 439 {
 440     int isrv;
 441     isrv = get_highest_priority_int(s->isr);
 442     if (isrv < 0)
 443         return;
 444     reset_bit(s->isr, isrv);
 445     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 446             set the remote IRR bit for level triggered interrupts. */
 447     apic_update_irq(s);
 448 }
 449
 450 static int apic_find_dest(uint8_t dest)
 451 {
 452     APICState *apic = local_apics[dest];
 453     int i;
 454
 455     if (apic && apic->id == dest)
 456         return dest;  /* shortcut in case apic->id == apic->idx */
 457
 458     for (i = 0; i < MAX_APICS; i++) {
 459         apic = local_apics[i];
 460         if (apic && apic->id == dest)
 461             return i;
 462     }
 463
 464     return -1;
 465 }
 466
 467 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 468                                       uint8_t dest, uint8_t dest_mode)
 469 {
 470     APICState *apic_iter;
 471     int i;
 472
 473     if (dest_mode == 0) {
 474         if (dest == 0xff) {
 475             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 476         } else {
 477             int idx = apic_find_dest(dest);
 478             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 479             if (idx >= 0)
 480                 set_bit(deliver_bitmask, idx);
 481         }
 482     } else {
 483         /* XXX: cluster mode */
 484         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 485         for(i = 0; i < MAX_APICS; i++) {
 486             apic_iter = local_apics[i];
 487             if (apic_iter) {
 488                 if (apic_iter->dest_mode == 0xf) {
 489                     if (dest & apic_iter->log_dest)
 490                         set_bit(deliver_bitmask, i);
 491                 } else if (apic_iter->dest_mode == 0x0) {
 492                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 493                         (dest & apic_iter->log_dest & 0x0f)) {
 494                         set_bit(deliver_bitmask, i);
 495                     }
 496                 }
 497             }
 498         }
 499     }
 500 }
 501
 502
 503 void apic_init_reset(CPUState *env)
 504 {
 505     APICState *s = env->apic_state;
 506     int i;
 507
 508     if (!s)
 509         return;
 510
 511     s->tpr = 0;
 512     s->spurious_vec = 0xff;
 513     s->log_dest = 0;
 514     s->dest_mode = 0xf;
 515     memset(s->isr, 0, sizeof(s->isr));
 516     memset(s->tmr, 0, sizeof(s->tmr));
 517     memset(s->irr, 0, sizeof(s->irr));
 518     for(i = 0; i < APIC_LVT_NB; i++)
 519         s->lvt[i] = 1 << 16; /* mask LVT */
 520     s->esr = 0;
 521     memset(s->icr, 0, sizeof(s->icr));
 522     s->divide_conf = 0;
 523     s->count_shift = 0;
 524     s->initial_count = 0;
 525     s->initial_count_load_time = 0;
 526     s->next_time = 0;
 527     s->wait_for_sipi = 1;
 528
 529     env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP);
 530 }
 531
 532 static void apic_startup(APICState *s, int vector_num)
 533 {
 534     s->sipi_vector = vector_num;
 535     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 536 }
 537
 538 void apic_sipi(CPUState *env)
 539 {
 540     APICState *s = env->apic_state;
 541
 542     cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI);
 543
 544     if (!s->wait_for_sipi)
 545         return;
 546
 547     env->eip = 0;
 548     cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12,
 549                            env->segs[R_CS].limit, env->segs[R_CS].flags);
 550     env->halted = 0;
 551     s->wait_for_sipi = 0;
 552 }
 553
 554 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 555                          uint8_t delivery_mode, uint8_t vector_num,
 556                          uint8_t polarity, uint8_t trigger_mode)
 557 {
 558     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 559     int dest_shorthand = (s->icr[0] >> 18) & 3;
 560     APICState *apic_iter;
 561
 562     switch (dest_shorthand) {
 563     case 0:
 564         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 565         break;
 566     case 1:
 567         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 568         set_bit(deliver_bitmask, s->idx);
 569         break;
 570     case 2:
 571         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 572         break;
 573     case 3:
 574         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 575         reset_bit(deliver_bitmask, s->idx);
 576         break;
 577     }
 578
 579     switch (delivery_mode) {
 580         case APIC_DM_INIT:
 581             {
 582                 int trig_mode = (s->icr[0] >> 15) & 1;
 583                 int level = (s->icr[0] >> 14) & 1;
 584                 if (level == 0 && trig_mode == 1) {
 585                     foreach_apic(apic_iter, deliver_bitmask,
 586                                  apic_iter->arb_id = apic_iter->id );
 587                     return;
 588                 }
 589             }
 590             break;
 591
 592         case APIC_DM_SIPI:
 593             foreach_apic(apic_iter, deliver_bitmask,
 594                          apic_startup(apic_iter, vector_num) );
 595             return;
 596     }
 597
 598     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 599                      trigger_mode);
 600 }
 601
 602 int apic_get_interrupt(CPUState *env)
 603 {
 604     APICState *s = env->apic_state;
 605     int intno;
 606
 607     /* if the APIC is installed or enabled, we let the 8259 handle the
 608        IRQs */
 609     if (!s)
 610         return -1;
 611     if (!(s->spurious_vec & APIC_SV_ENABLE))
 612         return -1;
 613
 614     /* XXX: spurious IRQ handling */
 615     intno = get_highest_priority_int(s->irr);
 616     if (intno < 0)
 617         return -1;
 618     if (s->tpr && intno <= s->tpr)
 619         return s->spurious_vec & 0xff;
 620     reset_bit(s->irr, intno);
 621     set_bit(s->isr, intno);
 622     apic_update_irq(s);
 623     return intno;
 624 }
 625
 626 int apic_accept_pic_intr(CPUState *env)
 627 {
 628     APICState *s = env->apic_state;
 629     uint32_t lvt0;
 630
 631     if (!s)
 632         return -1;
 633
 634     lvt0 = s->lvt[APIC_LVT_LINT0];
 635
 636     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 637         (lvt0 & APIC_LVT_MASKED) == 0)
 638         return 1;
 639
 640     return 0;
 641 }
 642
 643 static uint32_t apic_get_current_count(APICState *s)
 644 {
 645     int64_t d;
 646     uint32_t val;
 647     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 648         s->count_shift;
 649     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 650         /* periodic */
 651         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 652     } else {
 653         if (d >= s->initial_count)
 654             val = 0;
 655         else
 656             val = s->initial_count - d;
 657     }
 658     return val;
 659 }
 660
 661 static void apic_timer_update(APICState *s, int64_t current_time)
 662 {
 663     int64_t next_time, d;
 664
 665     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 666         d = (current_time - s->initial_count_load_time) >>
 667             s->count_shift;
 668         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 669             if (!s->initial_count)
 670                 goto no_timer;
 671             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 672         } else {
 673             if (d >= s->initial_count)
 674                 goto no_timer;
 675             d = (uint64_t)s->initial_count + 1;
 676         }
 677         next_time = s->initial_count_load_time + (d << s->count_shift);
 678         qemu_mod_timer(s->timer, next_time);
 679         s->next_time = next_time;
 680     } else {
 681     no_timer:
 682         qemu_del_timer(s->timer);
 683     }
 684 }
 685
 686 static void apic_timer(void *opaque)
 687 {
 688     APICState *s = opaque;
 689
 690     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
 691     apic_timer_update(s, s->next_time);
 692 }
 693
 694 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 695 {
 696     return 0;
 697 }
 698
 699 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 700 {
 701     return 0;
 702 }
 703
 704 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 705 {
 706 }
 707
 708 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 709 {
 710 }
 711
 712 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 713 {
 714     CPUState *env;
 715     APICState *s;
 716     uint32_t val;
 717     int index;
 718
 719     env = cpu_single_env;
 720     if (!env)
 721         return 0;
 722     s = env->apic_state;
 723
 724     index = (addr >> 4) & 0xff;
 725     switch(index) {
 726     case 0x02: /* id */
 727         val = s->id << 24;
 728         break;
 729     case 0x03: /* version */
 730         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 731         break;
 732     case 0x08:
 733         val = s->tpr;
 734         break;
 735     case 0x09:
 736         val = apic_get_arb_pri(s);
 737         break;
 738     case 0x0a:
 739         /* ppr */
 740         val = apic_get_ppr(s);
 741         break;
 742     case 0x0b:
 743         val = 0;
 744         break;
 745     case 0x0d:
 746         val = s->log_dest << 24;
 747         break;
 748     case 0x0e:
 749         val = s->dest_mode << 28;
 750         break;
 751     case 0x0f:
 752         val = s->spurious_vec;
 753         break;
 754     case 0x10 ... 0x17:
 755         val = s->isr[index & 7];
 756         break;
 757     case 0x18 ... 0x1f:
 758         val = s->tmr[index & 7];
 759         break;
 760     case 0x20 ... 0x27:
 761         val = s->irr[index & 7];
 762         break;
 763     case 0x28:
 764         val = s->esr;
 765         break;
 766     case 0x30:
 767     case 0x31:
 768         val = s->icr[index & 1];
 769         break;
 770     case 0x32 ... 0x37:
 771         val = s->lvt[index - 0x32];
 772         break;
 773     case 0x38:
 774         val = s->initial_count;
 775         break;
 776     case 0x39:
 777         val = apic_get_current_count(s);
 778         break;
 779     case 0x3e:
 780         val = s->divide_conf;
 781         break;
 782     default:
 783         s->esr |= ESR_ILLEGAL_ADDRESS;
 784         val = 0;
 785         break;
 786     }
 787     DPRINTF("read: " TARGET_FMT_plx " = %08x\n", addr, val);
 788     return val;
 789 }
 790
 791 static void apic_send_msi(target_phys_addr_t addr, uint32 data)
 792 {
 793     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 794     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 795     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 796     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 797     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 798     /* XXX: Ignore redirection hint. */
 799     apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
 800 }
 801
 802 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 803 {
 804     CPUState *env;
 805     APICState *s;
 806     int index = (addr >> 4) & 0xff;
 807     if (addr > 0xfff || !index) {
 808         /* MSI and MMIO APIC are at the same memory location,
 809          * but actually not on the global bus: MSI is on PCI bus
 810          * APIC is connected directly to the CPU.
 811          * Mapping them on the global bus happens to work because
 812          * MSI registers are reserved in APIC MMIO and vice versa. */
 813         apic_send_msi(addr, val);
 814         return;
 815     }
 816
 817     env = cpu_single_env;
 818     if (!env)
 819         return;
 820     s = env->apic_state;
 821
 822     DPRINTF("write: " TARGET_FMT_plx " = %08x\n", addr, val);
 823
 824     switch(index) {
 825     case 0x02:
 826         s->id = (val >> 24);
 827         break;
 828     case 0x03:
 829         break;
 830     case 0x08:
 831         s->tpr = val;
 832         apic_update_irq(s);
 833         break;
 834     case 0x09:
 835     case 0x0a:
 836         break;
 837     case 0x0b: /* EOI */
 838         apic_eoi(s);
 839         break;
 840     case 0x0d:
 841         s->log_dest = val >> 24;
 842         break;
 843     case 0x0e:
 844         s->dest_mode = val >> 28;
 845         break;
 846     case 0x0f:
 847         s->spurious_vec = val & 0x1ff;
 848         apic_update_irq(s);
 849         break;
 850     case 0x10 ... 0x17:
 851     case 0x18 ... 0x1f:
 852     case 0x20 ... 0x27:
 853     case 0x28:
 854         break;
 855     case 0x30:
 856         s->icr[0] = val;
 857         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 858                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 859                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 860         break;
 861     case 0x31:
 862         s->icr[1] = val;
 863         break;
 864     case 0x32 ... 0x37:
 865         {
 866             int n = index - 0x32;
 867             s->lvt[n] = val;
 868             if (n == APIC_LVT_TIMER)
 869                 apic_timer_update(s, qemu_get_clock(vm_clock));
 870         }
 871         break;
 872     case 0x38:
 873         s->initial_count = val;
 874         s->initial_count_load_time = qemu_get_clock(vm_clock);
 875         apic_timer_update(s, s->initial_count_load_time);
 876         break;
 877     case 0x39:
 878         break;
 879     case 0x3e:
 880         {
 881             int v;
 882             s->divide_conf = val & 0xb;
 883             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 884             s->count_shift = (v + 1) & 7;
 885         }
 886         break;
 887     default:
 888         s->esr |= ESR_ILLEGAL_ADDRESS;
 889         break;
 890     }
 891 }
 892
 893 #ifdef KVM_CAP_IRQCHIP
 894
 895 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 896 {
 897     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 898 }
 899
 900 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 901                                  int reg_id, uint32_t val)
 902 {
 903     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 904 }
 905
 906 static void kvm_kernel_lapic_save_to_user(APICState *s)
 907 {
 908     struct kvm_lapic_state apic;
 909     struct kvm_lapic_state *kapic = &apic;
 910     int i, v;
 911
 912     kvm_get_lapic(s->cpu_env, kapic);
 913
 914     s->id = kapic_reg(kapic, 0x2) >> 24;
 915     s->tpr = kapic_reg(kapic, 0x8);
 916     s->arb_id = kapic_reg(kapic, 0x9);
 917     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 918     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 919     s->spurious_vec = kapic_reg(kapic, 0xf);
 920     for (i = 0; i < 8; i++) {
 921         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 922         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 923         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 924     }
 925     s->esr = kapic_reg(kapic, 0x28);
 926     s->icr[0] = kapic_reg(kapic, 0x30);
 927     s->icr[1] = kapic_reg(kapic, 0x31);
 928     for (i = 0; i < APIC_LVT_NB; i++)
 929         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 930     s->initial_count = kapic_reg(kapic, 0x38);
 931     s->divide_conf = kapic_reg(kapic, 0x3e);
 932
 933     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 934     s->count_shift = (v + 1) & 7;
 935
 936     s->initial_count_load_time = qemu_get_clock(vm_clock);
 937     apic_timer_update(s, s->initial_count_load_time);
 938 }
 939
 940 static void kvm_kernel_lapic_load_from_user(APICState *s)
 941 {
 942     struct kvm_lapic_state apic;
 943     struct kvm_lapic_state *klapic = &apic;
 944     int i;
 945
 946     memset(klapic, 0, sizeof apic);
 947     kapic_set_reg(klapic, 0x2, s->id << 24);
 948     kapic_set_reg(klapic, 0x8, s->tpr);
 949     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 950     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 951     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 952     for (i = 0; i < 8; i++) {
 953         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 954         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 955         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 956     }
 957     kapic_set_reg(klapic, 0x28, s->esr);
 958     kapic_set_reg(klapic, 0x30, s->icr[0]);
 959     kapic_set_reg(klapic, 0x31, s->icr[1]);
 960     for (i = 0; i < APIC_LVT_NB; i++)
 961         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 962     kapic_set_reg(klapic, 0x38, s->initial_count);
 963     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 964
 965     kvm_set_lapic(s->cpu_env, klapic);
 966 }
 967
 968 #endif
 969
 970 void kvm_load_lapic(CPUState *env)
 971 {
 972 #ifdef KVM_CAP_IRQCHIP
 973     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 974         kvm_kernel_lapic_load_from_user(env->apic_state);
 975     }
 976 #endif
 977 }
 978
 979 void kvm_save_lapic(CPUState *env)
 980 {
 981 #ifdef KVM_CAP_IRQCHIP
 982     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 983         kvm_kernel_lapic_save_to_user(env->apic_state);
 984     }
 985 #endif
 986 }
 987
 988 /* This function is only used for old state version 1 and 2 */
 989 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 990 {
 991     APICState *s = opaque;
 992     int i;
 993
 994     if (version_id > 2)
 995         return -EINVAL;
 996
 997     /* XXX: what if the base changes? (registered memory regions) */
 998     qemu_get_be32s(f, &s->apicbase);
 999     qemu_get_8s(f, &s->id);
1000     qemu_get_8s(f, &s->arb_id);
1001     qemu_get_8s(f, &s->tpr);
1002     qemu_get_be32s(f, &s->spurious_vec);
1003     qemu_get_8s(f, &s->log_dest);
1004     qemu_get_8s(f, &s->dest_mode);
1005     for (i = 0; i < 8; i++) {
1006         qemu_get_be32s(f, &s->isr[i]);
1007         qemu_get_be32s(f, &s->tmr[i]);
1008         qemu_get_be32s(f, &s->irr[i]);
1009     }
1010     for (i = 0; i < APIC_LVT_NB; i++) {
1011         qemu_get_be32s(f, &s->lvt[i]);
1012     }
1013     qemu_get_be32s(f, &s->esr);
1014     qemu_get_be32s(f, &s->icr[0]);
1015     qemu_get_be32s(f, &s->icr[1]);
1016     qemu_get_be32s(f, &s->divide_conf);
1017     s->count_shift=qemu_get_be32(f);
1018     qemu_get_be32s(f, &s->initial_count);
1019     s->initial_count_load_time=qemu_get_be64(f);
1020     s->next_time=qemu_get_be64(f);
1021
1022     if (version_id >= 2)
1023         qemu_get_timer(f, s->timer);
1024     return 0;
1025 }
1026
1027 static const VMStateDescription vmstate_apic = {
1028     .name = "apic",
1029     .version_id = 3,
1030     .minimum_version_id = 3,
1031     .minimum_version_id_old = 1,
1032     .load_state_old = apic_load_old,
1033     .fields      = (VMStateField []) {
1034         VMSTATE_UINT32(apicbase, APICState),
1035         VMSTATE_UINT8(id, APICState),
1036         VMSTATE_UINT8(arb_id, APICState),
1037         VMSTATE_UINT8(tpr, APICState),
1038         VMSTATE_UINT32(spurious_vec, APICState),
1039         VMSTATE_UINT8(log_dest, APICState),
1040         VMSTATE_UINT8(dest_mode, APICState),
1041         VMSTATE_UINT32_ARRAY(isr, APICState, 8),
1042         VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
1043         VMSTATE_UINT32_ARRAY(irr, APICState, 8),
1044         VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
1045         VMSTATE_UINT32(esr, APICState),
1046         VMSTATE_UINT32_ARRAY(icr, APICState, 2),
1047         VMSTATE_UINT32(divide_conf, APICState),
1048         VMSTATE_INT32(count_shift, APICState),
1049         VMSTATE_UINT32(initial_count, APICState),
1050         VMSTATE_INT64(initial_count_load_time, APICState),
1051         VMSTATE_INT64(next_time, APICState),
1052         VMSTATE_TIMER(timer, APICState),
1053         VMSTATE_END_OF_LIST()
1054     }
1055 };
1056
1057 static void apic_reset(void *opaque)
1058 {
1059     APICState *s = opaque;
1060     int bsp;
1061
1062     bsp = cpu_is_bsp(s->cpu_env);
1063     s->apicbase = 0xfee00000 |
1064         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
1065
1066     cpu_reset(s->cpu_env);
1067     apic_init_reset(s->cpu_env);
1068
1069     if (bsp) {
1070         /*
1071          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1072          * time typically by BIOS, so PIC interrupt can be delivered to the
1073          * processor when local APIC is enabled.
1074          */
1075         s->lvt[APIC_LVT_LINT0] = 0x700;
1076     }
1077 }
1078
1079 static CPUReadMemoryFunc * const apic_mem_read[3] = {
1080     apic_mem_readb,
1081     apic_mem_readw,
1082     apic_mem_readl,
1083 };
1084
1085 static CPUWriteMemoryFunc * const apic_mem_write[3] = {
1086     apic_mem_writeb,
1087     apic_mem_writew,
1088     apic_mem_writel,
1089 };
1090
1091 int apic_init(CPUState *env)
1092 {
1093     APICState *s;
1094
1095     if (last_apic_idx >= MAX_APICS)
1096         return -1;
1097     s = qemu_mallocz(sizeof(APICState));
1098     env->apic_state = s;
1099     s->idx = last_apic_idx++;
1100     s->id = env->cpuid_apic_id;
1101     s->cpu_env = env;
1102
1103     msix_supported = 1;
1104
1105     /* XXX: mapping more APICs at the same memory location */
1106     if (apic_io_memory == 0) {
1107         /* NOTE: the APIC is directly connected to the CPU - it is not
1108            on the global memory bus. */
1109         apic_io_memory = cpu_register_io_memory(apic_mem_read,
1110                                                 apic_mem_write, NULL);
1111         /* XXX: what if the base changes? */
1112         cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE,
1113                                      apic_io_memory);
1114     }
1115     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1116
1117     vmstate_register(s->idx, &vmstate_apic, s);
1118     qemu_register_reset(apic_reset, s);
1119
1120     local_apics[s->idx] = s;
1121     return 0;
1122 }