hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32
  33 //#define HPET_DEBUG
  34 #ifdef HPET_DEBUG
  35 #define DPRINTF printf
  36 #else
  37 #define DPRINTF(...)
  38 #endif
  39
  40 struct HPETState;
  41 typedef struct HPETTimer {  /* timers */
  42     uint8_t tn;             /*timer number*/
  43     QEMUTimer *qemu_timer;
  44     struct HPETState *state;
  45     /* Memory-mapped, software visible timer registers */
  46     uint64_t config;        /* configuration/cap */
  47     uint64_t cmp;           /* comparator */
  48     uint64_t fsb;           /* FSB route, not supported now */
  49     /* Hidden register state */
  50     uint64_t period;        /* Last value written to comparator */
  51     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  52                              * mode. Next pop will be actual timer expiration.
  53                              */
  54 } HPETTimer;
  55
  56 typedef struct HPETState {
  57     uint64_t hpet_offset;
  58     qemu_irq *irqs;
  59     HPETTimer timer[HPET_NUM_TIMERS];
  60
  61     /* Memory-mapped, software visible registers */
  62     uint64_t capability;        /* capabilities */
  63     uint64_t config;            /* configuration */
  64     uint64_t isr;               /* interrupt status reg */
  65     uint64_t hpet_counter;      /* main counter */
  66 } HPETState;
  67
  68 static HPETState *hpet_statep;
  69
  70 uint32_t hpet_in_legacy_mode(void)
  71 {
  72     if (!hpet_statep) {
  73         return 0;
  74     }
  75     return hpet_statep->config & HPET_CFG_LEGACY;
  76 }
  77
  78 static uint32_t timer_int_route(struct HPETTimer *timer)
  79 {
  80     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  81 }
  82
  83 static uint32_t hpet_enabled(void)
  84 {
  85     return hpet_statep->config & HPET_CFG_ENABLE;
  86 }
  87
  88 static uint32_t timer_is_periodic(HPETTimer *t)
  89 {
  90     return t->config & HPET_TN_PERIODIC;
  91 }
  92
  93 static uint32_t timer_enabled(HPETTimer *t)
  94 {
  95     return t->config & HPET_TN_ENABLE;
  96 }
  97
  98 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
  99 {
 100     return ((int32_t)(b) - (int32_t)(a) < 0);
 101 }
 102
 103 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 104 {
 105     return ((int64_t)(b) - (int64_t)(a) < 0);
 106 }
 107
 108 static uint64_t ticks_to_ns(uint64_t value)
 109 {
 110     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 111 }
 112
 113 static uint64_t ns_to_ticks(uint64_t value)
 114 {
 115     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 116 }
 117
 118 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 119 {
 120     new &= mask;
 121     new |= old & ~mask;
 122     return new;
 123 }
 124
 125 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 126 {
 127     return (!(old & mask) && (new & mask));
 128 }
 129
 130 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 131 {
 132     return ((old & mask) && !(new & mask));
 133 }
 134
 135 static uint64_t hpet_get_ticks(void)
 136 {
 137     return ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
 138 }
 139
 140 /*
 141  * calculate diff between comparator value and current ticks
 142  */
 143 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 144 {
 145
 146     if (t->config & HPET_TN_32BIT) {
 147         uint32_t diff, cmp;
 148
 149         cmp = (uint32_t)t->cmp;
 150         diff = cmp - (uint32_t)current;
 151         diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
 152         return (uint64_t)diff;
 153     } else {
 154         uint64_t diff, cmp;
 155
 156         cmp = t->cmp;
 157         diff = cmp - current;
 158         diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
 159         return diff;
 160     }
 161 }
 162
 163 static void update_irq(struct HPETTimer *timer)
 164 {
 165     int route;
 166
 167     if (timer->tn <= 1 && hpet_in_legacy_mode()) {
 168         /* if LegacyReplacementRoute bit is set, HPET specification requires
 169          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 170          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 171          */
 172         route = (timer->tn == 0) ? 0 : 8;
 173     } else {
 174         route = timer_int_route(timer);
 175     }
 176     if (!timer_enabled(timer) || !hpet_enabled()) {
 177         return;
 178     }
 179     qemu_irq_pulse(timer->state->irqs[route]);
 180 }
 181
 182 static void hpet_pre_save(void *opaque)
 183 {
 184     HPETState *s = opaque;
 185
 186     /* save current counter value */
 187     s->hpet_counter = hpet_get_ticks();
 188 }
 189
 190 static int hpet_post_load(void *opaque, int version_id)
 191 {
 192     HPETState *s = opaque;
 193
 194     /* Recalculate the offset between the main counter and guest time */
 195     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 196
 197     if (hpet_in_legacy_mode()) {
 198         hpet_pit_disable();
 199     }
 200
 201     return 0;
 202 }
 203
 204 static const VMStateDescription vmstate_hpet_timer = {
 205     .name = "hpet_timer",
 206     .version_id = 1,
 207     .minimum_version_id = 1,
 208     .minimum_version_id_old = 1,
 209     .fields      = (VMStateField []) {
 210         VMSTATE_UINT8(tn, HPETTimer),
 211         VMSTATE_UINT64(config, HPETTimer),
 212         VMSTATE_UINT64(cmp, HPETTimer),
 213         VMSTATE_UINT64(fsb, HPETTimer),
 214         VMSTATE_UINT64(period, HPETTimer),
 215         VMSTATE_UINT8(wrap_flag, HPETTimer),
 216         VMSTATE_TIMER(qemu_timer, HPETTimer),
 217         VMSTATE_END_OF_LIST()
 218     }
 219 };
 220
 221 static const VMStateDescription vmstate_hpet = {
 222     .name = "hpet",
 223     .version_id = 1,
 224     .minimum_version_id = 1,
 225     .minimum_version_id_old = 1,
 226     .pre_save = hpet_pre_save,
 227     .post_load = hpet_post_load,
 228     .fields      = (VMStateField []) {
 229         VMSTATE_UINT64(config, HPETState),
 230         VMSTATE_UINT64(isr, HPETState),
 231         VMSTATE_UINT64(hpet_counter, HPETState),
 232         VMSTATE_STRUCT_ARRAY(timer, HPETState, HPET_NUM_TIMERS, 0,
 233                              vmstate_hpet_timer, HPETTimer),
 234         VMSTATE_END_OF_LIST()
 235     }
 236 };
 237
 238 /*
 239  * timer expiration callback
 240  */
 241 static void hpet_timer(void *opaque)
 242 {
 243     HPETTimer *t = opaque;
 244     uint64_t diff;
 245
 246     uint64_t period = t->period;
 247     uint64_t cur_tick = hpet_get_ticks();
 248
 249     if (timer_is_periodic(t) && period != 0) {
 250         if (t->config & HPET_TN_32BIT) {
 251             while (hpet_time_after(cur_tick, t->cmp)) {
 252                 t->cmp = (uint32_t)(t->cmp + t->period);
 253             }
 254         } else {
 255             while (hpet_time_after64(cur_tick, t->cmp)) {
 256                 t->cmp += period;
 257             }
 258         }
 259         diff = hpet_calculate_diff(t, cur_tick);
 260         qemu_mod_timer(t->qemu_timer,
 261                        qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 262     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 263         if (t->wrap_flag) {
 264             diff = hpet_calculate_diff(t, cur_tick);
 265             qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) +
 266                            (int64_t)ticks_to_ns(diff));
 267             t->wrap_flag = 0;
 268         }
 269     }
 270     update_irq(t);
 271 }
 272
 273 static void hpet_set_timer(HPETTimer *t)
 274 {
 275     uint64_t diff;
 276     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 277     uint64_t cur_tick = hpet_get_ticks();
 278
 279     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 280     t->wrap_flag = 0;
 281     diff = hpet_calculate_diff(t, cur_tick);
 282
 283     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 284      * counter wraps in addition to an interrupt with comparator match.
 285      */
 286     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 287         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 288         if (wrap_diff < (uint32_t)diff) {
 289             diff = wrap_diff;
 290             t->wrap_flag = 1;
 291         }
 292     }
 293     qemu_mod_timer(t->qemu_timer,
 294                    qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 295 }
 296
 297 static void hpet_del_timer(HPETTimer *t)
 298 {
 299     qemu_del_timer(t->qemu_timer);
 300 }
 301
 302 #ifdef HPET_DEBUG
 303 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 304 {
 305     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 306     return 0;
 307 }
 308
 309 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 310 {
 311     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 312     return 0;
 313 }
 314 #endif
 315
 316 static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
 317 {
 318     HPETState *s = opaque;
 319     uint64_t cur_tick, index;
 320
 321     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 322     index = addr;
 323     /*address range of all TN regs*/
 324     if (index >= 0x100 && index <= 0x3ff) {
 325         uint8_t timer_id = (addr - 0x100) / 0x20;
 326         HPETTimer *timer = &s->timer[timer_id];
 327
 328         if (timer_id > HPET_NUM_TIMERS - 1) {
 329             DPRINTF("qemu: timer id out of range\n");
 330             return 0;
 331         }
 332
 333         switch ((addr - 0x100) % 0x20) {
 334         case HPET_TN_CFG:
 335             return timer->config;
 336         case HPET_TN_CFG + 4: // Interrupt capabilities
 337             return timer->config >> 32;
 338         case HPET_TN_CMP: // comparator register
 339             return timer->cmp;
 340         case HPET_TN_CMP + 4:
 341             return timer->cmp >> 32;
 342         case HPET_TN_ROUTE:
 343             return timer->fsb >> 32;
 344         default:
 345             DPRINTF("qemu: invalid hpet_ram_readl\n");
 346             break;
 347         }
 348     } else {
 349         switch (index) {
 350         case HPET_ID:
 351             return s->capability;
 352         case HPET_PERIOD:
 353             return s->capability >> 32;
 354         case HPET_CFG:
 355             return s->config;
 356         case HPET_CFG + 4:
 357             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
 358             return 0;
 359         case HPET_COUNTER:
 360             if (hpet_enabled()) {
 361                 cur_tick = hpet_get_ticks();
 362             } else {
 363                 cur_tick = s->hpet_counter;
 364             }
 365             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 366             return cur_tick;
 367         case HPET_COUNTER + 4:
 368             if (hpet_enabled()) {
 369                 cur_tick = hpet_get_ticks();
 370             } else {
 371                 cur_tick = s->hpet_counter;
 372             }
 373             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 374             return cur_tick >> 32;
 375         case HPET_STATUS:
 376             return s->isr;
 377         default:
 378             DPRINTF("qemu: invalid hpet_ram_readl\n");
 379             break;
 380         }
 381     }
 382     return 0;
 383 }
 384
 385 #ifdef HPET_DEBUG
 386 static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
 387                             uint32_t value)
 388 {
 389     printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
 390            addr, value);
 391 }
 392
 393 static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
 394                             uint32_t value)
 395 {
 396     printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
 397            addr, value);
 398 }
 399 #endif
 400
 401 static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
 402                             uint32_t value)
 403 {
 404     int i;
 405     HPETState *s = opaque;
 406     uint64_t old_val, new_val, val, index;
 407
 408     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 409     index = addr;
 410     old_val = hpet_ram_readl(opaque, addr);
 411     new_val = value;
 412
 413     /*address range of all TN regs*/
 414     if (index >= 0x100 && index <= 0x3ff) {
 415         uint8_t timer_id = (addr - 0x100) / 0x20;
 416         HPETTimer *timer = &s->timer[timer_id];
 417
 418         DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
 419         if (timer_id > HPET_NUM_TIMERS - 1) {
 420             DPRINTF("qemu: timer id out of range\n");
 421             return;
 422         }
 423         switch ((addr - 0x100) % 0x20) {
 424         case HPET_TN_CFG:
 425             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 426             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 427             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 428             if (new_val & HPET_TN_32BIT) {
 429                 timer->cmp = (uint32_t)timer->cmp;
 430                 timer->period = (uint32_t)timer->period;
 431             }
 432             if (new_val & HPET_TN_TYPE_LEVEL) {
 433                 printf("qemu: level-triggered hpet not supported\n");
 434                 exit (-1);
 435             }
 436             break;
 437         case HPET_TN_CFG + 4: // Interrupt capabilities
 438             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 439             break;
 440         case HPET_TN_CMP: // comparator register
 441             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
 442             if (timer->config & HPET_TN_32BIT) {
 443                 new_val = (uint32_t)new_val;
 444             }
 445             if (!timer_is_periodic(timer)
 446                 || (timer->config & HPET_TN_SETVAL)) {
 447                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 448             }
 449             if (timer_is_periodic(timer)) {
 450                 /*
 451                  * FIXME: Clamp period to reasonable min value?
 452                  * Clamp period to reasonable max value
 453                  */
 454                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 455                 timer->period =
 456                     (timer->period & 0xffffffff00000000ULL) | new_val;
 457             }
 458             timer->config &= ~HPET_TN_SETVAL;
 459             if (hpet_enabled()) {
 460                 hpet_set_timer(timer);
 461             }
 462             break;
 463         case HPET_TN_CMP + 4: // comparator register high order
 464             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 465             if (!timer_is_periodic(timer)
 466                 || (timer->config & HPET_TN_SETVAL)) {
 467                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 468             } else {
 469                 /*
 470                  * FIXME: Clamp period to reasonable min value?
 471                  * Clamp period to reasonable max value
 472                  */
 473                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 474                 timer->period =
 475                     (timer->period & 0xffffffffULL) | new_val << 32;
 476                 }
 477                 timer->config &= ~HPET_TN_SETVAL;
 478                 if (hpet_enabled()) {
 479                     hpet_set_timer(timer);
 480                 }
 481                 break;
 482         case HPET_TN_ROUTE + 4:
 483             DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
 484             break;
 485         default:
 486             DPRINTF("qemu: invalid hpet_ram_writel\n");
 487             break;
 488         }
 489         return;
 490     } else {
 491         switch (index) {
 492         case HPET_ID:
 493             return;
 494         case HPET_CFG:
 495             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 496             s->config = (s->config & 0xffffffff00000000ULL) | val;
 497             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 498                 /* Enable main counter and interrupt generation. */
 499                 s->hpet_offset =
 500                     ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 501                 for (i = 0; i < HPET_NUM_TIMERS; i++) {
 502                     if ((&s->timer[i])->cmp != ~0ULL) {
 503                         hpet_set_timer(&s->timer[i]);
 504                     }
 505                 }
 506             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 507                 /* Halt main counter and disable interrupt generation. */
 508                 s->hpet_counter = hpet_get_ticks();
 509                 for (i = 0; i < HPET_NUM_TIMERS; i++) {
 510                     hpet_del_timer(&s->timer[i]);
 511                 }
 512             }
 513             /* i8254 and RTC are disabled when HPET is in legacy mode */
 514             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 515                 hpet_pit_disable();
 516             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 517                 hpet_pit_enable();
 518             }
 519             break;
 520         case HPET_CFG + 4:
 521             DPRINTF("qemu: invalid HPET_CFG+4 write \n");
 522             break;
 523         case HPET_STATUS:
 524             /* FIXME: need to handle level-triggered interrupts */
 525             break;
 526         case HPET_COUNTER:
 527             if (hpet_enabled()) {
 528                 printf("qemu: Writing counter while HPET enabled!\n");
 529             }
 530             s->hpet_counter =
 531                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 532             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 533                     value, s->hpet_counter);
 534             break;
 535         case HPET_COUNTER + 4:
 536             if (hpet_enabled()) {
 537                 printf("qemu: Writing counter while HPET enabled!\n");
 538             }
 539             s->hpet_counter =
 540                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 541             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 542                     value, s->hpet_counter);
 543             break;
 544         default:
 545             DPRINTF("qemu: invalid hpet_ram_writel\n");
 546             break;
 547         }
 548     }
 549 }
 550
 551 static CPUReadMemoryFunc * const hpet_ram_read[] = {
 552 #ifdef HPET_DEBUG
 553     hpet_ram_readb,
 554     hpet_ram_readw,
 555 #else
 556     NULL,
 557     NULL,
 558 #endif
 559     hpet_ram_readl,
 560 };
 561
 562 static CPUWriteMemoryFunc * const hpet_ram_write[] = {
 563 #ifdef HPET_DEBUG
 564     hpet_ram_writeb,
 565     hpet_ram_writew,
 566 #else
 567     NULL,
 568     NULL,
 569 #endif
 570     hpet_ram_writel,
 571 };
 572
 573 static void hpet_reset(void *opaque)
 574 {
 575     HPETState *s = opaque;
 576     int i;
 577     static int count = 0;
 578
 579     for (i = 0; i < HPET_NUM_TIMERS; i++) {
 580         HPETTimer *timer = &s->timer[i];
 581
 582         hpet_del_timer(timer);
 583         timer->tn = i;
 584         timer->cmp = ~0ULL;
 585         timer->config =  HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 586         /* advertise availability of ioapic inti2 */
 587         timer->config |=  0x00000004ULL << 32;
 588         timer->state = s;
 589         timer->period = 0ULL;
 590         timer->wrap_flag = 0;
 591     }
 592
 593     s->hpet_counter = 0ULL;
 594     s->hpet_offset = 0ULL;
 595     /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
 596     s->capability = 0x8086a201ULL;
 597     s->capability |= ((HPET_CLK_PERIOD) << 32);
 598     s->config = 0ULL;
 599     if (count > 0) {
 600         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 601          * because hpet is taking over for pit here. On subsequent invocations,
 602          * hpet_reset is called due to system reset. At this point control must
 603          * be returned to pit until SW reenables hpet.
 604          */
 605         hpet_pit_enable();
 606     }
 607     count = 1;
 608 }
 609
 610
 611 void hpet_init(qemu_irq *irq)
 612 {
 613     int i, iomemtype;
 614     HPETTimer *timer;
 615     HPETState *s;
 616
 617     DPRINTF ("hpet_init\n");
 618
 619     s = qemu_mallocz(sizeof(HPETState));
 620     hpet_statep = s;
 621     s->irqs = irq;
 622     for (i = 0; i < HPET_NUM_TIMERS; i++) {
 623         timer = &s->timer[i];
 624         timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
 625     }
 626     vmstate_register(-1, &vmstate_hpet, s);
 627     qemu_register_reset(hpet_reset, s);
 628     /* HPET Area */
 629     iomemtype = cpu_register_io_memory(hpet_ram_read,
 630                                        hpet_ram_write, s);
 631     cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
 632 }