hw/msix.c

   1 /*
   2  * MSI-X device support
   3  *
   4  * This module includes support for MSI-X in pci devices.
   5  *
   6  * Author: Michael S. Tsirkin <mst@redhat.com>
   7  *
   8  *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2.  See
  11  * the COPYING file in the top-level directory.
  12  */
  13
  14 #include "hw.h"
  15 #include "msix.h"
  16 #include "pci.h"
  17 #include "kvm.h"
  18
  19 /* Declaration from linux/pci_regs.h */
  20 #define  PCI_CAP_ID_MSIX 0x11 /* MSI-X */
  21 #define  PCI_MSIX_FLAGS 2     /* Table at lower 11 bits */
  22 #define  PCI_MSIX_FLAGS_QSIZE   0x7FF
  23 #define  PCI_MSIX_FLAGS_ENABLE  (1 << 15)
  24 #define  PCI_MSIX_FLAGS_MASKALL (1 << 14)
  25 #define  PCI_MSIX_FLAGS_BIRMASK (7 << 0)
  26
  27 /* MSI-X capability structure */
  28 #define MSIX_TABLE_OFFSET 4
  29 #define MSIX_PBA_OFFSET 8
  30 #define MSIX_CAP_LENGTH 12
  31
  32 /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
  33 #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
  34 #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
  35 #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
  36
  37 /* MSI-X table format */
  38 #define MSIX_MSG_ADDR 0
  39 #define MSIX_MSG_UPPER_ADDR 4
  40 #define MSIX_MSG_DATA 8
  41 #define MSIX_VECTOR_CTRL 12
  42 #define MSIX_ENTRY_SIZE 16
  43 #define MSIX_VECTOR_MASK 0x1
  44
  45 /* How much space does an MSIX table need. */
  46 /* The spec requires giving the table structure
  47  * a 4K aligned region all by itself. */
  48 #define MSIX_PAGE_SIZE 0x1000
  49 /* Reserve second half of the page for pending bits */
  50 #define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
  51 #define MSIX_MAX_ENTRIES 32
  52
  53
  54 #ifdef MSIX_DEBUG
  55 #define DEBUG(fmt, ...)                                       \
  56     do {                                                      \
  57       fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__);    \
  58     } while (0)
  59 #else
  60 #define DEBUG(fmt, ...) do { } while(0)
  61 #endif
  62
  63 /* Flag for interrupt controller to declare MSI-X support */
  64 int msix_supported;
  65
  66 #ifdef CONFIG_KVM
  67 /* KVM specific MSIX helpers */
  68 static void kvm_msix_free(PCIDevice *dev)
  69 {
  70     int vector, changed = 0;
  71     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
  72         if (dev->msix_entry_used[vector]) {
  73             kvm_del_routing_entry(kvm_context, &dev->msix_irq_entries[vector]);
  74             changed = 1;
  75         }
  76     }
  77     if (changed) {
  78         kvm_commit_irq_routes(kvm_context);
  79     }
  80 }
  81
  82 static void kvm_msix_routing_entry(PCIDevice *dev, unsigned vector,
  83                                    struct kvm_irq_routing_entry *entry)
  84 {
  85     uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE;
  86     entry->type = KVM_IRQ_ROUTING_MSI;
  87     entry->flags = 0;
  88     entry->u.msi.address_lo = pci_get_long(table_entry + MSIX_MSG_ADDR);
  89     entry->u.msi.address_hi = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
  90     entry->u.msi.data = pci_get_long(table_entry + MSIX_MSG_DATA);
  91 }
  92
  93 static void kvm_msix_update(PCIDevice *dev, int vector,
  94                             int was_masked, int is_masked)
  95 {
  96     struct kvm_irq_routing_entry e = {}, *entry;
  97     int mask_cleared = was_masked && !is_masked;
  98     /* It is only legal to change an entry when it is masked. Therefore, it is
  99      * enough to update the routing in kernel when mask is being cleared. */
 100     if (!mask_cleared) {
 101         return;
 102     }
 103     if (!dev->msix_entry_used[vector]) {
 104         return;
 105     }
 106     entry = dev->msix_irq_entries + vector;
 107     e.gsi = entry->gsi;
 108     kvm_msix_routing_entry(dev, vector, &e);
 109     if (memcmp(&entry->u.msi, &e.u.msi, sizeof entry->u.msi)) {
 110         int r;
 111         r = kvm_update_routing_entry(kvm_context, entry, &e);
 112         if (r) {
 113             fprintf(stderr, "%s: kvm_update_routing_entry failed: %s\n", __func__,
 114                     strerror(-r));
 115             exit(1);
 116         }
 117         memcpy(&entry->u.msi, &e.u.msi, sizeof entry->u.msi);
 118         r = kvm_commit_irq_routes(kvm_context);
 119         if (r) {
 120             fprintf(stderr, "%s: kvm_commit_irq_routes failed: %s\n", __func__,
 121                     strerror(-r));
 122             exit(1);
 123         }
 124     }
 125 }
 126
 127 static int kvm_msix_add(PCIDevice *dev, unsigned vector)
 128 {
 129     struct kvm_irq_routing_entry *entry = dev->msix_irq_entries + vector;
 130     int r;
 131
 132     if (!kvm_has_gsi_routing(kvm_context)) {
 133         fprintf(stderr, "Warning: no MSI-X support found. "
 134                 "At least kernel 2.6.30 is required for MSI-X support.\n"
 135                );
 136         return -EOPNOTSUPP;
 137     }
 138
 139     r = kvm_get_irq_route_gsi(kvm_context);
 140     if (r < 0) {
 141         fprintf(stderr, "%s: kvm_get_irq_route_gsi failed: %s\n", __func__, strerror(-r));
 142         return r;
 143     }
 144     entry->gsi = r;
 145     kvm_msix_routing_entry(dev, vector, entry);
 146     r = kvm_add_routing_entry(kvm_context, entry);
 147     if (r < 0) {
 148         fprintf(stderr, "%s: kvm_add_routing_entry failed: %s\n", __func__, strerror(-r));
 149         return r;
 150     }
 151
 152     r = kvm_commit_irq_routes(kvm_context);
 153     if (r < 0) {
 154         fprintf(stderr, "%s: kvm_commit_irq_routes failed: %s\n", __func__, strerror(-r));
 155         return r;
 156     }
 157     return 0;
 158 }
 159
 160 static void kvm_msix_del(PCIDevice *dev, unsigned vector)
 161 {
 162     if (dev->msix_entry_used[vector]) {
 163         return;
 164     }
 165     kvm_del_routing_entry(kvm_context, &dev->msix_irq_entries[vector]);
 166     kvm_commit_irq_routes(kvm_context);
 167 }
 168 #else
 169
 170 static void kvm_msix_free(PCIDevice *dev) {}
 171 static void kvm_msix_update(PCIDevice *dev, int vector,
 172                             int was_masked, int is_masked) {}
 173 static int kvm_msix_add(PCIDevice *dev, unsigned vector) { return -1; }
 174 static void kvm_msix_del(PCIDevice *dev, unsigned vector) {}
 175 #endif
 176
 177 /* Add MSI-X capability to the config space for the device. */
 178 /* Given a bar and its size, add MSI-X table on top of it
 179  * and fill MSI-X capability in the config space.
 180  * Original bar size must be a power of 2 or 0.
 181  * New bar size is returned. */
 182 static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
 183                            unsigned bar_nr, unsigned bar_size)
 184 {
 185     int config_offset;
 186     uint8_t *config;
 187     uint32_t new_size;
 188
 189     if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
 190         return -EINVAL;
 191     if (bar_size > 0x80000000)
 192         return -ENOSPC;
 193
 194     /* Add space for MSI-X structures */
 195     if (!bar_size) {
 196         new_size = MSIX_PAGE_SIZE;
 197     } else if (bar_size < MSIX_PAGE_SIZE) {
 198         bar_size = MSIX_PAGE_SIZE;
 199         new_size = MSIX_PAGE_SIZE * 2;
 200     } else {
 201         new_size = bar_size * 2;
 202     }
 203
 204     pdev->msix_bar_size = new_size;
 205     config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
 206     if (config_offset < 0)
 207         return config_offset;
 208     config = pdev->config + config_offset;
 209
 210     pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
 211     /* Table on top of BAR */
 212     pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr);
 213     /* Pending bits on top of that */
 214     pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) |
 215                  bar_nr);
 216     pdev->msix_cap = config_offset;
 217     /* Make flags bit writeable. */
 218     pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
 219             MSIX_MASKALL_MASK;
 220     return 0;
 221 }
 222
 223 static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
 224 {
 225     PCIDevice *dev = opaque;
 226     unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
 227     void *page = dev->msix_table_page;
 228
 229     return pci_get_long(page + offset);
 230 }
 231
 232 static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
 233 {
 234     fprintf(stderr, "MSI-X: only dword read is allowed!\n");
 235     return 0;
 236 }
 237
 238 static uint8_t msix_pending_mask(int vector)
 239 {
 240     return 1 << (vector % 8);
 241 }
 242
 243 static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
 244 {
 245     return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
 246 }
 247
 248 static int msix_is_pending(PCIDevice *dev, int vector)
 249 {
 250     return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
 251 }
 252
 253 static void msix_set_pending(PCIDevice *dev, int vector)
 254 {
 255     *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
 256 }
 257
 258 static void msix_clr_pending(PCIDevice *dev, int vector)
 259 {
 260     *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
 261 }
 262
 263 static int msix_function_masked(PCIDevice *dev)
 264 {
 265     return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
 266 }
 267
 268 static int msix_is_masked(PCIDevice *dev, int vector)
 269 {
 270     unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
 271     return msix_function_masked(dev) ||
 272            dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
 273 }
 274
 275 static void msix_handle_mask_update(PCIDevice *dev, int vector)
 276 {
 277     if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
 278         msix_clr_pending(dev, vector);
 279         msix_notify(dev, vector);
 280     }
 281 }
 282
 283 /* Handle MSI-X capability config write. */
 284 void msix_write_config(PCIDevice *dev, uint32_t addr,
 285                        uint32_t val, int len)
 286 {
 287     unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
 288     int vector;
 289
 290     if (!range_covers_byte(addr, len, enable_pos)) {
 291         return;
 292     }
 293
 294     if (!msix_enabled(dev)) {
 295         return;
 296     }
 297
 298     qemu_set_irq(dev->irq[0], 0);
 299
 300     if (msix_function_masked(dev)) {
 301         return;
 302     }
 303
 304     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 305         msix_handle_mask_update(dev, vector);
 306     }
 307 }
 308
 309 static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
 310                              uint32_t val)
 311 {
 312     PCIDevice *dev = opaque;
 313     unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
 314     int vector = offset / MSIX_ENTRY_SIZE;
 315     int was_masked = msix_is_masked(dev, vector);
 316     pci_set_long(dev->msix_table_page + offset, val);
 317     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 318         kvm_msix_update(dev, vector, was_masked, msix_is_masked(dev, vector));
 319     }
 320     if (was_masked != msix_is_masked(dev, vector) &&
 321         dev->msix_mask_notifier && dev->msix_mask_notifier_opaque[vector]) {
 322         int r = dev->msix_mask_notifier(dev, vector,
 323                                         dev->msix_mask_notifier_opaque[vector],
 324                                         msix_is_masked(dev, vector));
 325         assert(r >= 0);
 326     }
 327     msix_handle_mask_update(dev, vector);
 328 }
 329
 330 static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
 331                                       uint32_t val)
 332 {
 333     fprintf(stderr, "MSI-X: only dword write is allowed!\n");
 334 }
 335
 336 static CPUWriteMemoryFunc * const msix_mmio_write[] = {
 337     msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
 338 };
 339
 340 static CPUReadMemoryFunc * const msix_mmio_read[] = {
 341     msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
 342 };
 343
 344 /* Should be called from device's map method. */
 345 void msix_mmio_map(PCIDevice *d, int region_num,
 346                    pcibus_t addr, pcibus_t size, int type)
 347 {
 348     uint8_t *config = d->config + d->msix_cap;
 349     uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
 350     uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
 351     /* TODO: for assigned devices, we'll want to make it possible to map
 352      * pending bits separately in case they are in a separate bar. */
 353     int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
 354
 355     if (table_bir != region_num)
 356         return;
 357     if (size <= offset)
 358         return;
 359     cpu_register_physical_memory(addr + offset, size - offset,
 360                                  d->msix_mmio_index);
 361 }
 362
 363 static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
 364 {
 365     int vector, r;
 366     for (vector = 0; vector < nentries; ++vector) {
 367         unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
 368         int was_masked = msix_is_masked(dev, vector);
 369         dev->msix_table_page[offset] |= MSIX_VECTOR_MASK;
 370         if (was_masked != msix_is_masked(dev, vector) &&
 371             dev->msix_mask_notifier && dev->msix_mask_notifier_opaque[vector]) {
 372             r = dev->msix_mask_notifier(dev, vector,
 373                                         dev->msix_mask_notifier_opaque[vector],
 374                                         msix_is_masked(dev, vector));
 375             assert(r >= 0);
 376         }
 377     }
 378 }
 379
 380 /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 381  * modified, it should be retrieved with msix_bar_size. */
 382 int msix_init(struct PCIDevice *dev, unsigned short nentries,
 383               unsigned bar_nr, unsigned bar_size)
 384 {
 385     int ret;
 386     /* Nothing to do if MSI is not supported by interrupt controller */
 387     if (!msix_supported)
 388         return -ENOTSUP;
 389
 390     if (nentries > MSIX_MAX_ENTRIES)
 391         return -EINVAL;
 392
 393 #ifdef KVM_CAP_IRQCHIP
 394     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 395         dev->msix_irq_entries = qemu_malloc(nentries *
 396                                             sizeof *dev->msix_irq_entries);
 397     }
 398 #endif
 399     dev->msix_mask_notifier_opaque =
 400         qemu_mallocz(nentries * sizeof *dev->msix_mask_notifier_opaque);
 401     dev->msix_mask_notifier = NULL;
 402     dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
 403                                         sizeof *dev->msix_entry_used);
 404
 405     dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
 406     msix_mask_all(dev, nentries);
 407
 408     dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
 409                                                   msix_mmio_write, dev);
 410     if (dev->msix_mmio_index == -1) {
 411         ret = -EBUSY;
 412         goto err_index;
 413     }
 414
 415     dev->msix_entries_nr = nentries;
 416     ret = msix_add_config(dev, nentries, bar_nr, bar_size);
 417     if (ret)
 418         goto err_config;
 419
 420     dev->cap_present |= QEMU_PCI_CAP_MSIX;
 421     return 0;
 422
 423 err_config:
 424     dev->msix_entries_nr = 0;
 425     cpu_unregister_io_memory(dev->msix_mmio_index);
 426 err_index:
 427     qemu_free(dev->msix_table_page);
 428     dev->msix_table_page = NULL;
 429     qemu_free(dev->msix_entry_used);
 430     dev->msix_entry_used = NULL;
 431     return ret;
 432 }
 433
 434 static void msix_free_irq_entries(PCIDevice *dev)
 435 {
 436     int vector;
 437
 438     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 439         kvm_msix_free(dev);
 440     }
 441
 442     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 443         dev->msix_entry_used[vector] = 0;
 444         msix_clr_pending(dev, vector);
 445     }
 446 }
 447
 448 /* Clean up resources for the device. */
 449 int msix_uninit(PCIDevice *dev)
 450 {
 451     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 452         return 0;
 453     pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
 454     dev->msix_cap = 0;
 455     msix_free_irq_entries(dev);
 456     dev->msix_entries_nr = 0;
 457     cpu_unregister_io_memory(dev->msix_mmio_index);
 458     qemu_free(dev->msix_table_page);
 459     dev->msix_table_page = NULL;
 460     qemu_free(dev->msix_entry_used);
 461     dev->msix_entry_used = NULL;
 462     qemu_free(dev->msix_irq_entries);
 463     dev->msix_irq_entries = NULL;
 464     qemu_free(dev->msix_mask_notifier_opaque);
 465     dev->msix_mask_notifier_opaque = NULL;
 466     dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
 467     return 0;
 468 }
 469
 470 void msix_save(PCIDevice *dev, QEMUFile *f)
 471 {
 472     unsigned n = dev->msix_entries_nr;
 473
 474     if (!msix_supported) {
 475         return;
 476     }
 477
 478     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 479         return;
 480     }
 481     qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
 482     qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
 483 }
 484
 485 /* Should be called after restoring the config space. */
 486 void msix_load(PCIDevice *dev, QEMUFile *f)
 487 {
 488     unsigned n = dev->msix_entries_nr;
 489
 490     if (!msix_supported)
 491         return;
 492
 493     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 494         return;
 495     }
 496
 497     msix_free_irq_entries(dev);
 498     qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
 499     qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
 500 }
 501
 502 /* Does device support MSI-X? */
 503 int msix_present(PCIDevice *dev)
 504 {
 505     return dev->cap_present & QEMU_PCI_CAP_MSIX;
 506 }
 507
 508 /* Is MSI-X enabled? */
 509 int msix_enabled(PCIDevice *dev)
 510 {
 511     return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
 512         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
 513          MSIX_ENABLE_MASK);
 514 }
 515
 516 /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
 517 uint32_t msix_bar_size(PCIDevice *dev)
 518 {
 519     return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
 520         dev->msix_bar_size : 0;
 521 }
 522
 523 /* Send an MSI-X message */
 524 void msix_notify(PCIDevice *dev, unsigned vector)
 525 {
 526     uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE;
 527     uint64_t address;
 528     uint32_t data;
 529
 530     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 531         return;
 532     if (msix_is_masked(dev, vector)) {
 533         msix_set_pending(dev, vector);
 534         return;
 535     }
 536
 537 #ifdef KVM_CAP_IRQCHIP
 538     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 539         kvm_set_irq(dev->msix_irq_entries[vector].gsi, 1, NULL);
 540         return;
 541     }
 542 #endif
 543
 544     address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
 545     address = (address << 32) | pci_get_long(table_entry + MSIX_MSG_ADDR);
 546     data = pci_get_long(table_entry + MSIX_MSG_DATA);
 547     stl_phys(address, data);
 548 }
 549
 550 void msix_reset(PCIDevice *dev)
 551 {
 552     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 553         return;
 554     msix_free_irq_entries(dev);
 555     dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
 556             ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
 557     memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
 558     msix_mask_all(dev, dev->msix_entries_nr);
 559 }
 560
 561 /* PCI spec suggests that devices make it possible for software to configure
 562  * less vectors than supported by the device, but does not specify a standard
 563  * mechanism for devices to do so.
 564  *
 565  * We support this by asking devices to declare vectors software is going to
 566  * actually use, and checking this on the notification path. Devices that
 567  * don't want to follow the spec suggestion can declare all vectors as used. */
 568
 569 /* Mark vector as used. */
 570 int msix_vector_use(PCIDevice *dev, unsigned vector)
 571 {
 572     int ret;
 573     if (vector >= dev->msix_entries_nr)
 574         return -EINVAL;
 575     if (dev->msix_entry_used[vector]) {
 576         return 0;
 577     }
 578     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 579         ret = kvm_msix_add(dev, vector);
 580         if (ret) {
 581             return ret;
 582         }
 583     }
 584     ++dev->msix_entry_used[vector];
 585     return 0;
 586 }
 587
 588 /* Mark vector as unused. */
 589 void msix_vector_unuse(PCIDevice *dev, unsigned vector)
 590 {
 591     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
 592         return;
 593     }
 594     if (--dev->msix_entry_used[vector]) {
 595         return;
 596     }
 597     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 598         kvm_msix_del(dev, vector);
 599     }
 600     msix_clr_pending(dev, vector);
 601 }
 602
 603 void msix_unuse_all_vectors(PCIDevice *dev)
 604 {
 605     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 606         return;
 607     msix_free_irq_entries(dev);
 608 }
 609
 610 int msix_set_mask_notifier(PCIDevice *dev, unsigned vector, void *opaque)
 611 {
 612     int r;
 613     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 614         return 0;
 615
 616     assert(dev->msix_mask_notifier);
 617     assert(opaque);
 618     assert(!dev->msix_mask_notifier_opaque[vector]);
 619
 620     if (msix_is_masked(dev, vector)) {
 621         return 0;
 622     }
 623     r = dev->msix_mask_notifier(dev, vector, opaque,
 624                                 msix_is_masked(dev, vector));
 625     if (r < 0) {
 626         return r;
 627     }
 628     dev->msix_mask_notifier_opaque[vector] = opaque;
 629     return r;
 630 }
 631
 632 int msix_unset_mask_notifier(PCIDevice *dev, unsigned vector)
 633 {
 634     int r = 0;
 635     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 636         return 0;
 637
 638     assert(dev->msix_mask_notifier);
 639     assert(dev->msix_mask_notifier_opaque[vector]);
 640
 641     if (msix_is_masked(dev, vector)) {
 642         return 0;
 643     }
 644     r = dev->msix_mask_notifier(dev, vector,
 645                                 dev->msix_mask_notifier_opaque[vector],
 646                                 msix_is_masked(dev, vector));
 647     if (r < 0) {
 648         return r;
 649     }
 650     dev->msix_mask_notifier_opaque[vector] = NULL;
 651     return r;
 652 }