hw/vmware_vga.c

   1 /*
   2  * QEMU VMware-SVGA "chipset".
   3  *
   4  * Copyright (c) 2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "console.h"
  26 #include "pci.h"
  27
  28 #define VERBOSE
  29 #define EMBED_STDVGA
  30 #undef DIRECT_VRAM
  31 #define HW_RECT_ACCEL
  32 #define HW_FILL_ACCEL
  33 #define HW_MOUSE_ACCEL
  34
  35 #ifdef EMBED_STDVGA
  36 # include "vga_int.h"
  37 #endif
  38
  39 struct vmsvga_state_s {
  40 #ifdef EMBED_STDVGA
  41     VGA_STATE_COMMON
  42 #endif
  43
  44     int width;
  45     int height;
  46     int invalidated;
  47     int depth;
  48     int bypp;
  49     int enable;
  50     int config;
  51     struct {
  52         int id;
  53         int x;
  54         int y;
  55         int on;
  56     } cursor;
  57
  58 #ifndef EMBED_STDVGA
  59     DisplayState *ds;
  60     int vram_size;
  61 #endif
  62     uint8_t *vram;
  63     uint32_t vram_addr;
  64     int iomemtype;
  65
  66     int index;
  67     int scratch_size;
  68     uint32_t *scratch;
  69     int new_width;
  70     int new_height;
  71     uint32_t guest;
  72     uint32_t svgaid;
  73     uint32_t wred;
  74     uint32_t wgreen;
  75     uint32_t wblue;
  76     int syncing;
  77     int fb_size;
  78
  79     union {
  80         uint32_t *fifo;
  81         struct __attribute__((__packed__)) {
  82             uint32_t min;
  83             uint32_t max;
  84             uint32_t next_cmd;
  85             uint32_t stop;
  86             /* Add registers here when adding capabilities.  */
  87             uint32_t fifo[0];
  88         } *cmd;
  89     };
  90
  91 #define REDRAW_FIFO_LEN 512
  92     struct vmsvga_rect_s {
  93         int x, y, w, h;
  94     } redraw_fifo[REDRAW_FIFO_LEN];
  95     int redraw_fifo_first, redraw_fifo_last;
  96 };
  97
  98 struct pci_vmsvga_state_s {
  99     PCIDevice card;
 100     struct vmsvga_state_s chip;
 101 };
 102
 103 #define SVGA_MAGIC              0x900000UL
 104 #define SVGA_MAKE_ID(ver)       (SVGA_MAGIC << 8 | (ver))
 105 #define SVGA_ID_0               SVGA_MAKE_ID(0)
 106 #define SVGA_ID_1               SVGA_MAKE_ID(1)
 107 #define SVGA_ID_2               SVGA_MAKE_ID(2)
 108
 109 #define SVGA_LEGACY_BASE_PORT   0x4560
 110 #define SVGA_INDEX_PORT         0x0
 111 #define SVGA_VALUE_PORT         0x1
 112 #define SVGA_BIOS_PORT          0x2
 113
 114 #define SVGA_VERSION_2
 115
 116 #ifdef SVGA_VERSION_2
 117 # define SVGA_ID                SVGA_ID_2
 118 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 119 # define SVGA_IO_MUL            1
 120 # define SVGA_FIFO_SIZE         0x10000
 121 # define SVGA_MEM_BASE          0xe0000000
 122 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA2
 123 #else
 124 # define SVGA_ID                SVGA_ID_1
 125 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 126 # define SVGA_IO_MUL            4
 127 # define SVGA_FIFO_SIZE         0x10000
 128 # define SVGA_MEM_BASE          0xe0000000
 129 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA
 130 #endif
 131
 132 enum {
 133     /* ID 0, 1 and 2 registers */
 134     SVGA_REG_ID = 0,
 135     SVGA_REG_ENABLE = 1,
 136     SVGA_REG_WIDTH = 2,
 137     SVGA_REG_HEIGHT = 3,
 138     SVGA_REG_MAX_WIDTH = 4,
 139     SVGA_REG_MAX_HEIGHT = 5,
 140     SVGA_REG_DEPTH = 6,
 141     SVGA_REG_BITS_PER_PIXEL = 7,        /* Current bpp in the guest */
 142     SVGA_REG_PSEUDOCOLOR = 8,
 143     SVGA_REG_RED_MASK = 9,
 144     SVGA_REG_GREEN_MASK = 10,
 145     SVGA_REG_BLUE_MASK = 11,
 146     SVGA_REG_BYTES_PER_LINE = 12,
 147     SVGA_REG_FB_START = 13,
 148     SVGA_REG_FB_OFFSET = 14,
 149     SVGA_REG_VRAM_SIZE = 15,
 150     SVGA_REG_FB_SIZE = 16,
 151
 152     /* ID 1 and 2 registers */
 153     SVGA_REG_CAPABILITIES = 17,
 154     SVGA_REG_MEM_START = 18,            /* Memory for command FIFO */
 155     SVGA_REG_MEM_SIZE = 19,
 156     SVGA_REG_CONFIG_DONE = 20,          /* Set when memory area configured */
 157     SVGA_REG_SYNC = 21,                 /* Write to force synchronization */
 158     SVGA_REG_BUSY = 22,                 /* Read to check if sync is done */
 159     SVGA_REG_GUEST_ID = 23,             /* Set guest OS identifier */
 160     SVGA_REG_CURSOR_ID = 24,            /* ID of cursor */
 161     SVGA_REG_CURSOR_X = 25,             /* Set cursor X position */
 162     SVGA_REG_CURSOR_Y = 26,             /* Set cursor Y position */
 163     SVGA_REG_CURSOR_ON = 27,            /* Turn cursor on/off */
 164     SVGA_REG_HOST_BITS_PER_PIXEL = 28,  /* Current bpp in the host */
 165     SVGA_REG_SCRATCH_SIZE = 29,         /* Number of scratch registers */
 166     SVGA_REG_MEM_REGS = 30,             /* Number of FIFO registers */
 167     SVGA_REG_NUM_DISPLAYS = 31,         /* Number of guest displays */
 168     SVGA_REG_PITCHLOCK = 32,            /* Fixed pitch for all modes */
 169
 170     SVGA_PALETTE_BASE = 1024,           /* Base of SVGA color map */
 171     SVGA_PALETTE_END  = SVGA_PALETTE_BASE + 767,
 172     SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
 173 };
 174
 175 #define SVGA_CAP_NONE                   0
 176 #define SVGA_CAP_RECT_FILL              (1 << 0)
 177 #define SVGA_CAP_RECT_COPY              (1 << 1)
 178 #define SVGA_CAP_RECT_PAT_FILL          (1 << 2)
 179 #define SVGA_CAP_LEGACY_OFFSCREEN       (1 << 3)
 180 #define SVGA_CAP_RASTER_OP              (1 << 4)
 181 #define SVGA_CAP_CURSOR                 (1 << 5)
 182 #define SVGA_CAP_CURSOR_BYPASS          (1 << 6)
 183 #define SVGA_CAP_CURSOR_BYPASS_2        (1 << 7)
 184 #define SVGA_CAP_8BIT_EMULATION         (1 << 8)
 185 #define SVGA_CAP_ALPHA_CURSOR           (1 << 9)
 186 #define SVGA_CAP_GLYPH                  (1 << 10)
 187 #define SVGA_CAP_GLYPH_CLIPPING         (1 << 11)
 188 #define SVGA_CAP_OFFSCREEN_1            (1 << 12)
 189 #define SVGA_CAP_ALPHA_BLEND            (1 << 13)
 190 #define SVGA_CAP_3D                     (1 << 14)
 191 #define SVGA_CAP_EXTENDED_FIFO          (1 << 15)
 192 #define SVGA_CAP_MULTIMON               (1 << 16)
 193 #define SVGA_CAP_PITCHLOCK              (1 << 17)
 194
 195 /*
 196  * FIFO offsets (seen as an array of 32-bit words)
 197  */
 198 enum {
 199     /*
 200      * The original defined FIFO offsets
 201      */
 202     SVGA_FIFO_MIN = 0,
 203     SVGA_FIFO_MAX,      /* The distance from MIN to MAX must be at least 10K */
 204     SVGA_FIFO_NEXT_CMD,
 205     SVGA_FIFO_STOP,
 206
 207     /*
 208      * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
 209      */
 210     SVGA_FIFO_CAPABILITIES = 4,
 211     SVGA_FIFO_FLAGS,
 212     SVGA_FIFO_FENCE,
 213     SVGA_FIFO_3D_HWVERSION,
 214     SVGA_FIFO_PITCHLOCK,
 215 };
 216
 217 #define SVGA_FIFO_CAP_NONE              0
 218 #define SVGA_FIFO_CAP_FENCE             (1 << 0)
 219 #define SVGA_FIFO_CAP_ACCELFRONT        (1 << 1)
 220 #define SVGA_FIFO_CAP_PITCHLOCK         (1 << 2)
 221
 222 #define SVGA_FIFO_FLAG_NONE             0
 223 #define SVGA_FIFO_FLAG_ACCELFRONT       (1 << 0)
 224
 225 /* These values can probably be changed arbitrarily.  */
 226 #define SVGA_SCRATCH_SIZE               0x8000
 227 #define SVGA_MAX_WIDTH                  2360
 228 #define SVGA_MAX_HEIGHT                 1770
 229
 230 #ifdef VERBOSE
 231 # define GUEST_OS_BASE          0x5001
 232 static const char *vmsvga_guest_id[] = {
 233     [0x00 ... 0x15] = "an unknown OS",
 234     [0x00] = "Dos",
 235     [0x01] = "Windows 3.1",
 236     [0x02] = "Windows 95",
 237     [0x03] = "Windows 98",
 238     [0x04] = "Windows ME",
 239     [0x05] = "Windows NT",
 240     [0x06] = "Windows 2000",
 241     [0x07] = "Linux",
 242     [0x08] = "OS/2",
 243     [0x0a] = "BSD",
 244     [0x0b] = "Whistler",
 245     [0x15] = "Windows 2003",
 246 };
 247 #endif
 248
 249 enum {
 250     SVGA_CMD_INVALID_CMD = 0,
 251     SVGA_CMD_UPDATE = 1,
 252     SVGA_CMD_RECT_FILL = 2,
 253     SVGA_CMD_RECT_COPY = 3,
 254     SVGA_CMD_DEFINE_BITMAP = 4,
 255     SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
 256     SVGA_CMD_DEFINE_PIXMAP = 6,
 257     SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
 258     SVGA_CMD_RECT_BITMAP_FILL = 8,
 259     SVGA_CMD_RECT_PIXMAP_FILL = 9,
 260     SVGA_CMD_RECT_BITMAP_COPY = 10,
 261     SVGA_CMD_RECT_PIXMAP_COPY = 11,
 262     SVGA_CMD_FREE_OBJECT = 12,
 263     SVGA_CMD_RECT_ROP_FILL = 13,
 264     SVGA_CMD_RECT_ROP_COPY = 14,
 265     SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
 266     SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
 267     SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
 268     SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
 269     SVGA_CMD_DEFINE_CURSOR = 19,
 270     SVGA_CMD_DISPLAY_CURSOR = 20,
 271     SVGA_CMD_MOVE_CURSOR = 21,
 272     SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
 273     SVGA_CMD_DRAW_GLYPH = 23,
 274     SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
 275     SVGA_CMD_UPDATE_VERBOSE = 25,
 276     SVGA_CMD_SURFACE_FILL = 26,
 277     SVGA_CMD_SURFACE_COPY = 27,
 278     SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
 279     SVGA_CMD_FRONT_ROP_FILL = 29,
 280     SVGA_CMD_FENCE = 30,
 281 };
 282
 283 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
 284 enum {
 285     SVGA_CURSOR_ON_HIDE = 0,
 286     SVGA_CURSOR_ON_SHOW = 1,
 287     SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
 288     SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
 289 };
 290
 291 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
 292                 int x, int y, int w, int h)
 293 {
 294 #ifndef DIRECT_VRAM
 295     int line = h;
 296     int bypl = s->bypp * s->width;
 297     int width = s->bypp * w;
 298     int start = s->bypp * x + bypl * y;
 299     uint8_t *src = s->vram + start;
 300     uint8_t *dst = s->ds->data + start;
 301
 302     for (; line > 0; line --, src += bypl, dst += bypl)
 303         memcpy(dst, src, width);
 304 #endif
 305
 306     dpy_update(s->ds, x, y, w, h);
 307 }
 308
 309 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
 310 {
 311 #ifndef DIRECT_VRAM
 312     memcpy(s->ds->data, s->vram, s->bypp * s->width * s->height);
 313 #endif
 314
 315     dpy_update(s->ds, 0, 0, s->width, s->height);
 316 }
 317
 318 #ifdef DIRECT_VRAM
 319 # define vmsvga_update_rect_delayed     vmsvga_update_rect
 320 #else
 321 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
 322                 int x, int y, int w, int h)
 323 {
 324     struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
 325     s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
 326     rect->x = x;
 327     rect->y = y;
 328     rect->w = w;
 329     rect->h = h;
 330 }
 331 #endif
 332
 333 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
 334 {
 335     struct vmsvga_rect_s *rect;
 336     if (s->invalidated) {
 337         s->redraw_fifo_first = s->redraw_fifo_last;
 338         return;
 339     }
 340     /* Overlapping region updates can be optimised out here - if someone
 341      * knows a smart algorithm to do that, please share.  */
 342     while (s->redraw_fifo_first != s->redraw_fifo_last) {
 343         rect = &s->redraw_fifo[s->redraw_fifo_first ++];
 344         s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
 345         vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
 346     }
 347 }
 348
 349 #ifdef HW_RECT_ACCEL
 350 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
 351                 int x0, int y0, int x1, int y1, int w, int h)
 352 {
 353 # ifdef DIRECT_VRAM
 354     uint8_t *vram = s->ds->data;
 355 # else
 356     uint8_t *vram = s->vram;
 357 # endif
 358     int bypl = s->bypp * s->width;
 359     int width = s->bypp * w;
 360     int line = h;
 361     uint8_t *ptr[2];
 362
 363 # ifdef DIRECT_VRAM
 364     if (s->ds->dpy_copy)
 365         s->ds->dpy_copy(s->ds, x0, y0, x1, y1, w, h);
 366     else
 367 # endif
 368     {
 369         if (y1 > y0) {
 370             ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
 371             ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
 372             for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
 373                 memmove(ptr[1], ptr[0], width);
 374         } else {
 375             ptr[0] = vram + s->bypp * x0 + bypl * y0;
 376             ptr[1] = vram + s->bypp * x1 + bypl * y1;
 377             for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
 378                 memmove(ptr[1], ptr[0], width);
 379         }
 380     }
 381
 382     vmsvga_update_rect_delayed(s, x1, y1, w, h);
 383 }
 384 #endif
 385
 386 #ifdef HW_FILL_ACCEL
 387 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
 388                 uint32_t c, int x, int y, int w, int h)
 389 {
 390 # ifdef DIRECT_VRAM
 391     uint8_t *vram = s->ds->data;
 392 # else
 393     uint8_t *vram = s->vram;
 394 # endif
 395     int bypp = s->bypp;
 396     int bypl = bypp * s->width;
 397     int width = bypp * w;
 398     int line = h;
 399     int column;
 400     uint8_t *fst = vram + bypp * x + bypl * y;
 401     uint8_t *dst;
 402     uint8_t *src;
 403     uint8_t col[4];
 404
 405 # ifdef DIRECT_VRAM
 406     if (s->ds->dpy_fill)
 407         s->ds->dpy_fill(s->ds, x, y, w, h, c);
 408     else
 409 # endif
 410     {
 411         col[0] = c;
 412         col[1] = c >> 8;
 413         col[2] = c >> 16;
 414         col[3] = c >> 24;
 415
 416         if (line --) {
 417             dst = fst;
 418             src = col;
 419             for (column = width; column > 0; column --) {
 420                 *(dst ++) = *(src ++);
 421                 if (src - col == bypp)
 422                     src = col;
 423             }
 424             dst = fst;
 425             for (; line > 0; line --) {
 426                 dst += bypl;
 427                 memcpy(dst, fst, width);
 428             }
 429         }
 430     }
 431
 432     vmsvga_update_rect_delayed(s, x, y, w, h);
 433 }
 434 #endif
 435
 436 struct vmsvga_cursor_definition_s {
 437     int width;
 438     int height;
 439     int id;
 440     int bpp;
 441     int hot_x;
 442     int hot_y;
 443     uint32_t mask[1024];
 444     uint32_t image[1024];
 445 };
 446
 447 #define SVGA_BITMAP_SIZE(w, h)          ((((w) + 31) >> 5) * (h))
 448 #define SVGA_PIXMAP_SIZE(w, h, bpp)     (((((w) * (bpp)) + 31) >> 5) * (h))
 449
 450 #ifdef HW_MOUSE_ACCEL
 451 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
 452                 struct vmsvga_cursor_definition_s *c)
 453 {
 454     int i;
 455     for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
 456         c->mask[i] = ~c->mask[i];
 457
 458     if (s->ds->cursor_define)
 459         s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
 460                         (uint8_t *) c->image, (uint8_t *) c->mask);
 461 }
 462 #endif
 463
 464 static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
 465 {
 466     if (!s->config || !s->enable)
 467         return 1;
 468     return (s->cmd->next_cmd == s->cmd->stop);
 469 }
 470
 471 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
 472 {
 473     uint32_t cmd = s->fifo[s->cmd->stop >> 2];
 474     s->cmd->stop += 4;
 475     if (s->cmd->stop >= s->cmd->max)
 476         s->cmd->stop = s->cmd->min;
 477     return cmd;
 478 }
 479
 480 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
 481 {
 482     uint32_t cmd, colour;
 483     int args = 0;
 484     int x, y, dx, dy, width, height;
 485     struct vmsvga_cursor_definition_s cursor;
 486     while (!vmsvga_fifo_empty(s))
 487         switch (cmd = vmsvga_fifo_read(s)) {
 488         case SVGA_CMD_UPDATE:
 489         case SVGA_CMD_UPDATE_VERBOSE:
 490             x = vmsvga_fifo_read(s);
 491             y = vmsvga_fifo_read(s);
 492             width = vmsvga_fifo_read(s);
 493             height = vmsvga_fifo_read(s);
 494             vmsvga_update_rect_delayed(s, x, y, width, height);
 495             break;
 496
 497         case SVGA_CMD_RECT_FILL:
 498             colour = vmsvga_fifo_read(s);
 499             x = vmsvga_fifo_read(s);
 500             y = vmsvga_fifo_read(s);
 501             width = vmsvga_fifo_read(s);
 502             height = vmsvga_fifo_read(s);
 503 #ifdef HW_FILL_ACCEL
 504             vmsvga_fill_rect(s, colour, x, y, width, height);
 505             break;
 506 #else
 507             goto badcmd;
 508 #endif
 509
 510         case SVGA_CMD_RECT_COPY:
 511             x = vmsvga_fifo_read(s);
 512             y = vmsvga_fifo_read(s);
 513             dx = vmsvga_fifo_read(s);
 514             dy = vmsvga_fifo_read(s);
 515             width = vmsvga_fifo_read(s);
 516             height = vmsvga_fifo_read(s);
 517 #ifdef HW_RECT_ACCEL
 518             vmsvga_copy_rect(s, x, y, dx, dy, width, height);
 519             break;
 520 #else
 521             goto badcmd;
 522 #endif
 523
 524         case SVGA_CMD_DEFINE_CURSOR:
 525             cursor.id = vmsvga_fifo_read(s);
 526             cursor.hot_x = vmsvga_fifo_read(s);
 527             cursor.hot_y = vmsvga_fifo_read(s);
 528             cursor.width = x = vmsvga_fifo_read(s);
 529             cursor.height = y = vmsvga_fifo_read(s);
 530             vmsvga_fifo_read(s);
 531             cursor.bpp = vmsvga_fifo_read(s);
 532             for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
 533                 cursor.mask[args] = vmsvga_fifo_read(s);
 534             for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
 535                 cursor.image[args] = vmsvga_fifo_read(s);
 536 #ifdef HW_MOUSE_ACCEL
 537             vmsvga_cursor_define(s, &cursor);
 538             break;
 539 #else
 540             args = 0;
 541             goto badcmd;
 542 #endif
 543
 544         /*
 545          * Other commands that we at least know the number of arguments
 546          * for so we can avoid FIFO desync if driver uses them illegally.
 547          */
 548         case SVGA_CMD_DEFINE_ALPHA_CURSOR:
 549             vmsvga_fifo_read(s);
 550             vmsvga_fifo_read(s);
 551             vmsvga_fifo_read(s);
 552             x = vmsvga_fifo_read(s);
 553             y = vmsvga_fifo_read(s);
 554             args = x * y;
 555             goto badcmd;
 556         case SVGA_CMD_RECT_ROP_FILL:
 557             args = 6;
 558             goto badcmd;
 559         case SVGA_CMD_RECT_ROP_COPY:
 560             args = 7;
 561             goto badcmd;
 562         case SVGA_CMD_DRAW_GLYPH_CLIPPED:
 563             vmsvga_fifo_read(s);
 564             vmsvga_fifo_read(s);
 565             args = 7 + (vmsvga_fifo_read(s) >> 2);
 566             goto badcmd;
 567         case SVGA_CMD_SURFACE_ALPHA_BLEND:
 568             args = 12;
 569             goto badcmd;
 570
 571         /*
 572          * Other commands that are not listed as depending on any
 573          * CAPABILITIES bits, but are not described in the README either.
 574          */
 575         case SVGA_CMD_SURFACE_FILL:
 576         case SVGA_CMD_SURFACE_COPY:
 577         case SVGA_CMD_FRONT_ROP_FILL:
 578         case SVGA_CMD_FENCE:
 579         case SVGA_CMD_INVALID_CMD:
 580             break; /* Nop */
 581
 582         default:
 583         badcmd:
 584             while (args --)
 585                 vmsvga_fifo_read(s);
 586             printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
 587                             __FUNCTION__, cmd);
 588             break;
 589         }
 590
 591     s->syncing = 0;
 592 }
 593
 594 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
 595 {
 596     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 597     return s->index;
 598 }
 599
 600 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
 601 {
 602     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 603     s->index = index;
 604 }
 605
 606 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
 607 {
 608     uint32_t caps;
 609     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 610     switch (s->index) {
 611     case SVGA_REG_ID:
 612         return s->svgaid;
 613
 614     case SVGA_REG_ENABLE:
 615         return s->enable;
 616
 617     case SVGA_REG_WIDTH:
 618         return s->width;
 619
 620     case SVGA_REG_HEIGHT:
 621         return s->height;
 622
 623     case SVGA_REG_MAX_WIDTH:
 624         return SVGA_MAX_WIDTH;
 625
 626     case SVGA_REG_MAX_HEIGHT:
 627         return SVGA_MAX_HEIGHT;
 628
 629     case SVGA_REG_DEPTH:
 630         return s->depth;
 631
 632     case SVGA_REG_BITS_PER_PIXEL:
 633         return (s->depth + 7) & ~7;
 634
 635     case SVGA_REG_PSEUDOCOLOR:
 636         return 0x0;
 637
 638     case SVGA_REG_RED_MASK:
 639         return s->wred;
 640     case SVGA_REG_GREEN_MASK:
 641         return s->wgreen;
 642     case SVGA_REG_BLUE_MASK:
 643         return s->wblue;
 644
 645     case SVGA_REG_BYTES_PER_LINE:
 646         return ((s->depth + 7) >> 3) * s->new_width;
 647
 648     case SVGA_REG_FB_START:
 649         return s->vram_addr;
 650
 651     case SVGA_REG_FB_OFFSET:
 652         return 0x0;
 653
 654     case SVGA_REG_VRAM_SIZE:
 655         return s->vram_size - SVGA_FIFO_SIZE;
 656
 657     case SVGA_REG_FB_SIZE:
 658         return s->fb_size;
 659
 660     case SVGA_REG_CAPABILITIES:
 661         caps = SVGA_CAP_NONE;
 662 #ifdef HW_RECT_ACCEL
 663         caps |= SVGA_CAP_RECT_COPY;
 664 #endif
 665 #ifdef HW_FILL_ACCEL
 666         caps |= SVGA_CAP_RECT_FILL;
 667 #endif
 668 #ifdef HW_MOUSE_ACCEL
 669         if (s->ds->mouse_set)
 670             caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
 671                     SVGA_CAP_CURSOR_BYPASS;
 672 #endif
 673         return caps;
 674
 675     case SVGA_REG_MEM_START:
 676         return s->vram_addr + s->vram_size - SVGA_FIFO_SIZE;
 677
 678     case SVGA_REG_MEM_SIZE:
 679         return SVGA_FIFO_SIZE;
 680
 681     case SVGA_REG_CONFIG_DONE:
 682         return s->config;
 683
 684     case SVGA_REG_SYNC:
 685     case SVGA_REG_BUSY:
 686         return s->syncing;
 687
 688     case SVGA_REG_GUEST_ID:
 689         return s->guest;
 690
 691     case SVGA_REG_CURSOR_ID:
 692         return s->cursor.id;
 693
 694     case SVGA_REG_CURSOR_X:
 695         return s->cursor.x;
 696
 697     case SVGA_REG_CURSOR_Y:
 698         return s->cursor.x;
 699
 700     case SVGA_REG_CURSOR_ON:
 701         return s->cursor.on;
 702
 703     case SVGA_REG_HOST_BITS_PER_PIXEL:
 704         return (s->depth + 7) & ~7;
 705
 706     case SVGA_REG_SCRATCH_SIZE:
 707         return s->scratch_size;
 708
 709     case SVGA_REG_MEM_REGS:
 710     case SVGA_REG_NUM_DISPLAYS:
 711     case SVGA_REG_PITCHLOCK:
 712     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 713         return 0;
 714
 715     default:
 716         if (s->index >= SVGA_SCRATCH_BASE &&
 717                 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
 718             return s->scratch[s->index - SVGA_SCRATCH_BASE];
 719         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 720     }
 721
 722     return 0;
 723 }
 724
 725 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
 726 {
 727     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 728     switch (s->index) {
 729     case SVGA_REG_ID:
 730         if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
 731             s->svgaid = value;
 732         break;
 733
 734     case SVGA_REG_ENABLE:
 735         s->enable = value;
 736         s->config &= !!value;
 737         s->width = -1;
 738         s->height = -1;
 739         s->invalidated = 1;
 740 #ifdef EMBED_STDVGA
 741         s->invalidate(opaque);
 742 #endif
 743         if (s->enable)
 744             s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
 745         break;
 746
 747     case SVGA_REG_WIDTH:
 748         s->new_width = value;
 749         s->invalidated = 1;
 750         break;
 751
 752     case SVGA_REG_HEIGHT:
 753         s->new_height = value;
 754         s->invalidated = 1;
 755         break;
 756
 757     case SVGA_REG_DEPTH:
 758     case SVGA_REG_BITS_PER_PIXEL:
 759         if (value != s->depth) {
 760             printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
 761             s->config = 0;
 762         }
 763         break;
 764
 765     case SVGA_REG_CONFIG_DONE:
 766         if (value) {
 767             s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
 768             /* Check range and alignment.  */
 769             if ((s->cmd->min | s->cmd->max |
 770                         s->cmd->next_cmd | s->cmd->stop) & 3)
 771                 break;
 772             if (s->cmd->min < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
 773                 break;
 774             if (s->cmd->max > SVGA_FIFO_SIZE)
 775                 break;
 776             if (s->cmd->max < s->cmd->min + 10 * 1024)
 777                 break;
 778         }
 779         s->config = !!value;
 780         break;
 781
 782     case SVGA_REG_SYNC:
 783         s->syncing = 1;
 784         vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
 785         break;
 786
 787     case SVGA_REG_GUEST_ID:
 788         s->guest = value;
 789 #ifdef VERBOSE
 790         if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
 791                 sizeof(vmsvga_guest_id) / sizeof(*vmsvga_guest_id))
 792             printf("%s: guest runs %s.\n", __FUNCTION__,
 793                             vmsvga_guest_id[value - GUEST_OS_BASE]);
 794 #endif
 795         break;
 796
 797     case SVGA_REG_CURSOR_ID:
 798         s->cursor.id = value;
 799         break;
 800
 801     case SVGA_REG_CURSOR_X:
 802         s->cursor.x = value;
 803         break;
 804
 805     case SVGA_REG_CURSOR_Y:
 806         s->cursor.y = value;
 807         break;
 808
 809     case SVGA_REG_CURSOR_ON:
 810         s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
 811         s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
 812 #ifdef HW_MOUSE_ACCEL
 813         if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
 814             s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
 815 #endif
 816         break;
 817
 818     case SVGA_REG_MEM_REGS:
 819     case SVGA_REG_NUM_DISPLAYS:
 820     case SVGA_REG_PITCHLOCK:
 821     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 822         break;
 823
 824     default:
 825         if (s->index >= SVGA_SCRATCH_BASE &&
 826                 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 827             s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
 828             break;
 829         }
 830         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 831     }
 832 }
 833
 834 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
 835 {
 836     printf("%s: what are we supposed to return?\n", __FUNCTION__);
 837     return 0xcafe;
 838 }
 839
 840 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
 841 {
 842     printf("%s: what are we supposed to do with (%08x)?\n",
 843                     __FUNCTION__, data);
 844 }
 845
 846 static inline void vmsvga_size(struct vmsvga_state_s *s)
 847 {
 848     if (s->new_width != s->width || s->new_height != s->height) {
 849         s->width = s->new_width;
 850         s->height = s->new_height;
 851         dpy_resize(s->ds, s->width, s->height);
 852         s->invalidated = 1;
 853     }
 854 }
 855
 856 static void vmsvga_update_display(void *opaque)
 857 {
 858     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 859     if (!s->enable) {
 860 #ifdef EMBED_STDVGA
 861         s->update(opaque);
 862 #endif
 863         return;
 864     }
 865
 866     vmsvga_size(s);
 867
 868     vmsvga_fifo_run(s);
 869     vmsvga_update_rect_flush(s);
 870
 871     /*
 872      * Is it more efficient to look at vram VGA-dirty bits or wait
 873      * for the driver to issue SVGA_CMD_UPDATE?
 874      */
 875     if (s->invalidated) {
 876         s->invalidated = 0;
 877         vmsvga_update_screen(s);
 878     }
 879 }
 880
 881 static void vmsvga_reset(struct vmsvga_state_s *s)
 882 {
 883     s->index = 0;
 884     s->enable = 0;
 885     s->config = 0;
 886     s->width = -1;
 887     s->height = -1;
 888     s->svgaid = SVGA_ID;
 889     s->depth = s->ds->depth ? s->ds->depth : 24;
 890     s->bypp = (s->depth + 7) >> 3;
 891     s->cursor.on = 0;
 892     s->redraw_fifo_first = 0;
 893     s->redraw_fifo_last = 0;
 894     switch (s->depth) {
 895     case 8:
 896         s->wred   = 0x00000007;
 897         s->wgreen = 0x00000038;
 898         s->wblue  = 0x000000c0;
 899         break;
 900     case 15:
 901         s->wred   = 0x0000001f;
 902         s->wgreen = 0x000003e0;
 903         s->wblue  = 0x00007c00;
 904         break;
 905     case 16:
 906         s->wred   = 0x0000001f;
 907         s->wgreen = 0x000007e0;
 908         s->wblue  = 0x0000f800;
 909         break;
 910     case 24:
 911         s->wred   = 0x00ff0000;
 912         s->wgreen = 0x0000ff00;
 913         s->wblue  = 0x000000ff;
 914         break;
 915     case 32:
 916         s->wred   = 0x00ff0000;
 917         s->wgreen = 0x0000ff00;
 918         s->wblue  = 0x000000ff;
 919         break;
 920     }
 921     s->syncing = 0;
 922 }
 923
 924 static void vmsvga_invalidate_display(void *opaque)
 925 {
 926     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 927     if (!s->enable) {
 928 #ifdef EMBED_STDVGA
 929         s->invalidate(opaque);
 930 #endif
 931         return;
 932     }
 933
 934     s->invalidated = 1;
 935 }
 936
 937 /* save the vga display in a PPM image even if no display is
 938    available */
 939 static void vmsvga_screen_dump(void *opaque, const char *filename)
 940 {
 941     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 942     if (!s->enable) {
 943 #ifdef EMBED_STDVGA
 944         s->screen_dump(opaque, filename);
 945 #endif
 946         return;
 947     }
 948
 949     if (s->depth == 32) {
 950         ppm_save(filename, s->vram, s->width, s->height, s->ds->linesize);
 951     }
 952 }
 953
 954 #ifdef DIRECT_VRAM
 955 static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
 956 {
 957     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 958     addr -= s->vram_addr;
 959     if (addr < s->fb_size)
 960         return *(uint8_t *) (s->ds->data + addr);
 961     else
 962         return *(uint8_t *) (s->vram + addr);
 963 }
 964
 965 static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
 966 {
 967     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 968     addr -= s->vram_addr;
 969     if (addr < s->fb_size)
 970         return *(uint16_t *) (s->ds->data + addr);
 971     else
 972         return *(uint16_t *) (s->vram + addr);
 973 }
 974
 975 static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
 976 {
 977     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 978     addr -= s->vram_addr;
 979     if (addr < s->fb_size)
 980         return *(uint32_t *) (s->ds->data + addr);
 981     else
 982         return *(uint32_t *) (s->vram + addr);
 983 }
 984
 985 static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
 986                 uint32_t value)
 987 {
 988     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 989     addr -= s->vram_addr;
 990     if (addr < s->fb_size)
 991         *(uint8_t *) (s->ds->data + addr) = value;
 992     else
 993         *(uint8_t *) (s->vram + addr) = value;
 994 }
 995
 996 static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
 997                 uint32_t value)
 998 {
 999     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1000     addr -= s->vram_addr;
1001     if (addr < s->fb_size)
1002         *(uint16_t *) (s->ds->data + addr) = value;
1003     else
1004         *(uint16_t *) (s->vram + addr) = value;
1005 }
1006
1007 static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1008                 uint32_t value)
1009 {
1010     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1011     addr -= s->vram_addr;
1012     if (addr < s->fb_size)
1013         *(uint32_t *) (s->ds->data + addr) = value;
1014     else
1015         *(uint32_t *) (s->vram + addr) = value;
1016 }
1017
1018 static CPUReadMemoryFunc *vmsvga_vram_read[] = {
1019     vmsvga_vram_readb,
1020     vmsvga_vram_readw,
1021     vmsvga_vram_readl,
1022 };
1023
1024 static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
1025     vmsvga_vram_writeb,
1026     vmsvga_vram_writew,
1027     vmsvga_vram_writel,
1028 };
1029 #endif
1030
1031 static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
1032 {
1033     qemu_put_be32(f, s->depth);
1034     qemu_put_be32(f, s->enable);
1035     qemu_put_be32(f, s->config);
1036     qemu_put_be32(f, s->cursor.id);
1037     qemu_put_be32(f, s->cursor.x);
1038     qemu_put_be32(f, s->cursor.y);
1039     qemu_put_be32(f, s->cursor.on);
1040     qemu_put_be32(f, s->index);
1041     qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1042     qemu_put_be32(f, s->new_width);
1043     qemu_put_be32(f, s->new_height);
1044     qemu_put_be32s(f, &s->guest);
1045     qemu_put_be32s(f, &s->svgaid);
1046     qemu_put_be32(f, s->syncing);
1047     qemu_put_be32(f, s->fb_size);
1048 }
1049
1050 static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1051 {
1052     int depth;
1053     depth=qemu_get_be32(f);
1054     s->enable=qemu_get_be32(f);
1055     s->config=qemu_get_be32(f);
1056     s->cursor.id=qemu_get_be32(f);
1057     s->cursor.x=qemu_get_be32(f);
1058     s->cursor.y=qemu_get_be32(f);
1059     s->cursor.on=qemu_get_be32(f);
1060     s->index=qemu_get_be32(f);
1061     qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1062     s->new_width=qemu_get_be32(f);
1063     s->new_height=qemu_get_be32(f);
1064     qemu_get_be32s(f, &s->guest);
1065     qemu_get_be32s(f, &s->svgaid);
1066     s->syncing=qemu_get_be32(f);
1067     s->fb_size=qemu_get_be32(f);
1068
1069     if (s->enable && depth != s->depth) {
1070         printf("%s: need colour depth of %i bits to resume operation.\n",
1071                         __FUNCTION__, depth);
1072         return -EINVAL;
1073     }
1074
1075     s->invalidated = 1;
1076     if (s->config)
1077         s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
1078
1079     return 0;
1080 }
1081
1082 static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
1083                 uint8_t *vga_ram_base, unsigned long vga_ram_offset,
1084                 int vga_ram_size)
1085 {
1086     s->ds = ds;
1087     s->vram = vga_ram_base;
1088     s->vram_size = vga_ram_size;
1089     s->vram_addr = 0;
1090
1091     s->scratch_size = SVGA_SCRATCH_SIZE;
1092     s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
1093
1094     vmsvga_reset(s);
1095
1096 #ifdef DIRECT_VRAM
1097     s->iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1098                                           vmsvga_vram_write, s);
1099 #else
1100     s->iomemtype = vga_ram_offset | IO_MEM_RAM;
1101 #endif
1102
1103     graphic_console_init(ds, vmsvga_update_display,
1104                     vmsvga_invalidate_display, vmsvga_screen_dump, s);
1105
1106 #ifdef EMBED_STDVGA
1107     vga_common_init((VGAState *) s, ds,
1108                     vga_ram_base, vga_ram_offset, vga_ram_size);
1109     vga_init((VGAState *) s);
1110 #endif
1111 }
1112
1113 static void pci_vmsvga_save(QEMUFile *f, void *opaque)
1114 {
1115     struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1116     pci_device_save(&s->card, f);
1117     vmsvga_save(&s->chip, f);
1118 }
1119
1120 static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
1121 {
1122     struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1123     int ret;
1124
1125     ret = pci_device_load(&s->card, f);
1126     if (ret < 0)
1127         return ret;
1128
1129     ret = vmsvga_load(&s->chip, f);
1130     if (ret < 0)
1131         return ret;
1132
1133     return 0;
1134 }
1135
1136 static void pci_vmsvga_map(PCIDevice *pci_dev, int region_num,
1137                 uint32_t addr, uint32_t size, int type)
1138 {
1139     struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1140     struct vmsvga_state_s *s = &d->chip;
1141
1142     if (region_num == 0) {
1143         register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1144                              1, 4, vmsvga_index_read, s);
1145         register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1146                               1, 4, vmsvga_index_write, s);
1147         register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1148                              1, 4, vmsvga_value_read, s);
1149         register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1150                               1, 4, vmsvga_value_write, s);
1151         register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1152                              1, 4, vmsvga_bios_read, s);
1153         register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1154                               1, 4, vmsvga_bios_write, s);
1155     } else {
1156         cpu_register_physical_memory(addr, s->vram_size, s->iomemtype);
1157         s->vram_addr = addr;
1158         s->vram = s->vram_ptr;
1159     }
1160 }
1161
1162 #define PCI_VENDOR_ID_VMWARE            0x15ad
1163 #define PCI_DEVICE_ID_VMWARE_SVGA2      0x0405
1164 #define PCI_DEVICE_ID_VMWARE_SVGA       0x0710
1165 #define PCI_DEVICE_ID_VMWARE_NET        0x0720
1166 #define PCI_DEVICE_ID_VMWARE_SCSI       0x0730
1167 #define PCI_DEVICE_ID_VMWARE_IDE        0x1729
1168 #define PCI_CLASS_BASE_DISPLAY          0x03
1169 #define PCI_CLASS_SUB_VGA               0x00
1170 #define PCI_CLASS_HEADERTYPE_00h        0x00
1171
1172 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1173                      unsigned long vga_ram_offset, int vga_ram_size)
1174 {
1175     struct pci_vmsvga_state_s *s;
1176
1177     /* Setup PCI configuration */
1178     s = (struct pci_vmsvga_state_s *)
1179         pci_register_device(bus, "QEMUware SVGA",
1180                 sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
1181     s->card.config[PCI_VENDOR_ID]       = PCI_VENDOR_ID_VMWARE & 0xff;
1182     s->card.config[PCI_VENDOR_ID + 1]   = PCI_VENDOR_ID_VMWARE >> 8;
1183     s->card.config[PCI_DEVICE_ID]       = SVGA_PCI_DEVICE_ID & 0xff;
1184     s->card.config[PCI_DEVICE_ID + 1]   = SVGA_PCI_DEVICE_ID >> 8;
1185     s->card.config[PCI_COMMAND]         = 0x07;         /* I/O + Memory */
1186     s->card.config[PCI_CLASS_DEVICE]    = PCI_CLASS_SUB_VGA;
1187     s->card.config[0x0b]                = PCI_CLASS_BASE_DISPLAY;
1188     s->card.config[0x0c]                = 0x08;         /* Cache line size */
1189     s->card.config[0x0d]                = 0x40;         /* Latency timer */
1190     s->card.config[0x0e]                = PCI_CLASS_HEADERTYPE_00h;
1191     s->card.config[0x2c]                = PCI_VENDOR_ID_VMWARE & 0xff;
1192     s->card.config[0x2d]                = PCI_VENDOR_ID_VMWARE >> 8;
1193     s->card.config[0x2e]                = SVGA_PCI_DEVICE_ID & 0xff;
1194     s->card.config[0x2f]                = SVGA_PCI_DEVICE_ID >> 8;
1195     s->card.config[0x3c]                = 0xff;         /* End */
1196
1197     pci_register_io_region(&s->card, 0, 0x10,
1198                            PCI_ADDRESS_SPACE_IO, pci_vmsvga_map);
1199
1200     pci_register_io_region(&s->card, 1, vga_ram_size,
1201                            PCI_ADDRESS_SPACE_MEM, pci_vmsvga_map);
1202
1203     vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
1204
1205     register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
1206 }