target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27
  28 #ifdef KVM_UPSTREAM
  29 //#define DEBUG_KVM
  30
  31 #ifdef DEBUG_KVM
  32 #define dprintf(fmt, ...) \
  33     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  34 #else
  35 #define dprintf(fmt, ...) \
  36     do { } while (0)
  37 #endif
  38
  39 #define MSR_KVM_WALL_CLOCK  0x11
  40 #define MSR_KVM_SYSTEM_TIME 0x12
  41
  42 #ifdef KVM_CAP_EXT_CPUID
  43
  44 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  45 {
  46     struct kvm_cpuid2 *cpuid;
  47     int r, size;
  48
  49     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  50     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  51     cpuid->nent = max;
  52     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  53     if (r == 0 && cpuid->nent >= max) {
  54         r = -E2BIG;
  55     }
  56     if (r < 0) {
  57         if (r == -E2BIG) {
  58             qemu_free(cpuid);
  59             return NULL;
  60         } else {
  61             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  62                     strerror(-r));
  63             exit(1);
  64         }
  65     }
  66     return cpuid;
  67 }
  68
  69 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  70 {
  71     struct kvm_cpuid2 *cpuid;
  72     int i, max;
  73     uint32_t ret = 0;
  74     uint32_t cpuid_1_edx;
  75
  76     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  77         return -1U;
  78     }
  79
  80     max = 1;
  81     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  82         max *= 2;
  83     }
  84
  85     for (i = 0; i < cpuid->nent; ++i) {
  86         if (cpuid->entries[i].function == function) {
  87             switch (reg) {
  88             case R_EAX:
  89                 ret = cpuid->entries[i].eax;
  90                 break;
  91             case R_EBX:
  92                 ret = cpuid->entries[i].ebx;
  93                 break;
  94             case R_ECX:
  95                 ret = cpuid->entries[i].ecx;
  96                 break;
  97             case R_EDX:
  98                 ret = cpuid->entries[i].edx;
  99                 if (function == 0x80000001) {
 100                     /* On Intel, kvm returns cpuid according to the Intel spec,
 101                      * so add missing bits according to the AMD spec:
 102                      */
 103                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
 104                     ret |= cpuid_1_edx & 0xdfeff7ff;
 105                 }
 106                 break;
 107             }
 108         }
 109     }
 110
 111     qemu_free(cpuid);
 112
 113     return ret;
 114 }
 115
 116 #else
 117
 118 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 119 {
 120     return -1U;
 121 }
 122
 123 #endif
 124
 125 static void kvm_trim_features(uint32_t *features, uint32_t supported)
 126 {
 127     int i;
 128     uint32_t mask;
 129
 130     for (i = 0; i < 32; ++i) {
 131         mask = 1U << i;
 132         if ((*features & mask) && !(supported & mask)) {
 133             *features &= ~mask;
 134         }
 135     }
 136 }
 137
 138 int kvm_arch_init_vcpu(CPUState *env)
 139 {
 140     struct {
 141         struct kvm_cpuid2 cpuid;
 142         struct kvm_cpuid_entry2 entries[100];
 143     } __attribute__((packed)) cpuid_data;
 144     uint32_t limit, i, j, cpuid_i;
 145     uint32_t unused;
 146
 147     env->mp_state = KVM_MP_STATE_RUNNABLE;
 148
 149     kvm_trim_features(&env->cpuid_features,
 150         kvm_arch_get_supported_cpuid(env, 1, R_EDX));
 151
 152     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 153     kvm_trim_features(&env->cpuid_ext_features,
 154         kvm_arch_get_supported_cpuid(env, 1, R_ECX));
 155     env->cpuid_ext_features |= i;
 156
 157     kvm_trim_features(&env->cpuid_ext2_features,
 158         kvm_arch_get_supported_cpuid(env, 0x80000001, R_EDX));
 159     kvm_trim_features(&env->cpuid_ext3_features,
 160         kvm_arch_get_supported_cpuid(env, 0x80000001, R_ECX));
 161
 162     cpuid_i = 0;
 163
 164     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 165
 166     for (i = 0; i <= limit; i++) {
 167         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 168
 169         switch (i) {
 170         case 2: {
 171             /* Keep reading function 2 till all the input is received */
 172             int times;
 173
 174             c->function = i;
 175             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 176                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 177             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 178             times = c->eax & 0xff;
 179
 180             for (j = 1; j < times; ++j) {
 181                 c = &cpuid_data.entries[cpuid_i++];
 182                 c->function = i;
 183                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 184                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 185             }
 186             break;
 187         }
 188         case 4:
 189         case 0xb:
 190         case 0xd:
 191             for (j = 0; ; j++) {
 192                 c->function = i;
 193                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 194                 c->index = j;
 195                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 196
 197                 if (i == 4 && c->eax == 0)
 198                     break;
 199                 if (i == 0xb && !(c->ecx & 0xff00))
 200                     break;
 201                 if (i == 0xd && c->eax == 0)
 202                     break;
 203
 204                 c = &cpuid_data.entries[cpuid_i++];
 205             }
 206             break;
 207         default:
 208             c->function = i;
 209             c->flags = 0;
 210             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 211             break;
 212         }
 213     }
 214     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 215
 216     for (i = 0x80000000; i <= limit; i++) {
 217         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 218
 219         c->function = i;
 220         c->flags = 0;
 221         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 222     }
 223
 224     cpuid_data.cpuid.nent = cpuid_i;
 225
 226     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 227 }
 228
 229 void kvm_arch_reset_vcpu(CPUState *env)
 230 {
 231     env->interrupt_injected = -1;
 232     env->nmi_injected = 0;
 233     env->nmi_pending = 0;
 234 }
 235
 236 static int kvm_has_msr_star(CPUState *env)
 237 {
 238     static int has_msr_star;
 239     int ret;
 240
 241     /* first time */
 242     if (has_msr_star == 0) {
 243         struct kvm_msr_list msr_list, *kvm_msr_list;
 244
 245         has_msr_star = -1;
 246
 247         /* Obtain MSR list from KVM.  These are the MSRs that we must
 248          * save/restore */
 249         msr_list.nmsrs = 0;
 250         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 251         if (ret < 0 && ret != -E2BIG) {
 252             return 0;
 253         }
 254         /* Old kernel modules had a bug and could write beyond the provided
 255            memory. Allocate at least a safe amount of 1K. */
 256         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 257                                               msr_list.nmsrs *
 258                                               sizeof(msr_list.indices[0])));
 259
 260         kvm_msr_list->nmsrs = msr_list.nmsrs;
 261         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 262         if (ret >= 0) {
 263             int i;
 264
 265             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 266                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 267                     has_msr_star = 1;
 268                     break;
 269                 }
 270             }
 271         }
 272
 273         free(kvm_msr_list);
 274     }
 275
 276     if (has_msr_star == 1)
 277         return 1;
 278     return 0;
 279 }
 280
 281 int kvm_arch_init(KVMState *s, int smp_cpus)
 282 {
 283     int ret;
 284
 285     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 286      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 287      * must be part of guest physical memory, we need to allocate it.  Older
 288      * versions of KVM just assumed that it would be at the end of physical
 289      * memory but that doesn't work with more than 4GB of memory.  We simply
 290      * refuse to work with those older versions of KVM. */
 291     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 292     if (ret <= 0) {
 293         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 294         return ret;
 295     }
 296
 297     /* this address is 3 pages before the bios, and the bios should present
 298      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 299      * this?
 300      */
 301     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 302 }
 303
 304 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 305 {
 306     lhs->selector = rhs->selector;
 307     lhs->base = rhs->base;
 308     lhs->limit = rhs->limit;
 309     lhs->type = 3;
 310     lhs->present = 1;
 311     lhs->dpl = 3;
 312     lhs->db = 0;
 313     lhs->s = 1;
 314     lhs->l = 0;
 315     lhs->g = 0;
 316     lhs->avl = 0;
 317     lhs->unusable = 0;
 318 }
 319
 320 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 321 {
 322     unsigned flags = rhs->flags;
 323     lhs->selector = rhs->selector;
 324     lhs->base = rhs->base;
 325     lhs->limit = rhs->limit;
 326     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 327     lhs->present = (flags & DESC_P_MASK) != 0;
 328     lhs->dpl = rhs->selector & 3;
 329     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 330     lhs->s = (flags & DESC_S_MASK) != 0;
 331     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 332     lhs->g = (flags & DESC_G_MASK) != 0;
 333     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 334     lhs->unusable = 0;
 335 }
 336
 337 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 338 {
 339     lhs->selector = rhs->selector;
 340     lhs->base = rhs->base;
 341     lhs->limit = rhs->limit;
 342     lhs->flags =
 343         (rhs->type << DESC_TYPE_SHIFT)
 344         | (rhs->present * DESC_P_MASK)
 345         | (rhs->dpl << DESC_DPL_SHIFT)
 346         | (rhs->db << DESC_B_SHIFT)
 347         | (rhs->s * DESC_S_MASK)
 348         | (rhs->l << DESC_L_SHIFT)
 349         | (rhs->g * DESC_G_MASK)
 350         | (rhs->avl * DESC_AVL_MASK);
 351 }
 352
 353 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 354 {
 355     if (set)
 356         *kvm_reg = *qemu_reg;
 357     else
 358         *qemu_reg = *kvm_reg;
 359 }
 360
 361 static int kvm_getput_regs(CPUState *env, int set)
 362 {
 363     struct kvm_regs regs;
 364     int ret = 0;
 365
 366     if (!set) {
 367         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 368         if (ret < 0)
 369             return ret;
 370     }
 371
 372     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 373     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 374     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 375     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 376     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 377     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 378     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 379     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 380 #ifdef TARGET_X86_64
 381     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 382     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 383     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 384     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 385     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 386     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 387     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 388     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 389 #endif
 390
 391     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 392     kvm_getput_reg(&regs.rip, &env->eip, set);
 393
 394     if (set)
 395         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 396
 397     return ret;
 398 }
 399
 400 static int kvm_put_fpu(CPUState *env)
 401 {
 402     struct kvm_fpu fpu;
 403     int i;
 404
 405     memset(&fpu, 0, sizeof fpu);
 406     fpu.fsw = env->fpus & ~(7 << 11);
 407     fpu.fsw |= (env->fpstt & 7) << 11;
 408     fpu.fcw = env->fpuc;
 409     for (i = 0; i < 8; ++i)
 410         fpu.ftwx |= (!env->fptags[i]) << i;
 411     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 412     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 413     fpu.mxcsr = env->mxcsr;
 414
 415     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 416 }
 417
 418 static int kvm_put_sregs(CPUState *env)
 419 {
 420     struct kvm_sregs sregs;
 421
 422     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 423     if (env->interrupt_injected >= 0) {
 424         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 425                 (uint64_t)1 << (env->interrupt_injected % 64);
 426     }
 427
 428     if ((env->eflags & VM_MASK)) {
 429             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 430             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 431             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 432             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 433             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 434             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 435     } else {
 436             set_seg(&sregs.cs, &env->segs[R_CS]);
 437             set_seg(&sregs.ds, &env->segs[R_DS]);
 438             set_seg(&sregs.es, &env->segs[R_ES]);
 439             set_seg(&sregs.fs, &env->segs[R_FS]);
 440             set_seg(&sregs.gs, &env->segs[R_GS]);
 441             set_seg(&sregs.ss, &env->segs[R_SS]);
 442
 443             if (env->cr[0] & CR0_PE_MASK) {
 444                 /* force ss cpl to cs cpl */
 445                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 446                         (sregs.cs.selector & 3);
 447                 sregs.ss.dpl = sregs.ss.selector & 3;
 448             }
 449     }
 450
 451     set_seg(&sregs.tr, &env->tr);
 452     set_seg(&sregs.ldt, &env->ldt);
 453
 454     sregs.idt.limit = env->idt.limit;
 455     sregs.idt.base = env->idt.base;
 456     sregs.gdt.limit = env->gdt.limit;
 457     sregs.gdt.base = env->gdt.base;
 458
 459     sregs.cr0 = env->cr[0];
 460     sregs.cr2 = env->cr[2];
 461     sregs.cr3 = env->cr[3];
 462     sregs.cr4 = env->cr[4];
 463
 464     sregs.cr8 = cpu_get_apic_tpr(env);
 465     sregs.apic_base = cpu_get_apic_base(env);
 466
 467     sregs.efer = env->efer;
 468
 469     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 470 }
 471
 472 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 473                               uint32_t index, uint64_t value)
 474 {
 475     entry->index = index;
 476     entry->data = value;
 477 }
 478
 479 static int kvm_put_msrs(CPUState *env)
 480 {
 481     struct {
 482         struct kvm_msrs info;
 483         struct kvm_msr_entry entries[100];
 484     } msr_data;
 485     struct kvm_msr_entry *msrs = msr_data.entries;
 486     int n = 0;
 487
 488     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 489     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 490     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 491     if (kvm_has_msr_star(env))
 492         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 493     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 494     kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 495 #ifdef TARGET_X86_64
 496     /* FIXME if lm capable */
 497     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 498     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 499     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 500     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 501 #endif
 502     kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,  env->system_time_msr);
 503     kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK,  env->wall_clock_msr);
 504
 505     msr_data.info.nmsrs = n;
 506
 507     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 508
 509 }
 510
 511
 512 static int kvm_get_fpu(CPUState *env)
 513 {
 514     struct kvm_fpu fpu;
 515     int i, ret;
 516
 517     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 518     if (ret < 0)
 519         return ret;
 520
 521     env->fpstt = (fpu.fsw >> 11) & 7;
 522     env->fpus = fpu.fsw;
 523     env->fpuc = fpu.fcw;
 524     for (i = 0; i < 8; ++i)
 525         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 526     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 527     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 528     env->mxcsr = fpu.mxcsr;
 529
 530     return 0;
 531 }
 532
 533 static int kvm_get_sregs(CPUState *env)
 534 {
 535     struct kvm_sregs sregs;
 536     uint32_t hflags;
 537     int bit, i, ret;
 538
 539     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 540     if (ret < 0)
 541         return ret;
 542
 543     /* There can only be one pending IRQ set in the bitmap at a time, so try
 544        to find it and save its number instead (-1 for none). */
 545     env->interrupt_injected = -1;
 546     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 547         if (sregs.interrupt_bitmap[i]) {
 548             bit = ctz64(sregs.interrupt_bitmap[i]);
 549             env->interrupt_injected = i * 64 + bit;
 550             break;
 551         }
 552     }
 553
 554     get_seg(&env->segs[R_CS], &sregs.cs);
 555     get_seg(&env->segs[R_DS], &sregs.ds);
 556     get_seg(&env->segs[R_ES], &sregs.es);
 557     get_seg(&env->segs[R_FS], &sregs.fs);
 558     get_seg(&env->segs[R_GS], &sregs.gs);
 559     get_seg(&env->segs[R_SS], &sregs.ss);
 560
 561     get_seg(&env->tr, &sregs.tr);
 562     get_seg(&env->ldt, &sregs.ldt);
 563
 564     env->idt.limit = sregs.idt.limit;
 565     env->idt.base = sregs.idt.base;
 566     env->gdt.limit = sregs.gdt.limit;
 567     env->gdt.base = sregs.gdt.base;
 568
 569     env->cr[0] = sregs.cr0;
 570     env->cr[2] = sregs.cr2;
 571     env->cr[3] = sregs.cr3;
 572     env->cr[4] = sregs.cr4;
 573
 574     cpu_set_apic_base(env, sregs.apic_base);
 575
 576     env->efer = sregs.efer;
 577     //cpu_set_apic_tpr(env, sregs.cr8);
 578
 579 #define HFLAG_COPY_MASK ~( \
 580                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 581                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 582                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 583                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 584
 585
 586
 587     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 588     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 589     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 590             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 591     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 592     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 593             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 594
 595     if (env->efer & MSR_EFER_LMA) {
 596         hflags |= HF_LMA_MASK;
 597     }
 598
 599     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 600         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 601     } else {
 602         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 603                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 604         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 605                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 606         if (!(env->cr[0] & CR0_PE_MASK) ||
 607                    (env->eflags & VM_MASK) ||
 608                    !(hflags & HF_CS32_MASK)) {
 609                 hflags |= HF_ADDSEG_MASK;
 610             } else {
 611                 hflags |= ((env->segs[R_DS].base |
 612                                 env->segs[R_ES].base |
 613                                 env->segs[R_SS].base) != 0) <<
 614                     HF_ADDSEG_SHIFT;
 615             }
 616     }
 617     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 618
 619     return 0;
 620 }
 621
 622 static int kvm_get_msrs(CPUState *env)
 623 {
 624     struct {
 625         struct kvm_msrs info;
 626         struct kvm_msr_entry entries[100];
 627     } msr_data;
 628     struct kvm_msr_entry *msrs = msr_data.entries;
 629     int ret, i, n;
 630
 631     n = 0;
 632     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 633     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 634     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 635     if (kvm_has_msr_star(env))
 636         msrs[n++].index = MSR_STAR;
 637     msrs[n++].index = MSR_IA32_TSC;
 638     msrs[n++].index = MSR_VM_HSAVE_PA;
 639 #ifdef TARGET_X86_64
 640     /* FIXME lm_capable_kernel */
 641     msrs[n++].index = MSR_CSTAR;
 642     msrs[n++].index = MSR_KERNELGSBASE;
 643     msrs[n++].index = MSR_FMASK;
 644     msrs[n++].index = MSR_LSTAR;
 645 #endif
 646     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
 647     msrs[n++].index = MSR_KVM_WALL_CLOCK;
 648
 649     msr_data.info.nmsrs = n;
 650     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 651     if (ret < 0)
 652         return ret;
 653
 654     for (i = 0; i < ret; i++) {
 655         switch (msrs[i].index) {
 656         case MSR_IA32_SYSENTER_CS:
 657             env->sysenter_cs = msrs[i].data;
 658             break;
 659         case MSR_IA32_SYSENTER_ESP:
 660             env->sysenter_esp = msrs[i].data;
 661             break;
 662         case MSR_IA32_SYSENTER_EIP:
 663             env->sysenter_eip = msrs[i].data;
 664             break;
 665         case MSR_STAR:
 666             env->star = msrs[i].data;
 667             break;
 668 #ifdef TARGET_X86_64
 669         case MSR_CSTAR:
 670             env->cstar = msrs[i].data;
 671             break;
 672         case MSR_KERNELGSBASE:
 673             env->kernelgsbase = msrs[i].data;
 674             break;
 675         case MSR_FMASK:
 676             env->fmask = msrs[i].data;
 677             break;
 678         case MSR_LSTAR:
 679             env->lstar = msrs[i].data;
 680             break;
 681 #endif
 682         case MSR_IA32_TSC:
 683             env->tsc = msrs[i].data;
 684             break;
 685         case MSR_KVM_SYSTEM_TIME:
 686             env->system_time_msr = msrs[i].data;
 687             break;
 688         case MSR_KVM_WALL_CLOCK:
 689             env->wall_clock_msr = msrs[i].data;
 690             break;
 691         case MSR_VM_HSAVE_PA:
 692             env->vm_hsave = msrs[i].data;
 693             break;
 694         }
 695     }
 696
 697     return 0;
 698 }
 699
 700 static int kvm_put_mp_state(CPUState *env)
 701 {
 702     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 703
 704     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
 705 }
 706
 707 static int kvm_get_mp_state(CPUState *env)
 708 {
 709     struct kvm_mp_state mp_state;
 710     int ret;
 711
 712     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
 713     if (ret < 0) {
 714         return ret;
 715     }
 716     env->mp_state = mp_state.mp_state;
 717     return 0;
 718 }
 719
 720 static int kvm_put_vcpu_events(CPUState *env)
 721 {
 722 #ifdef KVM_CAP_VCPU_EVENTS
 723     struct kvm_vcpu_events events;
 724
 725     if (!kvm_has_vcpu_events()) {
 726         return 0;
 727     }
 728
 729     events.exception.injected = (env->exception_injected >= 0);
 730     events.exception.nr = env->exception_injected;
 731     events.exception.has_error_code = env->has_error_code;
 732     events.exception.error_code = env->error_code;
 733
 734     events.interrupt.injected = (env->interrupt_injected >= 0);
 735     events.interrupt.nr = env->interrupt_injected;
 736     events.interrupt.soft = env->soft_interrupt;
 737
 738     events.nmi.injected = env->nmi_injected;
 739     events.nmi.pending = env->nmi_pending;
 740     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
 741
 742     events.sipi_vector = env->sipi_vector;
 743
 744     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
 745 #else
 746     return 0;
 747 #endif
 748 }
 749
 750 static int kvm_get_vcpu_events(CPUState *env)
 751 {
 752 #ifdef KVM_CAP_VCPU_EVENTS
 753     struct kvm_vcpu_events events;
 754     int ret;
 755
 756     if (!kvm_has_vcpu_events()) {
 757         return 0;
 758     }
 759
 760     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
 761     if (ret < 0) {
 762        return ret;
 763     }
 764     env->exception_injected =
 765        events.exception.injected ? events.exception.nr : -1;
 766     env->has_error_code = events.exception.has_error_code;
 767     env->error_code = events.exception.error_code;
 768
 769     env->interrupt_injected =
 770         events.interrupt.injected ? events.interrupt.nr : -1;
 771     env->soft_interrupt = events.interrupt.soft;
 772
 773     env->nmi_injected = events.nmi.injected;
 774     env->nmi_pending = events.nmi.pending;
 775     if (events.nmi.masked) {
 776         env->hflags2 |= HF2_NMI_MASK;
 777     } else {
 778         env->hflags2 &= ~HF2_NMI_MASK;
 779     }
 780
 781     env->sipi_vector = events.sipi_vector;
 782 #endif
 783
 784     return 0;
 785 }
 786
 787 int kvm_arch_put_registers(CPUState *env)
 788 {
 789     int ret;
 790
 791     ret = kvm_getput_regs(env, 1);
 792     if (ret < 0)
 793         return ret;
 794
 795     ret = kvm_put_fpu(env);
 796     if (ret < 0)
 797         return ret;
 798
 799     ret = kvm_put_sregs(env);
 800     if (ret < 0)
 801         return ret;
 802
 803     ret = kvm_put_msrs(env);
 804     if (ret < 0)
 805         return ret;
 806
 807     ret = kvm_put_mp_state(env);
 808     if (ret < 0)
 809         return ret;
 810
 811     ret = kvm_put_vcpu_events(env);
 812     if (ret < 0)
 813         return ret;
 814
 815     return 0;
 816 }
 817
 818 int kvm_arch_get_registers(CPUState *env)
 819 {
 820     int ret;
 821
 822     ret = kvm_getput_regs(env, 0);
 823     if (ret < 0)
 824         return ret;
 825
 826     ret = kvm_get_fpu(env);
 827     if (ret < 0)
 828         return ret;
 829
 830     ret = kvm_get_sregs(env);
 831     if (ret < 0)
 832         return ret;
 833
 834     ret = kvm_get_msrs(env);
 835     if (ret < 0)
 836         return ret;
 837
 838     ret = kvm_get_mp_state(env);
 839     if (ret < 0)
 840         return ret;
 841
 842     ret = kvm_get_vcpu_events(env);
 843     if (ret < 0)
 844         return ret;
 845
 846     return 0;
 847 }
 848
 849 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 850 {
 851     /* Try to inject an interrupt if the guest can accept it */
 852     if (run->ready_for_interrupt_injection &&
 853         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 854         (env->eflags & IF_MASK)) {
 855         int irq;
 856
 857         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 858         irq = cpu_get_pic_interrupt(env);
 859         if (irq >= 0) {
 860             struct kvm_interrupt intr;
 861             intr.irq = irq;
 862             /* FIXME: errors */
 863             dprintf("injected interrupt %d\n", irq);
 864             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 865         }
 866     }
 867
 868     /* If we have an interrupt but the guest is not ready to receive an
 869      * interrupt, request an interrupt window exit.  This will
 870      * cause a return to userspace as soon as the guest is ready to
 871      * receive interrupts. */
 872     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 873         run->request_interrupt_window = 1;
 874     else
 875         run->request_interrupt_window = 0;
 876
 877     dprintf("setting tpr\n");
 878     run->cr8 = cpu_get_apic_tpr(env);
 879
 880     return 0;
 881 }
 882 #endif
 883
 884 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 885 {
 886     if (run->if_flag)
 887         env->eflags |= IF_MASK;
 888     else
 889         env->eflags &= ~IF_MASK;
 890
 891     cpu_set_apic_tpr(env, run->cr8);
 892     cpu_set_apic_base(env, run->apic_base);
 893
 894     return 0;
 895 }
 896
 897 #ifdef KVM_UPSTREAM
 898 static int kvm_handle_halt(CPUState *env)
 899 {
 900     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 901           (env->eflags & IF_MASK)) &&
 902         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 903         env->halted = 1;
 904         env->exception_index = EXCP_HLT;
 905         return 0;
 906     }
 907
 908     return 1;
 909 }
 910
 911 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 912 {
 913     int ret = 0;
 914
 915     switch (run->exit_reason) {
 916     case KVM_EXIT_HLT:
 917         dprintf("handle_hlt\n");
 918         ret = kvm_handle_halt(env);
 919         break;
 920     }
 921
 922     return ret;
 923 }
 924
 925 #ifdef KVM_CAP_SET_GUEST_DEBUG
 926 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 927 {
 928     static const uint8_t int3 = 0xcc;
 929
 930     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 931         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
 932         return -EINVAL;
 933     return 0;
 934 }
 935
 936 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 937 {
 938     uint8_t int3;
 939
 940     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 941         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
 942         return -EINVAL;
 943     return 0;
 944 }
 945
 946 static struct {
 947     target_ulong addr;
 948     int len;
 949     int type;
 950 } hw_breakpoint[4];
 951
 952 static int nb_hw_breakpoint;
 953
 954 static int find_hw_breakpoint(target_ulong addr, int len, int type)
 955 {
 956     int n;
 957
 958     for (n = 0; n < nb_hw_breakpoint; n++)
 959         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
 960             (hw_breakpoint[n].len == len || len == -1))
 961             return n;
 962     return -1;
 963 }
 964
 965 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 966                                   target_ulong len, int type)
 967 {
 968     switch (type) {
 969     case GDB_BREAKPOINT_HW:
 970         len = 1;
 971         break;
 972     case GDB_WATCHPOINT_WRITE:
 973     case GDB_WATCHPOINT_ACCESS:
 974         switch (len) {
 975         case 1:
 976             break;
 977         case 2:
 978         case 4:
 979         case 8:
 980             if (addr & (len - 1))
 981                 return -EINVAL;
 982             break;
 983         default:
 984             return -EINVAL;
 985         }
 986         break;
 987     default:
 988         return -ENOSYS;
 989     }
 990
 991     if (nb_hw_breakpoint == 4)
 992         return -ENOBUFS;
 993
 994     if (find_hw_breakpoint(addr, len, type) >= 0)
 995         return -EEXIST;
 996
 997     hw_breakpoint[nb_hw_breakpoint].addr = addr;
 998     hw_breakpoint[nb_hw_breakpoint].len = len;
 999     hw_breakpoint[nb_hw_breakpoint].type = type;
1000     nb_hw_breakpoint++;
1001
1002     return 0;
1003 }
1004
1005 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1006                                   target_ulong len, int type)
1007 {
1008     int n;
1009
1010     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1011     if (n < 0)
1012         return -ENOENT;
1013
1014     nb_hw_breakpoint--;
1015     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1016
1017     return 0;
1018 }
1019
1020 void kvm_arch_remove_all_hw_breakpoints(void)
1021 {
1022     nb_hw_breakpoint = 0;
1023 }
1024
1025 static CPUWatchpoint hw_watchpoint;
1026
1027 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1028 {
1029     int handle = 0;
1030     int n;
1031
1032     if (arch_info->exception == 1) {
1033         if (arch_info->dr6 & (1 << 14)) {
1034             if (cpu_single_env->singlestep_enabled)
1035                 handle = 1;
1036         } else {
1037             for (n = 0; n < 4; n++)
1038                 if (arch_info->dr6 & (1 << n))
1039                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1040                     case 0x0:
1041                         handle = 1;
1042                         break;
1043                     case 0x1:
1044                         handle = 1;
1045                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1046                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1047                         hw_watchpoint.flags = BP_MEM_WRITE;
1048                         break;
1049                     case 0x3:
1050                         handle = 1;
1051                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1052                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1053                         hw_watchpoint.flags = BP_MEM_ACCESS;
1054                         break;
1055                     }
1056         }
1057     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1058         handle = 1;
1059
1060     if (!handle)
1061         kvm_update_guest_debug(cpu_single_env,
1062                         (arch_info->exception == 1) ?
1063                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1064
1065     return handle;
1066 }
1067
1068 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1069 {
1070     const uint8_t type_code[] = {
1071         [GDB_BREAKPOINT_HW] = 0x0,
1072         [GDB_WATCHPOINT_WRITE] = 0x1,
1073         [GDB_WATCHPOINT_ACCESS] = 0x3
1074     };
1075     const uint8_t len_code[] = {
1076         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1077     };
1078     int n;
1079
1080     if (kvm_sw_breakpoints_active(env))
1081         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1082
1083     if (nb_hw_breakpoint > 0) {
1084         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1085         dbg->arch.debugreg[7] = 0x0600;
1086         for (n = 0; n < nb_hw_breakpoint; n++) {
1087             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1088             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1089                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1090                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1091         }
1092     }
1093 }
1094 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1095 #endif
1096
1097 #include "qemu-kvm-x86.c"