target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27 #include "hw/pc.h"
  28 #include "ioport.h"
  29
  30 #ifdef CONFIG_KVM_PARA
  31 #include <linux/kvm_para.h>
  32 #endif
  33 //
  34 //#define DEBUG_KVM
  35
  36 #ifdef DEBUG_KVM
  37 #define DPRINTF(fmt, ...) \
  38     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  39 #else
  40 #define DPRINTF(fmt, ...) \
  41     do { } while (0)
  42 #endif
  43
  44 #define MSR_KVM_WALL_CLOCK  0x11
  45 #define MSR_KVM_SYSTEM_TIME 0x12
  46
  47 #ifdef KVM_CAP_EXT_CPUID
  48
  49 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  50 {
  51     struct kvm_cpuid2 *cpuid;
  52     int r, size;
  53
  54     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  55     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  56     cpuid->nent = max;
  57     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  58     if (r == 0 && cpuid->nent >= max) {
  59         r = -E2BIG;
  60     }
  61     if (r < 0) {
  62         if (r == -E2BIG) {
  63             qemu_free(cpuid);
  64             return NULL;
  65         } else {
  66             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  67                     strerror(-r));
  68             exit(1);
  69         }
  70     }
  71     return cpuid;
  72 }
  73
  74 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  75 {
  76     struct kvm_cpuid2 *cpuid;
  77     int i, max;
  78     uint32_t ret = 0;
  79     uint32_t cpuid_1_edx;
  80
  81     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  82         return -1U;
  83     }
  84
  85     max = 1;
  86     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  87         max *= 2;
  88     }
  89
  90     for (i = 0; i < cpuid->nent; ++i) {
  91         if (cpuid->entries[i].function == function) {
  92             switch (reg) {
  93             case R_EAX:
  94                 ret = cpuid->entries[i].eax;
  95                 break;
  96             case R_EBX:
  97                 ret = cpuid->entries[i].ebx;
  98                 break;
  99             case R_ECX:
 100                 ret = cpuid->entries[i].ecx;
 101                 break;
 102             case R_EDX:
 103                 ret = cpuid->entries[i].edx;
 104                 switch (function) {
 105                 case 1:
 106                     /* KVM before 2.6.30 misreports the following features */
 107                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 108                     break;
 109                 case 0x80000001:
 110                     /* On Intel, kvm returns cpuid according to the Intel spec,
 111                      * so add missing bits according to the AMD spec:
 112                      */
 113                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
 114                     ret |= cpuid_1_edx & 0x183f7ff;
 115                     break;
 116                 }
 117                 break;
 118             }
 119         }
 120     }
 121
 122     qemu_free(cpuid);
 123
 124     return ret;
 125 }
 126
 127 #else
 128
 129 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 130 {
 131     return -1U;
 132 }
 133
 134 #endif
 135
 136 #ifdef KVM_UPSTREAM
 137
 138 #ifdef CONFIG_KVM_PARA
 139 struct kvm_para_features {
 140         int cap;
 141         int feature;
 142 } para_features[] = {
 143 #ifdef KVM_CAP_CLOCKSOURCE
 144         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 145 #endif
 146 #ifdef KVM_CAP_NOP_IO_DELAY
 147         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 148 #endif
 149 #ifdef KVM_CAP_PV_MMU
 150         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 151 #endif
 152         { -1, -1 }
 153 };
 154
 155 static int get_para_features(CPUState *env)
 156 {
 157         int i, features = 0;
 158
 159         for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 160                 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
 161                         features |= (1 << para_features[i].feature);
 162         }
 163
 164         return features;
 165 }
 166 #endif
 167
 168 int kvm_arch_init_vcpu(CPUState *env)
 169 {
 170     struct {
 171         struct kvm_cpuid2 cpuid;
 172         struct kvm_cpuid_entry2 entries[100];
 173     } __attribute__((packed)) cpuid_data;
 174     uint32_t limit, i, j, cpuid_i;
 175     uint32_t unused;
 176     struct kvm_cpuid_entry2 *c;
 177 #ifdef KVM_CPUID_SIGNATURE
 178     uint32_t signature[3];
 179 #endif
 180
 181     env->mp_state = KVM_MP_STATE_RUNNABLE;
 182
 183     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, R_EDX);
 184
 185     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 186     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, R_ECX);
 187     env->cpuid_ext_features |= i;
 188
 189     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 190                                                              R_EDX);
 191     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 192                                                              R_ECX);
 193
 194     cpuid_i = 0;
 195
 196 #ifdef CONFIG_KVM_PARA
 197     /* Paravirtualization CPUIDs */
 198     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 199     c = &cpuid_data.entries[cpuid_i++];
 200     memset(c, 0, sizeof(*c));
 201     c->function = KVM_CPUID_SIGNATURE;
 202     c->eax = 0;
 203     c->ebx = signature[0];
 204     c->ecx = signature[1];
 205     c->edx = signature[2];
 206
 207     c = &cpuid_data.entries[cpuid_i++];
 208     memset(c, 0, sizeof(*c));
 209     c->function = KVM_CPUID_FEATURES;
 210     c->eax = env->cpuid_kvm_features & get_para_features(env);
 211 #endif
 212
 213     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 214
 215     for (i = 0; i <= limit; i++) {
 216         c = &cpuid_data.entries[cpuid_i++];
 217
 218         switch (i) {
 219         case 2: {
 220             /* Keep reading function 2 till all the input is received */
 221             int times;
 222
 223             c->function = i;
 224             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 225                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 226             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 227             times = c->eax & 0xff;
 228
 229             for (j = 1; j < times; ++j) {
 230                 c = &cpuid_data.entries[cpuid_i++];
 231                 c->function = i;
 232                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 233                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 234             }
 235             break;
 236         }
 237         case 4:
 238         case 0xb:
 239         case 0xd:
 240             for (j = 0; ; j++) {
 241                 c->function = i;
 242                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 243                 c->index = j;
 244                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 245
 246                 if (i == 4 && c->eax == 0)
 247                     break;
 248                 if (i == 0xb && !(c->ecx & 0xff00))
 249                     break;
 250                 if (i == 0xd && c->eax == 0)
 251                     break;
 252
 253                 c = &cpuid_data.entries[cpuid_i++];
 254             }
 255             break;
 256         default:
 257             c->function = i;
 258             c->flags = 0;
 259             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 260             break;
 261         }
 262     }
 263     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 264
 265     for (i = 0x80000000; i <= limit; i++) {
 266         c = &cpuid_data.entries[cpuid_i++];
 267
 268         c->function = i;
 269         c->flags = 0;
 270         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 271     }
 272
 273     cpuid_data.cpuid.nent = cpuid_i;
 274
 275     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 276 }
 277
 278 #endif
 279 void kvm_arch_reset_vcpu(CPUState *env)
 280 {
 281     env->exception_injected = -1;
 282     env->interrupt_injected = -1;
 283     env->nmi_injected = 0;
 284     env->nmi_pending = 0;
 285 }
 286 #ifdef KVM_UPSTREAM
 287
 288 static int kvm_has_msr_star(CPUState *env)
 289 {
 290     static int has_msr_star;
 291     int ret;
 292
 293     /* first time */
 294     if (has_msr_star == 0) {
 295         struct kvm_msr_list msr_list, *kvm_msr_list;
 296
 297         has_msr_star = -1;
 298
 299         /* Obtain MSR list from KVM.  These are the MSRs that we must
 300          * save/restore */
 301         msr_list.nmsrs = 0;
 302         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 303         if (ret < 0 && ret != -E2BIG) {
 304             return 0;
 305         }
 306         /* Old kernel modules had a bug and could write beyond the provided
 307            memory. Allocate at least a safe amount of 1K. */
 308         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 309                                               msr_list.nmsrs *
 310                                               sizeof(msr_list.indices[0])));
 311
 312         kvm_msr_list->nmsrs = msr_list.nmsrs;
 313         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 314         if (ret >= 0) {
 315             int i;
 316
 317             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 318                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 319                     has_msr_star = 1;
 320                     break;
 321                 }
 322             }
 323         }
 324
 325         free(kvm_msr_list);
 326     }
 327
 328     if (has_msr_star == 1)
 329         return 1;
 330     return 0;
 331 }
 332
 333 static int kvm_init_identity_map_page(KVMState *s)
 334 {
 335 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 336     int ret;
 337     uint64_t addr = 0xfffbc000;
 338
 339     if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 340         return 0;
 341     }
 342
 343     ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
 344     if (ret < 0) {
 345         fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
 346         return ret;
 347     }
 348 #endif
 349     return 0;
 350 }
 351
 352 int kvm_arch_init(KVMState *s, int smp_cpus)
 353 {
 354     int ret;
 355
 356     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 357      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 358      * must be part of guest physical memory, we need to allocate it.  Older
 359      * versions of KVM just assumed that it would be at the end of physical
 360      * memory but that doesn't work with more than 4GB of memory.  We simply
 361      * refuse to work with those older versions of KVM. */
 362     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 363     if (ret <= 0) {
 364         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 365         return ret;
 366     }
 367
 368     /* this address is 3 pages before the bios, and the bios should present
 369      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 370      * this?
 371      */
 372     /*
 373      * Tell fw_cfg to notify the BIOS to reserve the range.
 374      */
 375     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 376         perror("e820_add_entry() table is full");
 377         exit(1);
 378     }
 379     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 380     if (ret < 0) {
 381         return ret;
 382     }
 383
 384     return kvm_init_identity_map_page(s);
 385 }
 386
 387 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 388 {
 389     lhs->selector = rhs->selector;
 390     lhs->base = rhs->base;
 391     lhs->limit = rhs->limit;
 392     lhs->type = 3;
 393     lhs->present = 1;
 394     lhs->dpl = 3;
 395     lhs->db = 0;
 396     lhs->s = 1;
 397     lhs->l = 0;
 398     lhs->g = 0;
 399     lhs->avl = 0;
 400     lhs->unusable = 0;
 401 }
 402
 403 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 404 {
 405     unsigned flags = rhs->flags;
 406     lhs->selector = rhs->selector;
 407     lhs->base = rhs->base;
 408     lhs->limit = rhs->limit;
 409     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 410     lhs->present = (flags & DESC_P_MASK) != 0;
 411     lhs->dpl = rhs->selector & 3;
 412     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 413     lhs->s = (flags & DESC_S_MASK) != 0;
 414     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 415     lhs->g = (flags & DESC_G_MASK) != 0;
 416     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 417     lhs->unusable = 0;
 418 }
 419
 420 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 421 {
 422     lhs->selector = rhs->selector;
 423     lhs->base = rhs->base;
 424     lhs->limit = rhs->limit;
 425     lhs->flags =
 426         (rhs->type << DESC_TYPE_SHIFT)
 427         | (rhs->present * DESC_P_MASK)
 428         | (rhs->dpl << DESC_DPL_SHIFT)
 429         | (rhs->db << DESC_B_SHIFT)
 430         | (rhs->s * DESC_S_MASK)
 431         | (rhs->l << DESC_L_SHIFT)
 432         | (rhs->g * DESC_G_MASK)
 433         | (rhs->avl * DESC_AVL_MASK);
 434 }
 435
 436 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 437 {
 438     if (set)
 439         *kvm_reg = *qemu_reg;
 440     else
 441         *qemu_reg = *kvm_reg;
 442 }
 443
 444 static int kvm_getput_regs(CPUState *env, int set)
 445 {
 446     struct kvm_regs regs;
 447     int ret = 0;
 448
 449     if (!set) {
 450         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 451         if (ret < 0)
 452             return ret;
 453     }
 454
 455     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 456     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 457     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 458     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 459     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 460     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 461     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 462     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 463 #ifdef TARGET_X86_64
 464     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 465     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 466     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 467     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 468     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 469     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 470     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 471     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 472 #endif
 473
 474     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 475     kvm_getput_reg(&regs.rip, &env->eip, set);
 476
 477     if (set)
 478         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 479
 480     return ret;
 481 }
 482
 483 static int kvm_put_fpu(CPUState *env)
 484 {
 485     struct kvm_fpu fpu;
 486     int i;
 487
 488     memset(&fpu, 0, sizeof fpu);
 489     fpu.fsw = env->fpus & ~(7 << 11);
 490     fpu.fsw |= (env->fpstt & 7) << 11;
 491     fpu.fcw = env->fpuc;
 492     for (i = 0; i < 8; ++i)
 493         fpu.ftwx |= (!env->fptags[i]) << i;
 494     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 495     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 496     fpu.mxcsr = env->mxcsr;
 497
 498     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 499 }
 500
 501 static int kvm_put_sregs(CPUState *env)
 502 {
 503     struct kvm_sregs sregs;
 504
 505     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 506     if (env->interrupt_injected >= 0) {
 507         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 508                 (uint64_t)1 << (env->interrupt_injected % 64);
 509     }
 510
 511     if ((env->eflags & VM_MASK)) {
 512             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 513             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 514             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 515             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 516             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 517             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 518     } else {
 519             set_seg(&sregs.cs, &env->segs[R_CS]);
 520             set_seg(&sregs.ds, &env->segs[R_DS]);
 521             set_seg(&sregs.es, &env->segs[R_ES]);
 522             set_seg(&sregs.fs, &env->segs[R_FS]);
 523             set_seg(&sregs.gs, &env->segs[R_GS]);
 524             set_seg(&sregs.ss, &env->segs[R_SS]);
 525
 526             if (env->cr[0] & CR0_PE_MASK) {
 527                 /* force ss cpl to cs cpl */
 528                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 529                         (sregs.cs.selector & 3);
 530                 sregs.ss.dpl = sregs.ss.selector & 3;
 531             }
 532     }
 533
 534     set_seg(&sregs.tr, &env->tr);
 535     set_seg(&sregs.ldt, &env->ldt);
 536
 537     sregs.idt.limit = env->idt.limit;
 538     sregs.idt.base = env->idt.base;
 539     sregs.gdt.limit = env->gdt.limit;
 540     sregs.gdt.base = env->gdt.base;
 541
 542     sregs.cr0 = env->cr[0];
 543     sregs.cr2 = env->cr[2];
 544     sregs.cr3 = env->cr[3];
 545     sregs.cr4 = env->cr[4];
 546
 547     sregs.cr8 = cpu_get_apic_tpr(env);
 548     sregs.apic_base = cpu_get_apic_base(env);
 549
 550     sregs.efer = env->efer;
 551
 552     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 553 }
 554
 555 #endif
 556
 557 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 558                               uint32_t index, uint64_t value)
 559 {
 560     entry->index = index;
 561     entry->data = value;
 562 }
 563
 564 #ifdef KVM_UPSTREAM
 565 static int kvm_put_msrs(CPUState *env, int level)
 566 {
 567     struct {
 568         struct kvm_msrs info;
 569         struct kvm_msr_entry entries[100];
 570     } msr_data;
 571     struct kvm_msr_entry *msrs = msr_data.entries;
 572     int n = 0;
 573
 574     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 575     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 576     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 577     if (kvm_has_msr_star(env))
 578         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 579     kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 580 #ifdef TARGET_X86_64
 581     /* FIXME if lm capable */
 582     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 583     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 584     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 585     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 586 #endif
 587     if (level == KVM_PUT_FULL_STATE) {
 588         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 589         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 590                           env->system_time_msr);
 591         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 592     }
 593
 594     msr_data.info.nmsrs = n;
 595
 596     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 597
 598 }
 599
 600
 601 static int kvm_get_fpu(CPUState *env)
 602 {
 603     struct kvm_fpu fpu;
 604     int i, ret;
 605
 606     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 607     if (ret < 0)
 608         return ret;
 609
 610     env->fpstt = (fpu.fsw >> 11) & 7;
 611     env->fpus = fpu.fsw;
 612     env->fpuc = fpu.fcw;
 613     for (i = 0; i < 8; ++i)
 614         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 615     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 616     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 617     env->mxcsr = fpu.mxcsr;
 618
 619     return 0;
 620 }
 621
 622 static int kvm_get_sregs(CPUState *env)
 623 {
 624     struct kvm_sregs sregs;
 625     uint32_t hflags;
 626     int bit, i, ret;
 627
 628     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 629     if (ret < 0)
 630         return ret;
 631
 632     /* There can only be one pending IRQ set in the bitmap at a time, so try
 633        to find it and save its number instead (-1 for none). */
 634     env->interrupt_injected = -1;
 635     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 636         if (sregs.interrupt_bitmap[i]) {
 637             bit = ctz64(sregs.interrupt_bitmap[i]);
 638             env->interrupt_injected = i * 64 + bit;
 639             break;
 640         }
 641     }
 642
 643     get_seg(&env->segs[R_CS], &sregs.cs);
 644     get_seg(&env->segs[R_DS], &sregs.ds);
 645     get_seg(&env->segs[R_ES], &sregs.es);
 646     get_seg(&env->segs[R_FS], &sregs.fs);
 647     get_seg(&env->segs[R_GS], &sregs.gs);
 648     get_seg(&env->segs[R_SS], &sregs.ss);
 649
 650     get_seg(&env->tr, &sregs.tr);
 651     get_seg(&env->ldt, &sregs.ldt);
 652
 653     env->idt.limit = sregs.idt.limit;
 654     env->idt.base = sregs.idt.base;
 655     env->gdt.limit = sregs.gdt.limit;
 656     env->gdt.base = sregs.gdt.base;
 657
 658     env->cr[0] = sregs.cr0;
 659     env->cr[2] = sregs.cr2;
 660     env->cr[3] = sregs.cr3;
 661     env->cr[4] = sregs.cr4;
 662
 663     cpu_set_apic_base(env, sregs.apic_base);
 664
 665     env->efer = sregs.efer;
 666     //cpu_set_apic_tpr(env, sregs.cr8);
 667
 668 #define HFLAG_COPY_MASK ~( \
 669                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 670                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 671                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 672                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 673
 674
 675
 676     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 677     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 678     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 679             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 680     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 681     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 682             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 683
 684     if (env->efer & MSR_EFER_LMA) {
 685         hflags |= HF_LMA_MASK;
 686     }
 687
 688     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 689         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 690     } else {
 691         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 692                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 693         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 694                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 695         if (!(env->cr[0] & CR0_PE_MASK) ||
 696                    (env->eflags & VM_MASK) ||
 697                    !(hflags & HF_CS32_MASK)) {
 698                 hflags |= HF_ADDSEG_MASK;
 699             } else {
 700                 hflags |= ((env->segs[R_DS].base |
 701                                 env->segs[R_ES].base |
 702                                 env->segs[R_SS].base) != 0) <<
 703                     HF_ADDSEG_SHIFT;
 704             }
 705     }
 706     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 707
 708     return 0;
 709 }
 710
 711 static int kvm_get_msrs(CPUState *env)
 712 {
 713     struct {
 714         struct kvm_msrs info;
 715         struct kvm_msr_entry entries[100];
 716     } msr_data;
 717     struct kvm_msr_entry *msrs = msr_data.entries;
 718     int ret, i, n;
 719
 720     n = 0;
 721     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 722     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 723     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 724     if (kvm_has_msr_star(env))
 725         msrs[n++].index = MSR_STAR;
 726     msrs[n++].index = MSR_IA32_TSC;
 727     msrs[n++].index = MSR_VM_HSAVE_PA;
 728 #ifdef TARGET_X86_64
 729     /* FIXME lm_capable_kernel */
 730     msrs[n++].index = MSR_CSTAR;
 731     msrs[n++].index = MSR_KERNELGSBASE;
 732     msrs[n++].index = MSR_FMASK;
 733     msrs[n++].index = MSR_LSTAR;
 734 #endif
 735     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
 736     msrs[n++].index = MSR_KVM_WALL_CLOCK;
 737
 738     msr_data.info.nmsrs = n;
 739     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 740     if (ret < 0)
 741         return ret;
 742
 743     for (i = 0; i < ret; i++) {
 744         switch (msrs[i].index) {
 745         case MSR_IA32_SYSENTER_CS:
 746             env->sysenter_cs = msrs[i].data;
 747             break;
 748         case MSR_IA32_SYSENTER_ESP:
 749             env->sysenter_esp = msrs[i].data;
 750             break;
 751         case MSR_IA32_SYSENTER_EIP:
 752             env->sysenter_eip = msrs[i].data;
 753             break;
 754         case MSR_STAR:
 755             env->star = msrs[i].data;
 756             break;
 757 #ifdef TARGET_X86_64
 758         case MSR_CSTAR:
 759             env->cstar = msrs[i].data;
 760             break;
 761         case MSR_KERNELGSBASE:
 762             env->kernelgsbase = msrs[i].data;
 763             break;
 764         case MSR_FMASK:
 765             env->fmask = msrs[i].data;
 766             break;
 767         case MSR_LSTAR:
 768             env->lstar = msrs[i].data;
 769             break;
 770 #endif
 771         case MSR_IA32_TSC:
 772             env->tsc = msrs[i].data;
 773             break;
 774         case MSR_KVM_SYSTEM_TIME:
 775             env->system_time_msr = msrs[i].data;
 776             break;
 777         case MSR_KVM_WALL_CLOCK:
 778             env->wall_clock_msr = msrs[i].data;
 779             break;
 780         case MSR_VM_HSAVE_PA:
 781             env->vm_hsave = msrs[i].data;
 782             break;
 783         }
 784     }
 785
 786     return 0;
 787 }
 788
 789 static int kvm_put_mp_state(CPUState *env)
 790 {
 791     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 792
 793     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
 794 }
 795
 796 static int kvm_get_mp_state(CPUState *env)
 797 {
 798     struct kvm_mp_state mp_state;
 799     int ret;
 800
 801     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
 802     if (ret < 0) {
 803         return ret;
 804     }
 805     env->mp_state = mp_state.mp_state;
 806     return 0;
 807 }
 808 #endif
 809
 810 static int kvm_put_vcpu_events(CPUState *env, int level)
 811 {
 812 #ifdef KVM_CAP_VCPU_EVENTS
 813     struct kvm_vcpu_events events;
 814
 815     if (!kvm_has_vcpu_events()) {
 816         return 0;
 817     }
 818
 819     events.exception.injected = (env->exception_injected >= 0);
 820     events.exception.nr = env->exception_injected;
 821     events.exception.has_error_code = env->has_error_code;
 822     events.exception.error_code = env->error_code;
 823
 824     events.interrupt.injected = (env->interrupt_injected >= 0);
 825     events.interrupt.nr = env->interrupt_injected;
 826     events.interrupt.soft = env->soft_interrupt;
 827
 828     events.nmi.injected = env->nmi_injected;
 829     events.nmi.pending = env->nmi_pending;
 830     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
 831
 832     events.sipi_vector = env->sipi_vector;
 833
 834     events.flags = 0;
 835     if (level >= KVM_PUT_RESET_STATE) {
 836         events.flags |=
 837             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
 838     }
 839
 840     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
 841 #else
 842     return 0;
 843 #endif
 844 }
 845
 846 static int kvm_get_vcpu_events(CPUState *env)
 847 {
 848 #ifdef KVM_CAP_VCPU_EVENTS
 849     struct kvm_vcpu_events events;
 850     int ret;
 851
 852     if (!kvm_has_vcpu_events()) {
 853         return 0;
 854     }
 855
 856     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
 857     if (ret < 0) {
 858        return ret;
 859     }
 860     env->exception_injected =
 861        events.exception.injected ? events.exception.nr : -1;
 862     env->has_error_code = events.exception.has_error_code;
 863     env->error_code = events.exception.error_code;
 864
 865     env->interrupt_injected =
 866         events.interrupt.injected ? events.interrupt.nr : -1;
 867     env->soft_interrupt = events.interrupt.soft;
 868
 869     env->nmi_injected = events.nmi.injected;
 870     env->nmi_pending = events.nmi.pending;
 871     if (events.nmi.masked) {
 872         env->hflags2 |= HF2_NMI_MASK;
 873     } else {
 874         env->hflags2 &= ~HF2_NMI_MASK;
 875     }
 876
 877     env->sipi_vector = events.sipi_vector;
 878 #endif
 879
 880     return 0;
 881 }
 882
 883 static int kvm_guest_debug_workarounds(CPUState *env)
 884 {
 885     int ret = 0;
 886 #ifdef KVM_CAP_SET_GUEST_DEBUG
 887     unsigned long reinject_trap = 0;
 888
 889     if (!kvm_has_vcpu_events()) {
 890         if (env->exception_injected == 1) {
 891             reinject_trap = KVM_GUESTDBG_INJECT_DB;
 892         } else if (env->exception_injected == 3) {
 893             reinject_trap = KVM_GUESTDBG_INJECT_BP;
 894         }
 895         env->exception_injected = -1;
 896     }
 897
 898     /*
 899      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
 900      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
 901      * by updating the debug state once again if single-stepping is on.
 902      * Another reason to call kvm_update_guest_debug here is a pending debug
 903      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
 904      * reinject them via SET_GUEST_DEBUG.
 905      */
 906     if (reinject_trap ||
 907         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
 908         ret = kvm_update_guest_debug(env, reinject_trap);
 909     }
 910 #endif /* KVM_CAP_SET_GUEST_DEBUG */
 911     return ret;
 912 }
 913
 914 static int kvm_put_debugregs(CPUState *env)
 915 {
 916 #ifdef KVM_CAP_DEBUGREGS
 917     struct kvm_debugregs dbgregs;
 918     int i;
 919
 920     if (!kvm_has_debugregs()) {
 921         return 0;
 922     }
 923
 924     for (i = 0; i < 4; i++) {
 925         dbgregs.db[i] = env->dr[i];
 926     }
 927     dbgregs.dr6 = env->dr[6];
 928     dbgregs.dr7 = env->dr[7];
 929     dbgregs.flags = 0;
 930
 931     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
 932 #else
 933     return 0;
 934 #endif
 935 }
 936
 937 static int kvm_get_debugregs(CPUState *env)
 938 {
 939 #ifdef KVM_CAP_DEBUGREGS
 940     struct kvm_debugregs dbgregs;
 941     int i, ret;
 942
 943     if (!kvm_has_debugregs()) {
 944         return 0;
 945     }
 946
 947     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
 948     if (ret < 0) {
 949        return ret;
 950     }
 951     for (i = 0; i < 4; i++) {
 952         env->dr[i] = dbgregs.db[i];
 953     }
 954     env->dr[4] = env->dr[6] = dbgregs.dr6;
 955     env->dr[5] = env->dr[7] = dbgregs.dr7;
 956 #endif
 957
 958     return 0;
 959 }
 960
 961 #ifdef KVM_UPSTREAM
 962 int kvm_arch_put_registers(CPUState *env, int level)
 963 {
 964     int ret;
 965
 966     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
 967
 968     ret = kvm_getput_regs(env, 1);
 969     if (ret < 0)
 970         return ret;
 971
 972     ret = kvm_put_fpu(env);
 973     if (ret < 0)
 974         return ret;
 975
 976     ret = kvm_put_sregs(env);
 977     if (ret < 0)
 978         return ret;
 979
 980     ret = kvm_put_msrs(env, level);
 981     if (ret < 0)
 982         return ret;
 983
 984     if (level >= KVM_PUT_RESET_STATE) {
 985         ret = kvm_put_mp_state(env);
 986         if (ret < 0)
 987             return ret;
 988     }
 989
 990     ret = kvm_put_vcpu_events(env, level);
 991     if (ret < 0)
 992         return ret;
 993
 994     /* must be last */
 995     ret = kvm_guest_debug_workarounds(env);
 996     if (ret < 0)
 997         return ret;
 998
 999     ret = kvm_put_debugregs(env);
1000     if (ret < 0)
1001         return ret;
1002
1003     return 0;
1004 }
1005
1006 int kvm_arch_get_registers(CPUState *env)
1007 {
1008     int ret;
1009
1010     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1011
1012     ret = kvm_getput_regs(env, 0);
1013     if (ret < 0)
1014         return ret;
1015
1016     ret = kvm_get_fpu(env);
1017     if (ret < 0)
1018         return ret;
1019
1020     ret = kvm_get_sregs(env);
1021     if (ret < 0)
1022         return ret;
1023
1024     ret = kvm_get_msrs(env);
1025     if (ret < 0)
1026         return ret;
1027
1028     ret = kvm_get_mp_state(env);
1029     if (ret < 0)
1030         return ret;
1031
1032     ret = kvm_get_vcpu_events(env);
1033     if (ret < 0)
1034         return ret;
1035
1036     ret = kvm_get_debugregs(env);
1037     if (ret < 0)
1038         return ret;
1039
1040     return 0;
1041 }
1042
1043 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1044 {
1045     /* Try to inject an interrupt if the guest can accept it */
1046     if (run->ready_for_interrupt_injection &&
1047         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1048         (env->eflags & IF_MASK)) {
1049         int irq;
1050
1051         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1052         irq = cpu_get_pic_interrupt(env);
1053         if (irq >= 0) {
1054             struct kvm_interrupt intr;
1055             intr.irq = irq;
1056             /* FIXME: errors */
1057             DPRINTF("injected interrupt %d\n", irq);
1058             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1059         }
1060     }
1061
1062     /* If we have an interrupt but the guest is not ready to receive an
1063      * interrupt, request an interrupt window exit.  This will
1064      * cause a return to userspace as soon as the guest is ready to
1065      * receive interrupts. */
1066     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1067         run->request_interrupt_window = 1;
1068     else
1069         run->request_interrupt_window = 0;
1070
1071     DPRINTF("setting tpr\n");
1072     run->cr8 = cpu_get_apic_tpr(env);
1073
1074     return 0;
1075 }
1076 #endif
1077
1078 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1079 {
1080     if (run->if_flag)
1081         env->eflags |= IF_MASK;
1082     else
1083         env->eflags &= ~IF_MASK;
1084
1085     cpu_set_apic_tpr(env, run->cr8);
1086     cpu_set_apic_base(env, run->apic_base);
1087
1088     return 0;
1089 }
1090
1091 #ifdef KVM_UPSTREAM
1092
1093 int kvm_arch_process_irqchip_events(CPUState *env)
1094 {
1095     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1096         kvm_cpu_synchronize_state(env);
1097         do_cpu_init(env);
1098         env->exception_index = EXCP_HALTED;
1099     }
1100
1101     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1102         kvm_cpu_synchronize_state(env);
1103         do_cpu_sipi(env);
1104     }
1105
1106     return env->halted;
1107 }
1108
1109 static int kvm_handle_halt(CPUState *env)
1110 {
1111     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1112           (env->eflags & IF_MASK)) &&
1113         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1114         env->halted = 1;
1115         env->exception_index = EXCP_HLT;
1116         return 0;
1117     }
1118
1119     return 1;
1120 }
1121
1122 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1123 {
1124     int ret = 0;
1125
1126     switch (run->exit_reason) {
1127     case KVM_EXIT_HLT:
1128         DPRINTF("handle_hlt\n");
1129         ret = kvm_handle_halt(env);
1130         break;
1131     }
1132
1133     return ret;
1134 }
1135 #endif
1136
1137 #ifdef KVM_CAP_SET_GUEST_DEBUG
1138 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1139 {
1140     static const uint8_t int3 = 0xcc;
1141
1142     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1143         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
1144         return -EINVAL;
1145     return 0;
1146 }
1147
1148 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1149 {
1150     uint8_t int3;
1151
1152     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1153         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1154         return -EINVAL;
1155     return 0;
1156 }
1157
1158 static struct {
1159     target_ulong addr;
1160     int len;
1161     int type;
1162 } hw_breakpoint[4];
1163
1164 static int nb_hw_breakpoint;
1165
1166 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1167 {
1168     int n;
1169
1170     for (n = 0; n < nb_hw_breakpoint; n++)
1171         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1172             (hw_breakpoint[n].len == len || len == -1))
1173             return n;
1174     return -1;
1175 }
1176
1177 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1178                                   target_ulong len, int type)
1179 {
1180     switch (type) {
1181     case GDB_BREAKPOINT_HW:
1182         len = 1;
1183         break;
1184     case GDB_WATCHPOINT_WRITE:
1185     case GDB_WATCHPOINT_ACCESS:
1186         switch (len) {
1187         case 1:
1188             break;
1189         case 2:
1190         case 4:
1191         case 8:
1192             if (addr & (len - 1))
1193                 return -EINVAL;
1194             break;
1195         default:
1196             return -EINVAL;
1197         }
1198         break;
1199     default:
1200         return -ENOSYS;
1201     }
1202
1203     if (nb_hw_breakpoint == 4)
1204         return -ENOBUFS;
1205
1206     if (find_hw_breakpoint(addr, len, type) >= 0)
1207         return -EEXIST;
1208
1209     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1210     hw_breakpoint[nb_hw_breakpoint].len = len;
1211     hw_breakpoint[nb_hw_breakpoint].type = type;
1212     nb_hw_breakpoint++;
1213
1214     return 0;
1215 }
1216
1217 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1218                                   target_ulong len, int type)
1219 {
1220     int n;
1221
1222     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1223     if (n < 0)
1224         return -ENOENT;
1225
1226     nb_hw_breakpoint--;
1227     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1228
1229     return 0;
1230 }
1231
1232 void kvm_arch_remove_all_hw_breakpoints(void)
1233 {
1234     nb_hw_breakpoint = 0;
1235 }
1236
1237 static CPUWatchpoint hw_watchpoint;
1238
1239 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1240 {
1241     int handle = 0;
1242     int n;
1243
1244     if (arch_info->exception == 1) {
1245         if (arch_info->dr6 & (1 << 14)) {
1246             if (cpu_single_env->singlestep_enabled)
1247                 handle = 1;
1248         } else {
1249             for (n = 0; n < 4; n++)
1250                 if (arch_info->dr6 & (1 << n))
1251                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1252                     case 0x0:
1253                         handle = 1;
1254                         break;
1255                     case 0x1:
1256                         handle = 1;
1257                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1258                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1259                         hw_watchpoint.flags = BP_MEM_WRITE;
1260                         break;
1261                     case 0x3:
1262                         handle = 1;
1263                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1264                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1265                         hw_watchpoint.flags = BP_MEM_ACCESS;
1266                         break;
1267                     }
1268         }
1269     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1270         handle = 1;
1271
1272     if (!handle) {
1273         cpu_synchronize_state(cpu_single_env);
1274         assert(cpu_single_env->exception_injected == -1);
1275
1276         cpu_single_env->exception_injected = arch_info->exception;
1277         cpu_single_env->has_error_code = 0;
1278     }
1279
1280     return handle;
1281 }
1282
1283 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1284 {
1285     const uint8_t type_code[] = {
1286         [GDB_BREAKPOINT_HW] = 0x0,
1287         [GDB_WATCHPOINT_WRITE] = 0x1,
1288         [GDB_WATCHPOINT_ACCESS] = 0x3
1289     };
1290     const uint8_t len_code[] = {
1291         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1292     };
1293     int n;
1294
1295     if (kvm_sw_breakpoints_active(env))
1296         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1297
1298     if (nb_hw_breakpoint > 0) {
1299         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1300         dbg->arch.debugreg[7] = 0x0600;
1301         for (n = 0; n < nb_hw_breakpoint; n++) {
1302             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1303             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1304                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1305                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1306         }
1307     }
1308 }
1309 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1310
1311 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1312 {
1313       return !(env->cr[0] & CR0_PE_MASK) ||
1314               ((env->segs[R_CS].selector  & 3) != 3);
1315 }
1316
1317 #include "qemu-kvm-x86.c"