2 * CFI parallel flash with AMD command set emulation
4 * Copyright (c) 2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
29 * - unlock bypass command
32 * It does not support flash interleaving.
33 * It does not implement boot blocs with reduced size
34 * It does not implement software data protection as found in many real chips
35 * It does not implement erase suspend/resume commands
36 * It does not implement multiple sectors erase
41 #include "qemu-timer.h"
44 //#define PFLASH_DEBUG
46 #define DPRINTF(fmt, args...) \
48 printf("PFLASH: " fmt , ##args); \
51 #define DPRINTF(fmt, args...) do { } while (0)
56 target_phys_addr_t base
;
61 int wcycle
; /* if 0, the flash is read normally */
67 uint16_t unlock_addr
[2];
69 uint8_t cfi_table
[0x52];
77 static void pflash_register_memory(pflash_t
*pfl
, int rom_mode
)
79 unsigned long phys_offset
= pfl
->fl_mem
;
83 phys_offset
|= pfl
->off
| IO_MEM_ROMD
;
84 pfl
->rom_mode
= rom_mode
;
86 for (i
= 0; i
< pfl
->mappings
; i
++)
87 cpu_register_physical_memory(pfl
->base
+ i
* pfl
->chip_len
,
88 pfl
->chip_len
, phys_offset
);
91 static void pflash_timer (void *opaque
)
93 pflash_t
*pfl
= opaque
;
95 DPRINTF("%s: command %02x done\n", __func__
, pfl
->cmd
);
101 pflash_register_memory(pfl
, 1);
107 static uint32_t pflash_read (pflash_t
*pfl
, uint32_t offset
, int width
)
113 DPRINTF("%s: offset " TARGET_FMT_lx
"\n", __func__
, offset
);
116 offset
-= (uint32_t)(long)pfl
->storage
;
117 /* Lazy reset of to ROMD mode */
118 if (pfl
->wcycle
== 0)
119 pflash_register_memory(pfl
, 1);
122 offset
&= pfl
->chip_len
- 1;
123 boff
= offset
& 0xFF;
126 else if (pfl
->width
== 4)
130 /* This should never happen : reset state & treat it as a read*/
131 DPRINTF("%s: unknown command state: %x\n", __func__
, pfl
->cmd
);
135 /* We accept reads during second unlock sequence... */
138 /* Flash area read */
143 // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
146 #if defined(TARGET_WORDS_BIGENDIAN)
147 ret
= p
[offset
] << 8;
148 ret
|= p
[offset
+ 1];
151 ret
|= p
[offset
+ 1] << 8;
153 // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
156 #if defined(TARGET_WORDS_BIGENDIAN)
157 ret
= p
[offset
] << 24;
158 ret
|= p
[offset
+ 1] << 16;
159 ret
|= p
[offset
+ 2] << 8;
160 ret
|= p
[offset
+ 3];
163 ret
|= p
[offset
+ 1] << 8;
164 ret
|= p
[offset
+ 2] << 16;
165 ret
|= p
[offset
+ 3] << 24;
167 // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
176 ret
= pfl
->ident
[boff
& 0x01];
179 ret
= 0x00; /* Pretend all sectors are unprotected */
183 if (pfl
->ident
[2 + (boff
& 0x01)] == (uint8_t)-1)
185 ret
= pfl
->ident
[2 + (boff
& 0x01)];
190 DPRINTF("%s: ID " TARGET_FMT_ld
" %x\n", __func__
, boff
, ret
);
195 /* Status register read */
197 DPRINTF("%s: status %x\n", __func__
, ret
);
203 if (boff
> pfl
->cfi_len
)
206 ret
= pfl
->cfi_table
[boff
];
213 /* update flash content on disk */
214 static void pflash_update(pflash_t
*pfl
, int offset
,
219 offset_end
= offset
+ size
;
220 /* round to sectors */
221 offset
= offset
>> 9;
222 offset_end
= (offset_end
+ 511) >> 9;
223 bdrv_write(pfl
->bs
, offset
, pfl
->storage
+ (offset
<< 9),
224 offset_end
- offset
);
228 static void pflash_write (pflash_t
*pfl
, uint32_t offset
, uint32_t value
,
236 if (pfl
->cmd
!= 0xA0 && cmd
== 0xF0) {
238 DPRINTF("%s: flash reset asked (%02x %02x)\n",
239 __func__
, pfl
->cmd
, cmd
);
243 DPRINTF("%s: offset " TARGET_FMT_lx
" %08x %d %d\n", __func__
,
244 offset
, value
, width
, pfl
->wcycle
);
245 /* WARNING: when the memory area is in ROMD mode, the offset is a
246 ram offset, not a physical address */
248 offset
-= (uint32_t)(long)pfl
->storage
;
251 offset
&= pfl
->chip_len
- 1;
253 DPRINTF("%s: offset " TARGET_FMT_lx
" %08x %d\n", __func__
,
254 offset
, value
, width
);
255 boff
= offset
& (pfl
->sector_len
- 1);
258 else if (pfl
->width
== 4)
260 switch (pfl
->wcycle
) {
262 /* Set the device in I/O access mode if required */
264 pflash_register_memory(pfl
, 0);
265 /* We're in read mode */
267 if (boff
== 0x55 && cmd
== 0x98) {
269 /* Enter CFI query mode */
274 if (boff
!= pfl
->unlock_addr
[0] || cmd
!= 0xAA) {
275 DPRINTF("%s: unlock0 failed " TARGET_FMT_lx
" %02x %04x\n",
276 __func__
, boff
, cmd
, pfl
->unlock_addr
[0]);
279 DPRINTF("%s: unlock sequence started\n", __func__
);
282 /* We started an unlock sequence */
284 if (boff
!= pfl
->unlock_addr
[1] || cmd
!= 0x55) {
285 DPRINTF("%s: unlock1 failed " TARGET_FMT_lx
" %02x\n", __func__
,
289 DPRINTF("%s: unlock sequence done\n", __func__
);
292 /* We finished an unlock sequence */
293 if (!pfl
->bypass
&& boff
!= pfl
->unlock_addr
[0]) {
294 DPRINTF("%s: command failed " TARGET_FMT_lx
" %02x\n", __func__
,
306 DPRINTF("%s: starting command %02x\n", __func__
, cmd
);
309 DPRINTF("%s: unknown command %02x\n", __func__
, cmd
);
316 /* We need another unlock sequence */
319 DPRINTF("%s: write data offset " TARGET_FMT_lx
" %08x %d\n",
320 __func__
, offset
, value
, width
);
325 pflash_update(pfl
, offset
, 1);
328 #if defined(TARGET_WORDS_BIGENDIAN)
329 p
[offset
] &= value
>> 8;
330 p
[offset
+ 1] &= value
;
333 p
[offset
+ 1] &= value
>> 8;
335 pflash_update(pfl
, offset
, 2);
338 #if defined(TARGET_WORDS_BIGENDIAN)
339 p
[offset
] &= value
>> 24;
340 p
[offset
+ 1] &= value
>> 16;
341 p
[offset
+ 2] &= value
>> 8;
342 p
[offset
+ 3] &= value
;
345 p
[offset
+ 1] &= value
>> 8;
346 p
[offset
+ 2] &= value
>> 16;
347 p
[offset
+ 3] &= value
>> 24;
349 pflash_update(pfl
, offset
, 4);
352 pfl
->status
= 0x00 | ~(value
& 0x80);
353 /* Let's pretend write is immediate */
358 if (pfl
->bypass
&& cmd
== 0x00) {
359 /* Unlock bypass reset */
362 /* We can enter CFI query mode from autoselect mode */
363 if (boff
== 0x55 && cmd
== 0x98)
367 DPRINTF("%s: invalid write for command %02x\n",
374 /* Ignore writes while flash data write is occuring */
375 /* As we suppose write is immediate, this should never happen */
380 /* Should never happen */
381 DPRINTF("%s: invalid command state %02x (wc 4)\n",
389 if (boff
!= pfl
->unlock_addr
[0]) {
390 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx
"\n",
395 DPRINTF("%s: start chip erase\n", __func__
);
396 memset(pfl
->storage
, 0xFF, pfl
->chip_len
);
398 pflash_update(pfl
, 0, pfl
->chip_len
);
399 /* Let's wait 5 seconds before chip erase is done */
400 qemu_mod_timer(pfl
->timer
,
401 qemu_get_clock(vm_clock
) + (ticks_per_sec
* 5));
406 offset
&= ~(pfl
->sector_len
- 1);
407 DPRINTF("%s: start sector erase at " TARGET_FMT_lx
"\n", __func__
,
409 memset(p
+ offset
, 0xFF, pfl
->sector_len
);
410 pflash_update(pfl
, offset
, pfl
->sector_len
);
412 /* Let's wait 1/2 second before sector erase is done */
413 qemu_mod_timer(pfl
->timer
,
414 qemu_get_clock(vm_clock
) + (ticks_per_sec
/ 2));
417 DPRINTF("%s: invalid command %02x (wc 5)\n", __func__
, cmd
);
425 /* Ignore writes during chip erase */
428 /* Ignore writes during sector erase */
431 /* Should never happen */
432 DPRINTF("%s: invalid command state %02x (wc 6)\n",
437 case 7: /* Special value for CFI queries */
438 DPRINTF("%s: invalid write in CFI query mode\n", __func__
);
441 /* Should never happen */
442 DPRINTF("%s: invalid write state (wc 7)\n", __func__
);
463 static uint32_t pflash_readb (void *opaque
, target_phys_addr_t addr
)
465 return pflash_read(opaque
, addr
, 1);
468 static uint32_t pflash_readw (void *opaque
, target_phys_addr_t addr
)
470 pflash_t
*pfl
= opaque
;
472 return pflash_read(pfl
, addr
, 2);
475 static uint32_t pflash_readl (void *opaque
, target_phys_addr_t addr
)
477 pflash_t
*pfl
= opaque
;
479 return pflash_read(pfl
, addr
, 4);
482 static void pflash_writeb (void *opaque
, target_phys_addr_t addr
,
485 pflash_write(opaque
, addr
, value
, 1);
488 static void pflash_writew (void *opaque
, target_phys_addr_t addr
,
491 pflash_t
*pfl
= opaque
;
493 pflash_write(pfl
, addr
, value
, 2);
496 static void pflash_writel (void *opaque
, target_phys_addr_t addr
,
499 pflash_t
*pfl
= opaque
;
501 pflash_write(pfl
, addr
, value
, 4);
504 static CPUWriteMemoryFunc
*pflash_write_ops
[] = {
510 static CPUReadMemoryFunc
*pflash_read_ops
[] = {
516 /* Count trailing zeroes of a 32 bits quantity */
517 static int ctz32 (uint32_t n
)
542 #if 0 /* This is not necessary as n is never 0 */
550 pflash_t
*pflash_cfi02_register(target_phys_addr_t base
, ram_addr_t off
,
551 BlockDriverState
*bs
, uint32_t sector_len
,
552 int nb_blocs
, int nb_mappings
, int width
,
553 uint16_t id0
, uint16_t id1
,
554 uint16_t id2
, uint16_t id3
,
555 uint16_t unlock_addr0
, uint16_t unlock_addr1
)
560 chip_len
= sector_len
* nb_blocs
;
561 /* XXX: to be fixed */
563 if (total_len
!= (8 * 1024 * 1024) && total_len
!= (16 * 1024 * 1024) &&
564 total_len
!= (32 * 1024 * 1024) && total_len
!= (64 * 1024 * 1024))
567 pfl
= qemu_mallocz(sizeof(pflash_t
));
570 pfl
->storage
= phys_ram_base
+ off
;
571 pfl
->fl_mem
= cpu_register_io_memory(0, pflash_read_ops
, pflash_write_ops
,
575 pfl
->chip_len
= chip_len
;
576 pfl
->mappings
= nb_mappings
;
577 pflash_register_memory(pfl
, 1);
580 /* read the initial flash content */
581 bdrv_read(pfl
->bs
, 0, pfl
->storage
, chip_len
>> 9);
583 #if 0 /* XXX: there should be a bit to set up read-only,
584 * the same way the hardware does (with WP pin).
590 pfl
->timer
= qemu_new_timer(vm_clock
, pflash_timer
, pfl
);
591 pfl
->sector_len
= sector_len
;
600 pfl
->unlock_addr
[0] = unlock_addr0
;
601 pfl
->unlock_addr
[1] = unlock_addr1
;
602 /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
604 /* Standard "QRY" string */
605 pfl
->cfi_table
[0x10] = 'Q';
606 pfl
->cfi_table
[0x11] = 'R';
607 pfl
->cfi_table
[0x12] = 'Y';
608 /* Command set (AMD/Fujitsu) */
609 pfl
->cfi_table
[0x13] = 0x02;
610 pfl
->cfi_table
[0x14] = 0x00;
611 /* Primary extended table address (none) */
612 pfl
->cfi_table
[0x15] = 0x00;
613 pfl
->cfi_table
[0x16] = 0x00;
614 /* Alternate command set (none) */
615 pfl
->cfi_table
[0x17] = 0x00;
616 pfl
->cfi_table
[0x18] = 0x00;
617 /* Alternate extended table (none) */
618 pfl
->cfi_table
[0x19] = 0x00;
619 pfl
->cfi_table
[0x1A] = 0x00;
621 pfl
->cfi_table
[0x1B] = 0x27;
623 pfl
->cfi_table
[0x1C] = 0x36;
624 /* Vpp min (no Vpp pin) */
625 pfl
->cfi_table
[0x1D] = 0x00;
626 /* Vpp max (no Vpp pin) */
627 pfl
->cfi_table
[0x1E] = 0x00;
629 pfl
->cfi_table
[0x1F] = 0x07;
630 /* Timeout for min size buffer write (16 µs) */
631 pfl
->cfi_table
[0x20] = 0x04;
632 /* Typical timeout for block erase (512 ms) */
633 pfl
->cfi_table
[0x21] = 0x09;
634 /* Typical timeout for full chip erase (4096 ms) */
635 pfl
->cfi_table
[0x22] = 0x0C;
637 pfl
->cfi_table
[0x23] = 0x01;
638 /* Max timeout for buffer write */
639 pfl
->cfi_table
[0x24] = 0x04;
640 /* Max timeout for block erase */
641 pfl
->cfi_table
[0x25] = 0x0A;
642 /* Max timeout for chip erase */
643 pfl
->cfi_table
[0x26] = 0x0D;
645 pfl
->cfi_table
[0x27] = ctz32(chip_len
) + 1;
646 /* Flash device interface (8 & 16 bits) */
647 pfl
->cfi_table
[0x28] = 0x02;
648 pfl
->cfi_table
[0x29] = 0x00;
649 /* Max number of bytes in multi-bytes write */
650 /* XXX: disable buffered write as it's not supported */
651 // pfl->cfi_table[0x2A] = 0x05;
652 pfl
->cfi_table
[0x2A] = 0x00;
653 pfl
->cfi_table
[0x2B] = 0x00;
654 /* Number of erase block regions (uniform) */
655 pfl
->cfi_table
[0x2C] = 0x01;
656 /* Erase block region 1 */
657 pfl
->cfi_table
[0x2D] = nb_blocs
- 1;
658 pfl
->cfi_table
[0x2E] = (nb_blocs
- 1) >> 8;
659 pfl
->cfi_table
[0x2F] = sector_len
>> 8;
660 pfl
->cfi_table
[0x30] = sector_len
>> 16;