hw/eccmemctl.c

   1 /*
   2  * QEMU Sparc Sun4m ECC memory controller emulation
   3  *
   4  * Copyright (c) 2007 Robert Reif
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "sysemu.h"
  27
  28 //#define DEBUG_ECC
  29
  30 #ifdef DEBUG_ECC
  31 #define DPRINTF(fmt, args...)                           \
  32     do { printf("ECC: " fmt , ##args); } while (0)
  33 #else
  34 #define DPRINTF(fmt, args...)
  35 #endif
  36
  37 /* There are 3 versions of this chip used in SMP sun4m systems:
  38  * MCC (version 0, implementation 0) SS-600MP
  39  * EMC (version 0, implementation 1) SS-10
  40  * SMC (version 0, implementation 2) SS-10SX and SS-20
  41  */
  42
  43 /* Register offsets */
  44 #define ECC_MER        0                /* Memory Enable Register */
  45 #define ECC_MDR        4                /* Memory Delay Register */
  46 #define ECC_MFSR       8                /* Memory Fault Status Register */
  47 #define ECC_VCR        12               /* Video Configuration Register */
  48 #define ECC_MFAR0      16               /* Memory Fault Address Register 0 */
  49 #define ECC_MFAR1      20               /* Memory Fault Address Register 1 */
  50 #define ECC_DR         24               /* Diagnostic Register */
  51 #define ECC_ECR0       28               /* Event Count Register 0 */
  52 #define ECC_ECR1       32               /* Event Count Register 1 */
  53
  54 /* ECC fault control register */
  55 #define ECC_MER_EE     0x00000001      /* Enable ECC checking */
  56 #define ECC_MER_EI     0x00000002      /* Enable Interrupts on correctable errors */
  57 #define ECC_MER_MRR0   0x00000004      /* SIMM 0 */
  58 #define ECC_MER_MRR1   0x00000008      /* SIMM 1 */
  59 #define ECC_MER_MRR2   0x00000010      /* SIMM 2 */
  60 #define ECC_MER_MRR3   0x00000020      /* SIMM 3 */
  61 #define ECC_MER_MRR4   0x00000040      /* SIMM 4 */
  62 #define ECC_MER_MRR5   0x00000080      /* SIMM 5 */
  63 #define ECC_MER_MRR6   0x00000100      /* SIMM 6 */
  64 #define ECC_MER_MRR7   0x00000200      /* SIMM 7 */
  65 #define ECC_MER_REU    0x00000200      /* Memory Refresh Enable (600MP) */
  66 #define ECC_MER_MRR    0x000003fc      /* MRR mask */
  67 #define ECC_MEM_A      0x00000400      /* Memory controller addr map select */
  68 #define ECC_MER_DCI    0x00000800      /* Dsiables Coherent Invalidate ACK */
  69 #define ECC_MER_VER    0x0f000000      /* Version */
  70 #define ECC_MER_IMPL   0xf0000000      /* Implementation */
  71
  72 /* ECC memory delay register */
  73 #define ECC_MDR_RRI    0x000003ff      /* Refresh Request Interval */
  74 #define ECC_MDR_MI     0x00001c00      /* MIH Delay */
  75 #define ECC_MDR_CI     0x0000e000      /* Coherent Invalidate Delay */
  76 #define ECC_MDR_MDL    0x001f0000      /* MBus Master arbitration delay */
  77 #define ECC_MDR_MDH    0x03e00000      /* MBus Master arbitration delay */
  78 #define ECC_MDR_GAD    0x7c000000      /* Graphics Arbitration Delay */
  79 #define ECC_MDR_RSC    0x80000000      /* Refresh load control */
  80 #define ECC_MDR_MASK   0x7fffffff
  81
  82 /* ECC fault status register */
  83 #define ECC_MFSR_CE    0x00000001      /* Correctable error */
  84 #define ECC_MFSR_BS    0x00000002      /* C2 graphics bad slot access */
  85 #define ECC_MFSR_TO    0x00000004      /* Timeout on write */
  86 #define ECC_MFSR_UE    0x00000008      /* Uncorrectable error */
  87 #define ECC_MFSR_DW    0x000000f0      /* Index of double word in block */
  88 #define ECC_MFSR_SYND  0x0000ff00      /* Syndrome for correctable error */
  89 #define ECC_MFSR_ME    0x00010000      /* Multiple errors */
  90 #define ECC_MFSR_C2ERR 0x00020000      /* C2 graphics error */
  91
  92 /* ECC fault address register 0 */
  93 #define ECC_MFAR0_PADDR 0x0000000f     /* PA[32-35] */
  94 #define ECC_MFAR0_TYPE  0x000000f0     /* Transaction type */
  95 #define ECC_MFAR0_SIZE  0x00000700     /* Transaction size */
  96 #define ECC_MFAR0_CACHE 0x00000800     /* Mapped cacheable */
  97 #define ECC_MFAR0_LOCK  0x00001000     /* Error occurred in atomic cycle */
  98 #define ECC_MFAR0_BMODE 0x00002000     /* Boot mode */
  99 #define ECC_MFAR0_VADDR 0x003fc000     /* VA[12-19] (superset bits) */
 100 #define ECC_MFAR0_S     0x08000000     /* Supervisor mode */
 101 #define ECC_MFARO_MID   0xf0000000     /* Module ID */
 102
 103 /* ECC diagnostic register */
 104 #define ECC_DR_CBX     0x00000001
 105 #define ECC_DR_CB0     0x00000002
 106 #define ECC_DR_CB1     0x00000004
 107 #define ECC_DR_CB2     0x00000008
 108 #define ECC_DR_CB4     0x00000010
 109 #define ECC_DR_CB8     0x00000020
 110 #define ECC_DR_CB16    0x00000040
 111 #define ECC_DR_CB32    0x00000080
 112 #define ECC_DR_DMODE   0x00000c00
 113
 114 #define ECC_NREGS      9
 115 #define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))
 116 #define ECC_ADDR_MASK  0x1f
 117
 118 #define ECC_DIAG_SIZE  4
 119 #define ECC_DIAG_MASK  (ECC_DIAG_SIZE - 1)
 120
 121 typedef struct ECCState {
 122     qemu_irq irq;
 123     uint32_t regs[ECC_NREGS];
 124     uint8_t diag[ECC_DIAG_SIZE];
 125 } ECCState;
 126
 127 static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 128 {
 129     ECCState *s = opaque;
 130
 131     switch (addr & ECC_ADDR_MASK) {
 132     case ECC_MER:
 133         s->regs[0] = (s->regs[0] & (ECC_MER_VER | ECC_MER_IMPL)) |
 134                      (val & ~(ECC_MER_VER | ECC_MER_IMPL));
 135         DPRINTF("Write memory enable %08x\n", val);
 136         break;
 137     case ECC_MDR:
 138         s->regs[1] =  val & ECC_MDR_MASK;
 139         DPRINTF("Write memory delay %08x\n", val);
 140         break;
 141     case ECC_MFSR:
 142         s->regs[2] =  val;
 143         DPRINTF("Write memory fault status %08x\n", val);
 144         break;
 145     case ECC_VCR:
 146         s->regs[3] =  val;
 147         DPRINTF("Write slot configuration %08x\n", val);
 148         break;
 149     case ECC_DR:
 150         s->regs[6] =  val;
 151         DPRINTF("Write diagnosiic %08x\n", val);
 152         break;
 153     case ECC_ECR0:
 154         s->regs[7] =  val;
 155         DPRINTF("Write event count 1 %08x\n", val);
 156         break;
 157     case ECC_ECR1:
 158         s->regs[7] =  val;
 159         DPRINTF("Write event count 2 %08x\n", val);
 160         break;
 161     }
 162 }
 163
 164 static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
 165 {
 166     ECCState *s = opaque;
 167     uint32_t ret = 0;
 168
 169     switch (addr & ECC_ADDR_MASK) {
 170     case ECC_MER:
 171         ret = s->regs[0];
 172         DPRINTF("Read memory enable %08x\n", ret);
 173         break;
 174     case ECC_MDR:
 175         ret = s->regs[1];
 176         DPRINTF("Read memory delay %08x\n", ret);
 177         break;
 178     case ECC_MFSR:
 179         ret = s->regs[2];
 180         DPRINTF("Read memory fault status %08x\n", ret);
 181         break;
 182     case ECC_VCR:
 183         ret = s->regs[3];
 184         DPRINTF("Read slot configuration %08x\n", ret);
 185         break;
 186     case ECC_MFAR0:
 187         ret = s->regs[4];
 188         DPRINTF("Read memory fault address 0 %08x\n", ret);
 189         break;
 190     case ECC_MFAR1:
 191         ret = s->regs[5];
 192         DPRINTF("Read memory fault address 1 %08x\n", ret);
 193         break;
 194     case ECC_DR:
 195         ret = s->regs[6];
 196         DPRINTF("Read diagnostic %08x\n", ret);
 197         break;
 198     case ECC_ECR0:
 199         ret = s->regs[7];
 200         DPRINTF("Read event count 1 %08x\n", ret);
 201         break;
 202     case ECC_ECR1:
 203         ret = s->regs[7];
 204         DPRINTF("Read event count 2 %08x\n", ret);
 205         break;
 206     }
 207     return ret;
 208 }
 209
 210 static CPUReadMemoryFunc *ecc_mem_read[3] = {
 211     NULL,
 212     NULL,
 213     ecc_mem_readl,
 214 };
 215
 216 static CPUWriteMemoryFunc *ecc_mem_write[3] = {
 217     NULL,
 218     NULL,
 219     ecc_mem_writel,
 220 };
 221
 222 static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
 223                                 uint32_t val)
 224 {
 225     ECCState *s = opaque;
 226
 227     DPRINTF("Write diagnostic[%d] = %02x\n", (int)(addr & ECC_DIAG_MASK), val);
 228     s->diag[addr & ECC_DIAG_MASK] = val;
 229 }
 230
 231 static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
 232 {
 233     ECCState *s = opaque;
 234     uint32_t ret = s->diag[addr & ECC_DIAG_MASK];
 235     DPRINTF("Read diagnostic[%d] = %02x\n", (int)(addr & ECC_DIAG_MASK), ret);
 236     return ret;
 237 }
 238
 239 static CPUReadMemoryFunc *ecc_diag_mem_read[3] = {
 240     ecc_diag_mem_readb,
 241     NULL,
 242     NULL,
 243 };
 244
 245 static CPUWriteMemoryFunc *ecc_diag_mem_write[3] = {
 246     ecc_diag_mem_writeb,
 247     NULL,
 248     NULL,
 249 };
 250
 251 static int ecc_load(QEMUFile *f, void *opaque, int version_id)
 252 {
 253     ECCState *s = opaque;
 254     int i;
 255
 256     if (version_id != 2)
 257         return -EINVAL;
 258
 259     for (i = 0; i < ECC_NREGS; i++)
 260         qemu_get_be32s(f, &s->regs[i]);
 261
 262     for (i = 0; i < ECC_DIAG_SIZE; i++)
 263         qemu_get_8s(f, &s->diag[i]);
 264
 265     return 0;
 266 }
 267
 268 static void ecc_save(QEMUFile *f, void *opaque)
 269 {
 270     ECCState *s = opaque;
 271     int i;
 272
 273     for (i = 0; i < ECC_NREGS; i++)
 274         qemu_put_be32s(f, &s->regs[i]);
 275
 276     for (i = 0; i < ECC_DIAG_SIZE; i++)
 277         qemu_put_8s(f, &s->diag[i]);
 278 }
 279
 280 static void ecc_reset(void *opaque)
 281 {
 282     ECCState *s = opaque;
 283     int i;
 284
 285     s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL);
 286     s->regs[ECC_MER] |= ECC_MER_MRR;
 287     s->regs[ECC_MDR] = 0x20;
 288     s->regs[ECC_MFSR] = 0;
 289     s->regs[ECC_VCR] = 0;
 290     s->regs[ECC_MFAR0] = 0x07c00000;
 291     s->regs[ECC_MFAR1] = 0;
 292     s->regs[ECC_DR] = 0;
 293     s->regs[ECC_ECR0] = 0;
 294     s->regs[ECC_ECR1] = 0;
 295
 296     for (i = 1; i < ECC_NREGS; i++)
 297         s->regs[i] = 0;
 298 }
 299
 300 void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
 301 {
 302     int ecc_io_memory;
 303     ECCState *s;
 304
 305     s = qemu_mallocz(sizeof(ECCState));
 306     if (!s)
 307         return NULL;
 308
 309     s->regs[0] = version;
 310     s->irq = irq;
 311
 312     ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
 313     cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);
 314     if (version == 0) { // SS-600MP only
 315         ecc_io_memory = cpu_register_io_memory(0, ecc_diag_mem_read,
 316                                                ecc_diag_mem_write, s);
 317         cpu_register_physical_memory(base + 0x1000, ECC_DIAG_SIZE,
 318                                      ecc_io_memory);
 319     }
 320     register_savevm("ECC", base, 2, ecc_save, ecc_load, s);
 321     qemu_register_reset(ecc_reset, s);
 322     ecc_reset(s);
 323     return s;
 324 }