4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>
24 #include "qemu-timer.h"
25 #include "host-utils.h"
29 //#define DEBUG_COALESCING
32 #define DPRINTF(fmt, ...) \
33 do { printf("apic: " fmt , ## __VA_ARGS__); } while (0)
35 #define DPRINTF(fmt, ...)
38 #ifdef DEBUG_COALESCING
39 #define DPRINTF_C(fmt, ...) \
40 do { printf("apic: " fmt , ## __VA_ARGS__); } while (0)
42 #define DPRINTF_C(fmt, ...)
45 /* APIC Local Vector Table */
46 #define APIC_LVT_TIMER 0
47 #define APIC_LVT_THERMAL 1
48 #define APIC_LVT_PERFORM 2
49 #define APIC_LVT_LINT0 3
50 #define APIC_LVT_LINT1 4
51 #define APIC_LVT_ERROR 5
54 /* APIC delivery modes */
55 #define APIC_DM_FIXED 0
56 #define APIC_DM_LOWPRI 1
59 #define APIC_DM_INIT 5
60 #define APIC_DM_SIPI 6
61 #define APIC_DM_EXTINT 7
63 /* APIC destination mode */
64 #define APIC_DESTMODE_FLAT 0xf
65 #define APIC_DESTMODE_CLUSTER 1
67 #define APIC_TRIGGER_EDGE 0
68 #define APIC_TRIGGER_LEVEL 1
70 #define APIC_LVT_TIMER_PERIODIC (1<<17)
71 #define APIC_LVT_MASKED (1<<16)
72 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
73 #define APIC_LVT_REMOTE_IRR (1<<14)
74 #define APIC_INPUT_POLARITY (1<<13)
75 #define APIC_SEND_PENDING (1<<12)
77 #define ESR_ILLEGAL_ADDRESS (1 << 7)
79 #define APIC_SV_ENABLE (1 << 8)
82 #define MAX_APIC_WORDS 8
84 /* Intel APIC constants: from include/asm/msidef.h */
85 #define MSI_DATA_VECTOR_SHIFT 0
86 #define MSI_DATA_VECTOR_MASK 0x000000ff
87 #define MSI_DATA_DELIVERY_MODE_SHIFT 8
88 #define MSI_DATA_TRIGGER_SHIFT 15
89 #define MSI_DATA_LEVEL_SHIFT 14
90 #define MSI_ADDR_DEST_MODE_SHIFT 2
91 #define MSI_ADDR_DEST_ID_SHIFT 12
92 #define MSI_ADDR_DEST_ID_MASK 0x00ffff0
94 #define MSI_ADDR_BASE 0xfee00000
95 #define MSI_ADDR_SIZE 0x100000
103 uint32_t spurious_vec
;
106 uint32_t isr
[8]; /* in service register */
107 uint32_t tmr
[8]; /* trigger mode register */
108 uint32_t irr
[8]; /* interrupt request register */
109 uint32_t lvt
[APIC_LVT_NB
];
110 uint32_t esr
; /* error register */
113 uint32_t divide_conf
;
115 uint32_t initial_count
;
116 int64_t initial_count_load_time
, next_time
;
123 static int apic_io_memory
;
124 static APICState
*local_apics
[MAX_APICS
+ 1];
125 static int last_apic_idx
= 0;
126 static int apic_irq_delivered
;
129 static void apic_set_irq(APICState
*s
, int vector_num
, int trigger_mode
);
130 static void apic_update_irq(APICState
*s
);
131 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
132 uint8_t dest
, uint8_t dest_mode
);
134 /* Find first bit starting from msb */
135 static int fls_bit(uint32_t value
)
137 return 31 - clz32(value
);
140 /* Find first bit starting from lsb */
141 static int ffs_bit(uint32_t value
)
146 static inline void set_bit(uint32_t *tab
, int index
)
150 mask
= 1 << (index
& 0x1f);
154 static inline void reset_bit(uint32_t *tab
, int index
)
158 mask
= 1 << (index
& 0x1f);
162 static inline int get_bit(uint32_t *tab
, int index
)
166 mask
= 1 << (index
& 0x1f);
167 return !!(tab
[i
] & mask
);
170 static void apic_local_deliver(APICState
*s
, int vector
)
172 uint32_t lvt
= s
->lvt
[vector
];
175 DPRINTF("%s: vector %d delivery mode %d\n", __func__
, vector
,
177 if (lvt
& APIC_LVT_MASKED
)
180 switch ((lvt
>> 8) & 7) {
182 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_SMI
);
186 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_NMI
);
190 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
194 trigger_mode
= APIC_TRIGGER_EDGE
;
195 if ((vector
== APIC_LVT_LINT0
|| vector
== APIC_LVT_LINT1
) &&
196 (lvt
& APIC_LVT_LEVEL_TRIGGER
))
197 trigger_mode
= APIC_TRIGGER_LEVEL
;
198 apic_set_irq(s
, lvt
& 0xff, trigger_mode
);
202 void apic_deliver_pic_intr(APICState
*s
, int level
)
205 apic_local_deliver(s
, APIC_LVT_LINT0
);
207 uint32_t lvt
= s
->lvt
[APIC_LVT_LINT0
];
209 switch ((lvt
>> 8) & 7) {
211 if (!(lvt
& APIC_LVT_LEVEL_TRIGGER
))
213 reset_bit(s
->irr
, lvt
& 0xff);
216 cpu_reset_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
222 #define foreach_apic(apic, deliver_bitmask, code) \
224 int __i, __j, __mask;\
225 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
226 __mask = deliver_bitmask[__i];\
228 for(__j = 0; __j < 32; __j++) {\
229 if (__mask & (1 << __j)) {\
230 apic = local_apics[__i * 32 + __j];\
240 static void apic_bus_deliver(const uint32_t *deliver_bitmask
,
241 uint8_t delivery_mode
,
242 uint8_t vector_num
, uint8_t polarity
,
243 uint8_t trigger_mode
)
245 APICState
*apic_iter
;
247 switch (delivery_mode
) {
249 /* XXX: search for focus processor, arbitration */
253 for(i
= 0; i
< MAX_APIC_WORDS
; i
++) {
254 if (deliver_bitmask
[i
]) {
255 d
= i
* 32 + ffs_bit(deliver_bitmask
[i
]);
260 apic_iter
= local_apics
[d
];
262 apic_set_irq(apic_iter
, vector_num
, trigger_mode
);
272 foreach_apic(apic_iter
, deliver_bitmask
,
273 cpu_interrupt(apic_iter
->cpu_env
, CPU_INTERRUPT_SMI
) );
277 foreach_apic(apic_iter
, deliver_bitmask
,
278 cpu_interrupt(apic_iter
->cpu_env
, CPU_INTERRUPT_NMI
) );
282 /* normal INIT IPI sent to processors */
283 foreach_apic(apic_iter
, deliver_bitmask
,
284 cpu_interrupt(apic_iter
->cpu_env
, CPU_INTERRUPT_INIT
) );
288 /* handled in I/O APIC code */
295 foreach_apic(apic_iter
, deliver_bitmask
,
296 apic_set_irq(apic_iter
, vector_num
, trigger_mode
) );
299 void apic_deliver_irq(uint8_t dest
, uint8_t dest_mode
,
300 uint8_t delivery_mode
, uint8_t vector_num
,
301 uint8_t polarity
, uint8_t trigger_mode
)
303 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
305 DPRINTF("%s: dest %d dest_mode %d delivery_mode %d vector %d"
306 " polarity %d trigger_mode %d\n", __func__
, dest
, dest_mode
,
307 delivery_mode
, vector_num
, polarity
, trigger_mode
);
308 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
309 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, polarity
,
313 void cpu_set_apic_base(APICState
*s
, uint64_t val
)
315 DPRINTF("cpu_set_apic_base: %016" PRIx64
"\n", val
);
318 if (kvm_enabled() && kvm_irqchip_in_kernel())
321 s
->apicbase
= (val
& 0xfffff000) |
322 (s
->apicbase
& (MSR_IA32_APICBASE_BSP
| MSR_IA32_APICBASE_ENABLE
));
323 /* if disabled, cannot be enabled again */
324 if (!(val
& MSR_IA32_APICBASE_ENABLE
)) {
325 s
->apicbase
&= ~MSR_IA32_APICBASE_ENABLE
;
326 cpu_clear_apic_feature(s
->cpu_env
);
327 s
->spurious_vec
&= ~APIC_SV_ENABLE
;
331 uint64_t cpu_get_apic_base(APICState
*s
)
333 DPRINTF("cpu_get_apic_base: %016" PRIx64
"\n",
334 s
? (uint64_t)s
->apicbase
: 0);
335 return s
? s
->apicbase
: 0;
338 void cpu_set_apic_tpr(APICState
*s
, uint8_t val
)
342 s
->tpr
= (val
& 0x0f) << 4;
346 uint8_t cpu_get_apic_tpr(APICState
*s
)
348 return s
? s
->tpr
>> 4 : 0;
351 /* return -1 if no bit is set */
352 static int get_highest_priority_int(uint32_t *tab
)
355 for(i
= 7; i
>= 0; i
--) {
357 return i
* 32 + fls_bit(tab
[i
]);
363 static int apic_get_ppr(APICState
*s
)
368 isrv
= get_highest_priority_int(s
->isr
);
379 static int apic_get_arb_pri(APICState
*s
)
381 /* XXX: arbitration */
385 /* signal the CPU if an irq is pending */
386 static void apic_update_irq(APICState
*s
)
389 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
391 irrv
= get_highest_priority_int(s
->irr
);
394 ppr
= apic_get_ppr(s
);
395 if (ppr
&& (irrv
& 0xf0) <= (ppr
& 0xf0))
397 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_HARD
);
400 void apic_reset_irq_delivered(void)
402 DPRINTF_C("%s: old coalescing %d\n", __func__
, apic_irq_delivered
);
403 apic_irq_delivered
= 0;
406 int apic_get_irq_delivered(void)
408 DPRINTF_C("%s: returning coalescing %d\n", __func__
, apic_irq_delivered
);
409 return apic_irq_delivered
;
412 void apic_set_irq_delivered(void)
414 apic_irq_delivered
= 1;
417 static void apic_set_irq(APICState
*s
, int vector_num
, int trigger_mode
)
419 apic_irq_delivered
+= !get_bit(s
->irr
, vector_num
);
420 DPRINTF_C("%s: coalescing %d\n", __func__
, apic_irq_delivered
);
422 set_bit(s
->irr
, vector_num
);
424 set_bit(s
->tmr
, vector_num
);
426 reset_bit(s
->tmr
, vector_num
);
430 static void apic_eoi(APICState
*s
)
433 isrv
= get_highest_priority_int(s
->isr
);
436 reset_bit(s
->isr
, isrv
);
437 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
438 set the remote IRR bit for level triggered interrupts. */
442 static int apic_find_dest(uint8_t dest
)
444 APICState
*apic
= local_apics
[dest
];
447 if (apic
&& apic
->id
== dest
)
448 return dest
; /* shortcut in case apic->id == apic->idx */
450 for (i
= 0; i
< MAX_APICS
; i
++) {
451 apic
= local_apics
[i
];
452 if (apic
&& apic
->id
== dest
)
459 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
460 uint8_t dest
, uint8_t dest_mode
)
462 APICState
*apic_iter
;
465 if (dest_mode
== 0) {
467 memset(deliver_bitmask
, 0xff, MAX_APIC_WORDS
* sizeof(uint32_t));
469 int idx
= apic_find_dest(dest
);
470 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
472 set_bit(deliver_bitmask
, idx
);
475 /* XXX: cluster mode */
476 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
477 for(i
= 0; i
< MAX_APICS
; i
++) {
478 apic_iter
= local_apics
[i
];
480 if (apic_iter
->dest_mode
== 0xf) {
481 if (dest
& apic_iter
->log_dest
)
482 set_bit(deliver_bitmask
, i
);
483 } else if (apic_iter
->dest_mode
== 0x0) {
484 if ((dest
& 0xf0) == (apic_iter
->log_dest
& 0xf0) &&
485 (dest
& apic_iter
->log_dest
& 0x0f)) {
486 set_bit(deliver_bitmask
, i
);
495 void apic_init_reset(APICState
*s
)
503 s
->spurious_vec
= 0xff;
506 memset(s
->isr
, 0, sizeof(s
->isr
));
507 memset(s
->tmr
, 0, sizeof(s
->tmr
));
508 memset(s
->irr
, 0, sizeof(s
->irr
));
509 for(i
= 0; i
< APIC_LVT_NB
; i
++)
510 s
->lvt
[i
] = 1 << 16; /* mask LVT */
512 memset(s
->icr
, 0, sizeof(s
->icr
));
515 s
->initial_count
= 0;
516 s
->initial_count_load_time
= 0;
518 s
->wait_for_sipi
= 1;
521 static void apic_startup(APICState
*s
, int vector_num
)
523 s
->sipi_vector
= vector_num
;
524 cpu_interrupt(s
->cpu_env
, CPU_INTERRUPT_SIPI
);
527 void apic_sipi(APICState
*s
)
529 cpu_reset_interrupt(s
->cpu_env
, CPU_INTERRUPT_SIPI
);
531 if (!s
->wait_for_sipi
)
533 cpu_x86_load_seg_cache_sipi(s
->cpu_env
, s
->sipi_vector
);
534 s
->wait_for_sipi
= 0;
537 static void apic_deliver(APICState
*s
, uint8_t dest
, uint8_t dest_mode
,
538 uint8_t delivery_mode
, uint8_t vector_num
,
539 uint8_t polarity
, uint8_t trigger_mode
)
541 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
542 int dest_shorthand
= (s
->icr
[0] >> 18) & 3;
543 APICState
*apic_iter
;
545 switch (dest_shorthand
) {
547 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
550 memset(deliver_bitmask
, 0x00, sizeof(deliver_bitmask
));
551 set_bit(deliver_bitmask
, s
->idx
);
554 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
557 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
558 reset_bit(deliver_bitmask
, s
->idx
);
562 switch (delivery_mode
) {
565 int trig_mode
= (s
->icr
[0] >> 15) & 1;
566 int level
= (s
->icr
[0] >> 14) & 1;
567 if (level
== 0 && trig_mode
== 1) {
568 foreach_apic(apic_iter
, deliver_bitmask
,
569 apic_iter
->arb_id
= apic_iter
->id
);
576 foreach_apic(apic_iter
, deliver_bitmask
,
577 apic_startup(apic_iter
, vector_num
) );
581 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, polarity
,
585 int apic_get_interrupt(APICState
*s
)
589 /* if the APIC is installed or enabled, we let the 8259 handle the
593 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
596 /* XXX: spurious IRQ handling */
597 intno
= get_highest_priority_int(s
->irr
);
600 if (s
->tpr
&& intno
<= s
->tpr
)
601 return s
->spurious_vec
& 0xff;
602 reset_bit(s
->irr
, intno
);
603 set_bit(s
->isr
, intno
);
608 int apic_accept_pic_intr(APICState
*s
)
615 lvt0
= s
->lvt
[APIC_LVT_LINT0
];
617 if ((s
->apicbase
& MSR_IA32_APICBASE_ENABLE
) == 0 ||
618 (lvt0
& APIC_LVT_MASKED
) == 0)
624 static uint32_t apic_get_current_count(APICState
*s
)
628 d
= (qemu_get_clock(vm_clock
) - s
->initial_count_load_time
) >>
630 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
632 val
= s
->initial_count
- (d
% ((uint64_t)s
->initial_count
+ 1));
634 if (d
>= s
->initial_count
)
637 val
= s
->initial_count
- d
;
642 static void apic_timer_update(APICState
*s
, int64_t current_time
)
644 int64_t next_time
, d
;
646 if (!(s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_MASKED
)) {
647 d
= (current_time
- s
->initial_count_load_time
) >>
649 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
650 if (!s
->initial_count
)
652 d
= ((d
/ ((uint64_t)s
->initial_count
+ 1)) + 1) * ((uint64_t)s
->initial_count
+ 1);
654 if (d
>= s
->initial_count
)
656 d
= (uint64_t)s
->initial_count
+ 1;
658 next_time
= s
->initial_count_load_time
+ (d
<< s
->count_shift
);
659 qemu_mod_timer(s
->timer
, next_time
);
660 s
->next_time
= next_time
;
663 qemu_del_timer(s
->timer
);
667 static void apic_timer(void *opaque
)
669 APICState
*s
= opaque
;
671 apic_local_deliver(s
, APIC_LVT_TIMER
);
672 apic_timer_update(s
, s
->next_time
);
675 static uint32_t apic_mem_readb(void *opaque
, target_phys_addr_t addr
)
680 static uint32_t apic_mem_readw(void *opaque
, target_phys_addr_t addr
)
685 static void apic_mem_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
689 static void apic_mem_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
693 static uint32_t apic_mem_readl(void *opaque
, target_phys_addr_t addr
)
699 s
= cpu_get_current_apic();
704 index
= (addr
>> 4) & 0xff;
709 case 0x03: /* version */
710 val
= 0x11 | ((APIC_LVT_NB
- 1) << 16); /* version 0x11 */
716 val
= apic_get_arb_pri(s
);
720 val
= apic_get_ppr(s
);
726 val
= s
->log_dest
<< 24;
729 val
= s
->dest_mode
<< 28;
732 val
= s
->spurious_vec
;
735 val
= s
->isr
[index
& 7];
738 val
= s
->tmr
[index
& 7];
741 val
= s
->irr
[index
& 7];
748 val
= s
->icr
[index
& 1];
751 val
= s
->lvt
[index
- 0x32];
754 val
= s
->initial_count
;
757 val
= apic_get_current_count(s
);
760 val
= s
->divide_conf
;
763 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
767 DPRINTF("read: " TARGET_FMT_plx
" = %08x\n", addr
, val
);
771 static void apic_send_msi(target_phys_addr_t addr
, uint32 data
)
773 uint8_t dest
= (addr
& MSI_ADDR_DEST_ID_MASK
) >> MSI_ADDR_DEST_ID_SHIFT
;
774 uint8_t vector
= (data
& MSI_DATA_VECTOR_MASK
) >> MSI_DATA_VECTOR_SHIFT
;
775 uint8_t dest_mode
= (addr
>> MSI_ADDR_DEST_MODE_SHIFT
) & 0x1;
776 uint8_t trigger_mode
= (data
>> MSI_DATA_TRIGGER_SHIFT
) & 0x1;
777 uint8_t delivery
= (data
>> MSI_DATA_DELIVERY_MODE_SHIFT
) & 0x7;
778 /* XXX: Ignore redirection hint. */
779 apic_deliver_irq(dest
, dest_mode
, delivery
, vector
, 0, trigger_mode
);
782 static void apic_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
785 int index
= (addr
>> 4) & 0xff;
786 if (addr
> 0xfff || !index
) {
787 /* MSI and MMIO APIC are at the same memory location,
788 * but actually not on the global bus: MSI is on PCI bus
789 * APIC is connected directly to the CPU.
790 * Mapping them on the global bus happens to work because
791 * MSI registers are reserved in APIC MMIO and vice versa. */
792 apic_send_msi(addr
, val
);
796 s
= cpu_get_current_apic();
801 DPRINTF("write: " TARGET_FMT_plx
" = %08x\n", addr
, val
);
820 s
->log_dest
= val
>> 24;
823 s
->dest_mode
= val
>> 28;
826 s
->spurious_vec
= val
& 0x1ff;
836 apic_deliver(s
, (s
->icr
[1] >> 24) & 0xff, (s
->icr
[0] >> 11) & 1,
837 (s
->icr
[0] >> 8) & 7, (s
->icr
[0] & 0xff),
838 (s
->icr
[0] >> 14) & 1, (s
->icr
[0] >> 15) & 1);
845 int n
= index
- 0x32;
847 if (n
== APIC_LVT_TIMER
)
848 apic_timer_update(s
, qemu_get_clock(vm_clock
));
852 s
->initial_count
= val
;
853 s
->initial_count_load_time
= qemu_get_clock(vm_clock
);
854 apic_timer_update(s
, s
->initial_count_load_time
);
861 s
->divide_conf
= val
& 0xb;
862 v
= (s
->divide_conf
& 3) | ((s
->divide_conf
>> 1) & 4);
863 s
->count_shift
= (v
+ 1) & 7;
867 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
872 #ifdef KVM_CAP_IRQCHIP
874 static inline uint32_t kapic_reg(struct kvm_lapic_state
*kapic
, int reg_id
)
876 return *((uint32_t *) (kapic
->regs
+ (reg_id
<< 4)));
879 static inline void kapic_set_reg(struct kvm_lapic_state
*kapic
,
880 int reg_id
, uint32_t val
)
882 *((uint32_t *) (kapic
->regs
+ (reg_id
<< 4))) = val
;
885 static void kvm_kernel_lapic_save_to_user(APICState
*s
)
887 struct kvm_lapic_state apic
;
888 struct kvm_lapic_state
*kapic
= &apic
;
891 kvm_get_lapic(s
->cpu_env
, kapic
);
893 s
->id
= kapic_reg(kapic
, 0x2) >> 24;
894 s
->tpr
= kapic_reg(kapic
, 0x8);
895 s
->arb_id
= kapic_reg(kapic
, 0x9);
896 s
->log_dest
= kapic_reg(kapic
, 0xd) >> 24;
897 s
->dest_mode
= kapic_reg(kapic
, 0xe) >> 28;
898 s
->spurious_vec
= kapic_reg(kapic
, 0xf);
899 for (i
= 0; i
< 8; i
++) {
900 s
->isr
[i
] = kapic_reg(kapic
, 0x10 + i
);
901 s
->tmr
[i
] = kapic_reg(kapic
, 0x18 + i
);
902 s
->irr
[i
] = kapic_reg(kapic
, 0x20 + i
);
904 s
->esr
= kapic_reg(kapic
, 0x28);
905 s
->icr
[0] = kapic_reg(kapic
, 0x30);
906 s
->icr
[1] = kapic_reg(kapic
, 0x31);
907 for (i
= 0; i
< APIC_LVT_NB
; i
++)
908 s
->lvt
[i
] = kapic_reg(kapic
, 0x32 + i
);
909 s
->initial_count
= kapic_reg(kapic
, 0x38);
910 s
->divide_conf
= kapic_reg(kapic
, 0x3e);
912 v
= (s
->divide_conf
& 3) | ((s
->divide_conf
>> 1) & 4);
913 s
->count_shift
= (v
+ 1) & 7;
915 s
->initial_count_load_time
= qemu_get_clock(vm_clock
);
916 apic_timer_update(s
, s
->initial_count_load_time
);
919 static void kvm_kernel_lapic_load_from_user(APICState
*s
)
921 struct kvm_lapic_state apic
;
922 struct kvm_lapic_state
*klapic
= &apic
;
925 memset(klapic
, 0, sizeof apic
);
926 kapic_set_reg(klapic
, 0x2, s
->id
<< 24);
927 kapic_set_reg(klapic
, 0x8, s
->tpr
);
928 kapic_set_reg(klapic
, 0xd, s
->log_dest
<< 24);
929 kapic_set_reg(klapic
, 0xe, s
->dest_mode
<< 28 | 0x0fffffff);
930 kapic_set_reg(klapic
, 0xf, s
->spurious_vec
);
931 for (i
= 0; i
< 8; i
++) {
932 kapic_set_reg(klapic
, 0x10 + i
, s
->isr
[i
]);
933 kapic_set_reg(klapic
, 0x18 + i
, s
->tmr
[i
]);
934 kapic_set_reg(klapic
, 0x20 + i
, s
->irr
[i
]);
936 kapic_set_reg(klapic
, 0x28, s
->esr
);
937 kapic_set_reg(klapic
, 0x30, s
->icr
[0]);
938 kapic_set_reg(klapic
, 0x31, s
->icr
[1]);
939 for (i
= 0; i
< APIC_LVT_NB
; i
++)
940 kapic_set_reg(klapic
, 0x32 + i
, s
->lvt
[i
]);
941 kapic_set_reg(klapic
, 0x38, s
->initial_count
);
942 kapic_set_reg(klapic
, 0x3e, s
->divide_conf
);
944 kvm_set_lapic(s
->cpu_env
, klapic
);
949 void kvm_load_lapic(CPUState
*env
)
951 #ifdef KVM_CAP_IRQCHIP
952 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
953 kvm_kernel_lapic_load_from_user(env
->apic_state
);
958 void kvm_save_lapic(CPUState
*env
)
960 #ifdef KVM_CAP_IRQCHIP
961 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
962 kvm_kernel_lapic_save_to_user(env
->apic_state
);
967 /* This function is only used for old state version 1 and 2 */
968 static int apic_load_old(QEMUFile
*f
, void *opaque
, int version_id
)
970 APICState
*s
= opaque
;
976 /* XXX: what if the base changes? (registered memory regions) */
977 qemu_get_be32s(f
, &s
->apicbase
);
978 qemu_get_8s(f
, &s
->id
);
979 qemu_get_8s(f
, &s
->arb_id
);
980 qemu_get_8s(f
, &s
->tpr
);
981 qemu_get_be32s(f
, &s
->spurious_vec
);
982 qemu_get_8s(f
, &s
->log_dest
);
983 qemu_get_8s(f
, &s
->dest_mode
);
984 for (i
= 0; i
< 8; i
++) {
985 qemu_get_be32s(f
, &s
->isr
[i
]);
986 qemu_get_be32s(f
, &s
->tmr
[i
]);
987 qemu_get_be32s(f
, &s
->irr
[i
]);
989 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
990 qemu_get_be32s(f
, &s
->lvt
[i
]);
992 qemu_get_be32s(f
, &s
->esr
);
993 qemu_get_be32s(f
, &s
->icr
[0]);
994 qemu_get_be32s(f
, &s
->icr
[1]);
995 qemu_get_be32s(f
, &s
->divide_conf
);
996 s
->count_shift
=qemu_get_be32(f
);
997 qemu_get_be32s(f
, &s
->initial_count
);
998 s
->initial_count_load_time
=qemu_get_be64(f
);
999 s
->next_time
=qemu_get_be64(f
);
1001 if (version_id
>= 2)
1002 qemu_get_timer(f
, s
->timer
);
1006 static const VMStateDescription vmstate_apic
= {
1009 .minimum_version_id
= 3,
1010 .minimum_version_id_old
= 1,
1011 .load_state_old
= apic_load_old
,
1012 .fields
= (VMStateField
[]) {
1013 VMSTATE_UINT32(apicbase
, APICState
),
1014 VMSTATE_UINT8(id
, APICState
),
1015 VMSTATE_UINT8(arb_id
, APICState
),
1016 VMSTATE_UINT8(tpr
, APICState
),
1017 VMSTATE_UINT32(spurious_vec
, APICState
),
1018 VMSTATE_UINT8(log_dest
, APICState
),
1019 VMSTATE_UINT8(dest_mode
, APICState
),
1020 VMSTATE_UINT32_ARRAY(isr
, APICState
, 8),
1021 VMSTATE_UINT32_ARRAY(tmr
, APICState
, 8),
1022 VMSTATE_UINT32_ARRAY(irr
, APICState
, 8),
1023 VMSTATE_UINT32_ARRAY(lvt
, APICState
, APIC_LVT_NB
),
1024 VMSTATE_UINT32(esr
, APICState
),
1025 VMSTATE_UINT32_ARRAY(icr
, APICState
, 2),
1026 VMSTATE_UINT32(divide_conf
, APICState
),
1027 VMSTATE_INT32(count_shift
, APICState
),
1028 VMSTATE_UINT32(initial_count
, APICState
),
1029 VMSTATE_INT64(initial_count_load_time
, APICState
),
1030 VMSTATE_INT64(next_time
, APICState
),
1031 VMSTATE_TIMER(timer
, APICState
),
1032 VMSTATE_END_OF_LIST()
1036 static void apic_reset(void *opaque
)
1038 APICState
*s
= opaque
;
1041 bsp
= cpu_is_bsp(s
->cpu_env
);
1042 s
->apicbase
= 0xfee00000 |
1043 (bsp
? MSR_IA32_APICBASE_BSP
: 0) | MSR_IA32_APICBASE_ENABLE
;
1049 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1050 * time typically by BIOS, so PIC interrupt can be delivered to the
1051 * processor when local APIC is enabled.
1053 s
->lvt
[APIC_LVT_LINT0
] = 0x700;
1057 static CPUReadMemoryFunc
* const apic_mem_read
[3] = {
1063 static CPUWriteMemoryFunc
* const apic_mem_write
[3] = {
1069 APICState
*apic_init(CPUState
*env
, uint32_t apic_id
)
1073 if (last_apic_idx
>= MAX_APICS
) {
1076 s
= qemu_mallocz(sizeof(APICState
));
1077 s
->idx
= last_apic_idx
++;
1083 /* XXX: mapping more APICs at the same memory location */
1084 if (apic_io_memory
== 0) {
1085 /* NOTE: the APIC is directly connected to the CPU - it is not
1086 on the global memory bus. */
1087 apic_io_memory
= cpu_register_io_memory(apic_mem_read
,
1088 apic_mem_write
, NULL
);
1089 /* XXX: what if the base changes? */
1090 cpu_register_physical_memory(MSI_ADDR_BASE
, MSI_ADDR_SIZE
,
1093 s
->timer
= qemu_new_timer(vm_clock
, apic_timer
, s
);
1095 vmstate_register(s
->idx
, &vmstate_apic
, s
);
1096 qemu_register_reset(apic_reset
, s
);
1098 local_apics
[s
->idx
] = s
;