hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "apic.h"
  21 #include "msix.h"
  22 #include "qemu-timer.h"
  23 #include "host-utils.h"
  24 #include "sysbus.h"
  25 #include "kvm.h"
  26
  27 //#define DEBUG_APIC
  28 //#define DEBUG_COALESCING
  29
  30 #ifdef DEBUG_APIC
  31 #define DPRINTF(fmt, ...)                                       \
  32     do { printf("apic: " fmt , ## __VA_ARGS__); } while (0)
  33 #else
  34 #define DPRINTF(fmt, ...)
  35 #endif
  36
  37 #ifdef DEBUG_COALESCING
  38 #define DPRINTF_C(fmt, ...)                                     \
  39     do { printf("apic: " fmt , ## __VA_ARGS__); } while (0)
  40 #else
  41 #define DPRINTF_C(fmt, ...)
  42 #endif
  43
  44 /* APIC Local Vector Table */
  45 #define APIC_LVT_TIMER   0
  46 #define APIC_LVT_THERMAL 1
  47 #define APIC_LVT_PERFORM 2
  48 #define APIC_LVT_LINT0   3
  49 #define APIC_LVT_LINT1   4
  50 #define APIC_LVT_ERROR   5
  51 #define APIC_LVT_NB      6
  52
  53 /* APIC delivery modes */
  54 #define APIC_DM_FIXED   0
  55 #define APIC_DM_LOWPRI  1
  56 #define APIC_DM_SMI     2
  57 #define APIC_DM_NMI     4
  58 #define APIC_DM_INIT    5
  59 #define APIC_DM_SIPI    6
  60 #define APIC_DM_EXTINT  7
  61
  62 /* APIC destination mode */
  63 #define APIC_DESTMODE_FLAT      0xf
  64 #define APIC_DESTMODE_CLUSTER   1
  65
  66 #define APIC_TRIGGER_EDGE  0
  67 #define APIC_TRIGGER_LEVEL 1
  68
  69 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  70 #define APIC_LVT_MASKED                 (1<<16)
  71 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  72 #define APIC_LVT_REMOTE_IRR             (1<<14)
  73 #define APIC_INPUT_POLARITY             (1<<13)
  74 #define APIC_SEND_PENDING               (1<<12)
  75
  76 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  77
  78 #define APIC_SV_ENABLE (1 << 8)
  79
  80 #define MAX_APICS 255
  81 #define MAX_APIC_WORDS 8
  82
  83 /* Intel APIC constants: from include/asm/msidef.h */
  84 #define MSI_DATA_VECTOR_SHIFT           0
  85 #define MSI_DATA_VECTOR_MASK            0x000000ff
  86 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  87 #define MSI_DATA_TRIGGER_SHIFT          15
  88 #define MSI_DATA_LEVEL_SHIFT            14
  89 #define MSI_ADDR_DEST_MODE_SHIFT        2
  90 #define MSI_ADDR_DEST_ID_SHIFT          12
  91 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  92
  93 #define MSI_ADDR_BASE                   0xfee00000
  94 #define MSI_ADDR_SIZE                   0x100000
  95
  96 struct APICState {
  97     SysBusDevice busdev;
  98     void *cpu_env;
  99     uint32_t apicbase;
 100     uint8_t id;
 101     uint8_t arb_id;
 102     uint8_t tpr;
 103     uint32_t spurious_vec;
 104     uint8_t log_dest;
 105     uint8_t dest_mode;
 106     uint32_t isr[8];  /* in service register */
 107     uint32_t tmr[8];  /* trigger mode register */
 108     uint32_t irr[8]; /* interrupt request register */
 109     uint32_t lvt[APIC_LVT_NB];
 110     uint32_t esr; /* error register */
 111     uint32_t icr[2];
 112
 113     uint32_t divide_conf;
 114     int count_shift;
 115     uint32_t initial_count;
 116     int64_t initial_count_load_time, next_time;
 117     uint32_t idx;
 118     QEMUTimer *timer;
 119     int sipi_vector;
 120     int wait_for_sipi;
 121 };
 122
 123 static APICState *local_apics[MAX_APICS + 1];
 124 static int apic_irq_delivered;
 125
 126 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 127 static void apic_update_irq(APICState *s);
 128 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 129                                       uint8_t dest, uint8_t dest_mode);
 130
 131 /* Find first bit starting from msb */
 132 static int fls_bit(uint32_t value)
 133 {
 134     return 31 - clz32(value);
 135 }
 136
 137 /* Find first bit starting from lsb */
 138 static int ffs_bit(uint32_t value)
 139 {
 140     return ctz32(value);
 141 }
 142
 143 static inline void set_bit(uint32_t *tab, int index)
 144 {
 145     int i, mask;
 146     i = index >> 5;
 147     mask = 1 << (index & 0x1f);
 148     tab[i] |= mask;
 149 }
 150
 151 static inline void reset_bit(uint32_t *tab, int index)
 152 {
 153     int i, mask;
 154     i = index >> 5;
 155     mask = 1 << (index & 0x1f);
 156     tab[i] &= ~mask;
 157 }
 158
 159 static inline int get_bit(uint32_t *tab, int index)
 160 {
 161     int i, mask;
 162     i = index >> 5;
 163     mask = 1 << (index & 0x1f);
 164     return !!(tab[i] & mask);
 165 }
 166
 167 static void apic_local_deliver(APICState *s, int vector)
 168 {
 169     uint32_t lvt = s->lvt[vector];
 170     int trigger_mode;
 171
 172     DPRINTF("%s: vector %d delivery mode %d\n", __func__, vector,
 173             (lvt >> 8) & 7);
 174     if (lvt & APIC_LVT_MASKED)
 175         return;
 176
 177     switch ((lvt >> 8) & 7) {
 178     case APIC_DM_SMI:
 179         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
 180         break;
 181
 182     case APIC_DM_NMI:
 183         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
 184         break;
 185
 186     case APIC_DM_EXTINT:
 187         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 188         break;
 189
 190     case APIC_DM_FIXED:
 191         trigger_mode = APIC_TRIGGER_EDGE;
 192         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 193             (lvt & APIC_LVT_LEVEL_TRIGGER))
 194             trigger_mode = APIC_TRIGGER_LEVEL;
 195         apic_set_irq(s, lvt & 0xff, trigger_mode);
 196     }
 197 }
 198
 199 void apic_deliver_pic_intr(APICState *s, int level)
 200 {
 201     if (level) {
 202         apic_local_deliver(s, APIC_LVT_LINT0);
 203     } else {
 204         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 205
 206         switch ((lvt >> 8) & 7) {
 207         case APIC_DM_FIXED:
 208             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 209                 break;
 210             reset_bit(s->irr, lvt & 0xff);
 211             /* fall through */
 212         case APIC_DM_EXTINT:
 213             cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 214             break;
 215         }
 216     }
 217 }
 218
 219 #define foreach_apic(apic, deliver_bitmask, code) \
 220 {\
 221     int __i, __j, __mask;\
 222     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 223         __mask = deliver_bitmask[__i];\
 224         if (__mask) {\
 225             for(__j = 0; __j < 32; __j++) {\
 226                 if (__mask & (1 << __j)) {\
 227                     apic = local_apics[__i * 32 + __j];\
 228                     if (apic) {\
 229                         code;\
 230                     }\
 231                 }\
 232             }\
 233         }\
 234     }\
 235 }
 236
 237 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 238                              uint8_t delivery_mode,
 239                              uint8_t vector_num, uint8_t polarity,
 240                              uint8_t trigger_mode)
 241 {
 242     APICState *apic_iter;
 243
 244     switch (delivery_mode) {
 245         case APIC_DM_LOWPRI:
 246             /* XXX: search for focus processor, arbitration */
 247             {
 248                 int i, d;
 249                 d = -1;
 250                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 251                     if (deliver_bitmask[i]) {
 252                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 253                         break;
 254                     }
 255                 }
 256                 if (d >= 0) {
 257                     apic_iter = local_apics[d];
 258                     if (apic_iter) {
 259                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 260                     }
 261                 }
 262             }
 263             return;
 264
 265         case APIC_DM_FIXED:
 266             break;
 267
 268         case APIC_DM_SMI:
 269             foreach_apic(apic_iter, deliver_bitmask,
 270                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 271             return;
 272
 273         case APIC_DM_NMI:
 274             foreach_apic(apic_iter, deliver_bitmask,
 275                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 276             return;
 277
 278         case APIC_DM_INIT:
 279             /* normal INIT IPI sent to processors */
 280             foreach_apic(apic_iter, deliver_bitmask,
 281                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 282             return;
 283
 284         case APIC_DM_EXTINT:
 285             /* handled in I/O APIC code */
 286             break;
 287
 288         default:
 289             return;
 290     }
 291
 292     foreach_apic(apic_iter, deliver_bitmask,
 293                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 294 }
 295
 296 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 297                       uint8_t delivery_mode, uint8_t vector_num,
 298                       uint8_t polarity, uint8_t trigger_mode)
 299 {
 300     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 301
 302     DPRINTF("%s: dest %d dest_mode %d delivery_mode %d vector %d"
 303             " polarity %d trigger_mode %d\n", __func__, dest, dest_mode,
 304             delivery_mode, vector_num, polarity, trigger_mode);
 305     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 306     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 307                      trigger_mode);
 308 }
 309
 310 void cpu_set_apic_base(APICState *s, uint64_t val)
 311 {
 312     DPRINTF("cpu_set_apic_base: %016" PRIx64 "\n", val);
 313     if (!s)
 314         return;
 315     if (kvm_enabled() && kvm_irqchip_in_kernel())
 316         s->apicbase = val;
 317     else
 318         s->apicbase = (val & 0xfffff000) |
 319             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 320     /* if disabled, cannot be enabled again */
 321     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 322         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 323         cpu_clear_apic_feature(s->cpu_env);
 324         s->spurious_vec &= ~APIC_SV_ENABLE;
 325     }
 326 }
 327
 328 uint64_t cpu_get_apic_base(APICState *s)
 329 {
 330     DPRINTF("cpu_get_apic_base: %016" PRIx64 "\n",
 331             s ? (uint64_t)s->apicbase: 0);
 332     return s ? s->apicbase : 0;
 333 }
 334
 335 void cpu_set_apic_tpr(APICState *s, uint8_t val)
 336 {
 337     if (!s)
 338         return;
 339     s->tpr = (val & 0x0f) << 4;
 340     apic_update_irq(s);
 341 }
 342
 343 uint8_t cpu_get_apic_tpr(APICState *s)
 344 {
 345     return s ? s->tpr >> 4 : 0;
 346 }
 347
 348 /* return -1 if no bit is set */
 349 static int get_highest_priority_int(uint32_t *tab)
 350 {
 351     int i;
 352     for(i = 7; i >= 0; i--) {
 353         if (tab[i] != 0) {
 354             return i * 32 + fls_bit(tab[i]);
 355         }
 356     }
 357     return -1;
 358 }
 359
 360 static int apic_get_ppr(APICState *s)
 361 {
 362     int tpr, isrv, ppr;
 363
 364     tpr = (s->tpr >> 4);
 365     isrv = get_highest_priority_int(s->isr);
 366     if (isrv < 0)
 367         isrv = 0;
 368     isrv >>= 4;
 369     if (tpr >= isrv)
 370         ppr = s->tpr;
 371     else
 372         ppr = isrv << 4;
 373     return ppr;
 374 }
 375
 376 static int apic_get_arb_pri(APICState *s)
 377 {
 378     /* XXX: arbitration */
 379     return 0;
 380 }
 381
 382 /* signal the CPU if an irq is pending */
 383 static void apic_update_irq(APICState *s)
 384 {
 385     int irrv, ppr;
 386     if (!(s->spurious_vec & APIC_SV_ENABLE))
 387         return;
 388     irrv = get_highest_priority_int(s->irr);
 389     if (irrv < 0)
 390         return;
 391     ppr = apic_get_ppr(s);
 392     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 393         return;
 394     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 395 }
 396
 397 void apic_reset_irq_delivered(void)
 398 {
 399     DPRINTF_C("%s: old coalescing %d\n", __func__, apic_irq_delivered);
 400     apic_irq_delivered = 0;
 401 }
 402
 403 int apic_get_irq_delivered(void)
 404 {
 405     DPRINTF_C("%s: returning coalescing %d\n", __func__, apic_irq_delivered);
 406     return apic_irq_delivered;
 407 }
 408
 409 void apic_set_irq_delivered(void)
 410 {
 411     apic_irq_delivered = 1;
 412 }
 413
 414 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 415 {
 416     apic_irq_delivered += !get_bit(s->irr, vector_num);
 417     DPRINTF_C("%s: coalescing %d\n", __func__, apic_irq_delivered);
 418
 419     set_bit(s->irr, vector_num);
 420     if (trigger_mode)
 421         set_bit(s->tmr, vector_num);
 422     else
 423         reset_bit(s->tmr, vector_num);
 424     apic_update_irq(s);
 425 }
 426
 427 static void apic_eoi(APICState *s)
 428 {
 429     int isrv;
 430     isrv = get_highest_priority_int(s->isr);
 431     if (isrv < 0)
 432         return;
 433     reset_bit(s->isr, isrv);
 434     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 435             set the remote IRR bit for level triggered interrupts. */
 436     apic_update_irq(s);
 437 }
 438
 439 static int apic_find_dest(uint8_t dest)
 440 {
 441     APICState *apic = local_apics[dest];
 442     int i;
 443
 444     if (apic && apic->id == dest)
 445         return dest;  /* shortcut in case apic->id == apic->idx */
 446
 447     for (i = 0; i < MAX_APICS; i++) {
 448         apic = local_apics[i];
 449         if (apic && apic->id == dest)
 450             return i;
 451     }
 452
 453     return -1;
 454 }
 455
 456 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 457                                       uint8_t dest, uint8_t dest_mode)
 458 {
 459     APICState *apic_iter;
 460     int i;
 461
 462     if (dest_mode == 0) {
 463         if (dest == 0xff) {
 464             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 465         } else {
 466             int idx = apic_find_dest(dest);
 467             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 468             if (idx >= 0)
 469                 set_bit(deliver_bitmask, idx);
 470         }
 471     } else {
 472         /* XXX: cluster mode */
 473         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 474         for(i = 0; i < MAX_APICS; i++) {
 475             apic_iter = local_apics[i];
 476             if (apic_iter) {
 477                 if (apic_iter->dest_mode == 0xf) {
 478                     if (dest & apic_iter->log_dest)
 479                         set_bit(deliver_bitmask, i);
 480                 } else if (apic_iter->dest_mode == 0x0) {
 481                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 482                         (dest & apic_iter->log_dest & 0x0f)) {
 483                         set_bit(deliver_bitmask, i);
 484                     }
 485                 }
 486             }
 487         }
 488     }
 489 }
 490
 491
 492 void apic_init_reset(APICState *s)
 493 {
 494     int i;
 495
 496     if (!s)
 497         return;
 498
 499     s->tpr = 0;
 500     s->spurious_vec = 0xff;
 501     s->log_dest = 0;
 502     s->dest_mode = 0xf;
 503     memset(s->isr, 0, sizeof(s->isr));
 504     memset(s->tmr, 0, sizeof(s->tmr));
 505     memset(s->irr, 0, sizeof(s->irr));
 506     for(i = 0; i < APIC_LVT_NB; i++)
 507         s->lvt[i] = 1 << 16; /* mask LVT */
 508     s->esr = 0;
 509     memset(s->icr, 0, sizeof(s->icr));
 510     s->divide_conf = 0;
 511     s->count_shift = 0;
 512     s->initial_count = 0;
 513     s->initial_count_load_time = 0;
 514     s->next_time = 0;
 515     s->wait_for_sipi = 1;
 516 }
 517
 518 static void apic_startup(APICState *s, int vector_num)
 519 {
 520     s->sipi_vector = vector_num;
 521     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 522 }
 523
 524 void apic_sipi(APICState *s)
 525 {
 526     cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 527
 528     if (!s->wait_for_sipi)
 529         return;
 530     cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
 531     s->wait_for_sipi = 0;
 532 }
 533
 534 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 535                          uint8_t delivery_mode, uint8_t vector_num,
 536                          uint8_t polarity, uint8_t trigger_mode)
 537 {
 538     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 539     int dest_shorthand = (s->icr[0] >> 18) & 3;
 540     APICState *apic_iter;
 541
 542     switch (dest_shorthand) {
 543     case 0:
 544         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 545         break;
 546     case 1:
 547         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 548         set_bit(deliver_bitmask, s->idx);
 549         break;
 550     case 2:
 551         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 552         break;
 553     case 3:
 554         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 555         reset_bit(deliver_bitmask, s->idx);
 556         break;
 557     }
 558
 559     switch (delivery_mode) {
 560         case APIC_DM_INIT:
 561             {
 562                 int trig_mode = (s->icr[0] >> 15) & 1;
 563                 int level = (s->icr[0] >> 14) & 1;
 564                 if (level == 0 && trig_mode == 1) {
 565                     foreach_apic(apic_iter, deliver_bitmask,
 566                                  apic_iter->arb_id = apic_iter->id );
 567                     return;
 568                 }
 569             }
 570             break;
 571
 572         case APIC_DM_SIPI:
 573             foreach_apic(apic_iter, deliver_bitmask,
 574                          apic_startup(apic_iter, vector_num) );
 575             return;
 576     }
 577
 578     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 579                      trigger_mode);
 580 }
 581
 582 int apic_get_interrupt(APICState *s)
 583 {
 584     int intno;
 585
 586     /* if the APIC is installed or enabled, we let the 8259 handle the
 587        IRQs */
 588     if (!s)
 589         return -1;
 590     if (!(s->spurious_vec & APIC_SV_ENABLE))
 591         return -1;
 592
 593     /* XXX: spurious IRQ handling */
 594     intno = get_highest_priority_int(s->irr);
 595     if (intno < 0)
 596         return -1;
 597     if (s->tpr && intno <= s->tpr)
 598         return s->spurious_vec & 0xff;
 599     reset_bit(s->irr, intno);
 600     set_bit(s->isr, intno);
 601     apic_update_irq(s);
 602     return intno;
 603 }
 604
 605 int apic_accept_pic_intr(APICState *s)
 606 {
 607     uint32_t lvt0;
 608
 609     if (!s)
 610         return -1;
 611
 612     lvt0 = s->lvt[APIC_LVT_LINT0];
 613
 614     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 615         (lvt0 & APIC_LVT_MASKED) == 0)
 616         return 1;
 617
 618     return 0;
 619 }
 620
 621 static uint32_t apic_get_current_count(APICState *s)
 622 {
 623     int64_t d;
 624     uint32_t val;
 625     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 626         s->count_shift;
 627     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 628         /* periodic */
 629         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 630     } else {
 631         if (d >= s->initial_count)
 632             val = 0;
 633         else
 634             val = s->initial_count - d;
 635     }
 636     return val;
 637 }
 638
 639 static void apic_timer_update(APICState *s, int64_t current_time)
 640 {
 641     int64_t next_time, d;
 642
 643     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 644         d = (current_time - s->initial_count_load_time) >>
 645             s->count_shift;
 646         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 647             if (!s->initial_count)
 648                 goto no_timer;
 649             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 650         } else {
 651             if (d >= s->initial_count)
 652                 goto no_timer;
 653             d = (uint64_t)s->initial_count + 1;
 654         }
 655         next_time = s->initial_count_load_time + (d << s->count_shift);
 656         qemu_mod_timer(s->timer, next_time);
 657         s->next_time = next_time;
 658     } else {
 659     no_timer:
 660         qemu_del_timer(s->timer);
 661     }
 662 }
 663
 664 static void apic_timer(void *opaque)
 665 {
 666     APICState *s = opaque;
 667
 668     apic_local_deliver(s, APIC_LVT_TIMER);
 669     apic_timer_update(s, s->next_time);
 670 }
 671
 672 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 673 {
 674     return 0;
 675 }
 676
 677 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 678 {
 679     return 0;
 680 }
 681
 682 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 683 {
 684 }
 685
 686 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 687 {
 688 }
 689
 690 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 691 {
 692     APICState *s;
 693     uint32_t val;
 694     int index;
 695
 696     s = cpu_get_current_apic();
 697     if (!s) {
 698         return 0;
 699     }
 700
 701     index = (addr >> 4) & 0xff;
 702     switch(index) {
 703     case 0x02: /* id */
 704         val = s->id << 24;
 705         break;
 706     case 0x03: /* version */
 707         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 708         break;
 709     case 0x08:
 710         val = s->tpr;
 711         break;
 712     case 0x09:
 713         val = apic_get_arb_pri(s);
 714         break;
 715     case 0x0a:
 716         /* ppr */
 717         val = apic_get_ppr(s);
 718         break;
 719     case 0x0b:
 720         val = 0;
 721         break;
 722     case 0x0d:
 723         val = s->log_dest << 24;
 724         break;
 725     case 0x0e:
 726         val = s->dest_mode << 28;
 727         break;
 728     case 0x0f:
 729         val = s->spurious_vec;
 730         break;
 731     case 0x10 ... 0x17:
 732         val = s->isr[index & 7];
 733         break;
 734     case 0x18 ... 0x1f:
 735         val = s->tmr[index & 7];
 736         break;
 737     case 0x20 ... 0x27:
 738         val = s->irr[index & 7];
 739         break;
 740     case 0x28:
 741         val = s->esr;
 742         break;
 743     case 0x30:
 744     case 0x31:
 745         val = s->icr[index & 1];
 746         break;
 747     case 0x32 ... 0x37:
 748         val = s->lvt[index - 0x32];
 749         break;
 750     case 0x38:
 751         val = s->initial_count;
 752         break;
 753     case 0x39:
 754         val = apic_get_current_count(s);
 755         break;
 756     case 0x3e:
 757         val = s->divide_conf;
 758         break;
 759     default:
 760         s->esr |= ESR_ILLEGAL_ADDRESS;
 761         val = 0;
 762         break;
 763     }
 764     DPRINTF("read: " TARGET_FMT_plx " = %08x\n", addr, val);
 765     return val;
 766 }
 767
 768 static void apic_send_msi(target_phys_addr_t addr, uint32 data)
 769 {
 770     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 771     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 772     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 773     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 774     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 775     /* XXX: Ignore redirection hint. */
 776     apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
 777 }
 778
 779 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 780 {
 781     APICState *s;
 782     int index = (addr >> 4) & 0xff;
 783     if (addr > 0xfff || !index) {
 784         /* MSI and MMIO APIC are at the same memory location,
 785          * but actually not on the global bus: MSI is on PCI bus
 786          * APIC is connected directly to the CPU.
 787          * Mapping them on the global bus happens to work because
 788          * MSI registers are reserved in APIC MMIO and vice versa. */
 789         apic_send_msi(addr, val);
 790         return;
 791     }
 792
 793     s = cpu_get_current_apic();
 794     if (!s) {
 795         return;
 796     }
 797
 798     DPRINTF("write: " TARGET_FMT_plx " = %08x\n", addr, val);
 799
 800     switch(index) {
 801     case 0x02:
 802         s->id = (val >> 24);
 803         break;
 804     case 0x03:
 805         break;
 806     case 0x08:
 807         s->tpr = val;
 808         apic_update_irq(s);
 809         break;
 810     case 0x09:
 811     case 0x0a:
 812         break;
 813     case 0x0b: /* EOI */
 814         apic_eoi(s);
 815         break;
 816     case 0x0d:
 817         s->log_dest = val >> 24;
 818         break;
 819     case 0x0e:
 820         s->dest_mode = val >> 28;
 821         break;
 822     case 0x0f:
 823         s->spurious_vec = val & 0x1ff;
 824         apic_update_irq(s);
 825         break;
 826     case 0x10 ... 0x17:
 827     case 0x18 ... 0x1f:
 828     case 0x20 ... 0x27:
 829     case 0x28:
 830         break;
 831     case 0x30:
 832         s->icr[0] = val;
 833         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 834                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 835                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 836         break;
 837     case 0x31:
 838         s->icr[1] = val;
 839         break;
 840     case 0x32 ... 0x37:
 841         {
 842             int n = index - 0x32;
 843             s->lvt[n] = val;
 844             if (n == APIC_LVT_TIMER)
 845                 apic_timer_update(s, qemu_get_clock(vm_clock));
 846         }
 847         break;
 848     case 0x38:
 849         s->initial_count = val;
 850         s->initial_count_load_time = qemu_get_clock(vm_clock);
 851         apic_timer_update(s, s->initial_count_load_time);
 852         break;
 853     case 0x39:
 854         break;
 855     case 0x3e:
 856         {
 857             int v;
 858             s->divide_conf = val & 0xb;
 859             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 860             s->count_shift = (v + 1) & 7;
 861         }
 862         break;
 863     default:
 864         s->esr |= ESR_ILLEGAL_ADDRESS;
 865         break;
 866     }
 867 }
 868
 869 #ifdef KVM_CAP_IRQCHIP
 870
 871 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 872 {
 873     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 874 }
 875
 876 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 877                                  int reg_id, uint32_t val)
 878 {
 879     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 880 }
 881
 882 static void kvm_kernel_lapic_save_to_user(APICState *s)
 883 {
 884     struct kvm_lapic_state apic;
 885     struct kvm_lapic_state *kapic = &apic;
 886     int i, v;
 887
 888     kvm_get_lapic(s->cpu_env, kapic);
 889
 890     s->id = kapic_reg(kapic, 0x2) >> 24;
 891     s->tpr = kapic_reg(kapic, 0x8);
 892     s->arb_id = kapic_reg(kapic, 0x9);
 893     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 894     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 895     s->spurious_vec = kapic_reg(kapic, 0xf);
 896     for (i = 0; i < 8; i++) {
 897         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 898         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 899         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 900     }
 901     s->esr = kapic_reg(kapic, 0x28);
 902     s->icr[0] = kapic_reg(kapic, 0x30);
 903     s->icr[1] = kapic_reg(kapic, 0x31);
 904     for (i = 0; i < APIC_LVT_NB; i++)
 905         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 906     s->initial_count = kapic_reg(kapic, 0x38);
 907     s->divide_conf = kapic_reg(kapic, 0x3e);
 908
 909     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 910     s->count_shift = (v + 1) & 7;
 911
 912     s->initial_count_load_time = qemu_get_clock(vm_clock);
 913     apic_timer_update(s, s->initial_count_load_time);
 914 }
 915
 916 static void kvm_kernel_lapic_load_from_user(APICState *s)
 917 {
 918     struct kvm_lapic_state apic;
 919     struct kvm_lapic_state *klapic = &apic;
 920     int i;
 921
 922     memset(klapic, 0, sizeof apic);
 923     kapic_set_reg(klapic, 0x2, s->id << 24);
 924     kapic_set_reg(klapic, 0x8, s->tpr);
 925     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 926     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 927     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 928     for (i = 0; i < 8; i++) {
 929         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 930         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 931         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 932     }
 933     kapic_set_reg(klapic, 0x28, s->esr);
 934     kapic_set_reg(klapic, 0x30, s->icr[0]);
 935     kapic_set_reg(klapic, 0x31, s->icr[1]);
 936     for (i = 0; i < APIC_LVT_NB; i++)
 937         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 938     kapic_set_reg(klapic, 0x38, s->initial_count);
 939     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 940
 941     kvm_set_lapic(s->cpu_env, klapic);
 942 }
 943
 944 #endif
 945
 946 void kvm_load_lapic(CPUState *env)
 947 {
 948 #ifdef KVM_CAP_IRQCHIP
 949     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 950         kvm_kernel_lapic_load_from_user(env->apic_state);
 951     }
 952 #endif
 953 }
 954
 955 void kvm_save_lapic(CPUState *env)
 956 {
 957 #ifdef KVM_CAP_IRQCHIP
 958     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 959         kvm_kernel_lapic_save_to_user(env->apic_state);
 960     }
 961 #endif
 962 }
 963
 964 /* This function is only used for old state version 1 and 2 */
 965 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 966 {
 967     APICState *s = opaque;
 968     int i;
 969
 970     if (version_id > 2)
 971         return -EINVAL;
 972
 973     /* XXX: what if the base changes? (registered memory regions) */
 974     qemu_get_be32s(f, &s->apicbase);
 975     qemu_get_8s(f, &s->id);
 976     qemu_get_8s(f, &s->arb_id);
 977     qemu_get_8s(f, &s->tpr);
 978     qemu_get_be32s(f, &s->spurious_vec);
 979     qemu_get_8s(f, &s->log_dest);
 980     qemu_get_8s(f, &s->dest_mode);
 981     for (i = 0; i < 8; i++) {
 982         qemu_get_be32s(f, &s->isr[i]);
 983         qemu_get_be32s(f, &s->tmr[i]);
 984         qemu_get_be32s(f, &s->irr[i]);
 985     }
 986     for (i = 0; i < APIC_LVT_NB; i++) {
 987         qemu_get_be32s(f, &s->lvt[i]);
 988     }
 989     qemu_get_be32s(f, &s->esr);
 990     qemu_get_be32s(f, &s->icr[0]);
 991     qemu_get_be32s(f, &s->icr[1]);
 992     qemu_get_be32s(f, &s->divide_conf);
 993     s->count_shift=qemu_get_be32(f);
 994     qemu_get_be32s(f, &s->initial_count);
 995     s->initial_count_load_time=qemu_get_be64(f);
 996     s->next_time=qemu_get_be64(f);
 997
 998     if (version_id >= 2)
 999         qemu_get_timer(f, s->timer);
1000     return 0;
1001 }
1002
1003 static const VMStateDescription vmstate_apic = {
1004     .name = "apic",
1005     .version_id = 3,
1006     .minimum_version_id = 3,
1007     .minimum_version_id_old = 1,
1008     .load_state_old = apic_load_old,
1009     .fields      = (VMStateField []) {
1010         VMSTATE_UINT32(apicbase, APICState),
1011         VMSTATE_UINT8(id, APICState),
1012         VMSTATE_UINT8(arb_id, APICState),
1013         VMSTATE_UINT8(tpr, APICState),
1014         VMSTATE_UINT32(spurious_vec, APICState),
1015         VMSTATE_UINT8(log_dest, APICState),
1016         VMSTATE_UINT8(dest_mode, APICState),
1017         VMSTATE_UINT32_ARRAY(isr, APICState, 8),
1018         VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
1019         VMSTATE_UINT32_ARRAY(irr, APICState, 8),
1020         VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
1021         VMSTATE_UINT32(esr, APICState),
1022         VMSTATE_UINT32_ARRAY(icr, APICState, 2),
1023         VMSTATE_UINT32(divide_conf, APICState),
1024         VMSTATE_INT32(count_shift, APICState),
1025         VMSTATE_UINT32(initial_count, APICState),
1026         VMSTATE_INT64(initial_count_load_time, APICState),
1027         VMSTATE_INT64(next_time, APICState),
1028         VMSTATE_TIMER(timer, APICState),
1029         VMSTATE_END_OF_LIST()
1030     }
1031 };
1032
1033 static void apic_reset(DeviceState *d)
1034 {
1035     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
1036     int bsp;
1037
1038     bsp = cpu_is_bsp(s->cpu_env);
1039     s->apicbase = 0xfee00000 |
1040         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
1041
1042     apic_init_reset(s);
1043
1044     if (bsp) {
1045         /*
1046          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1047          * time typically by BIOS, so PIC interrupt can be delivered to the
1048          * processor when local APIC is enabled.
1049          */
1050         s->lvt[APIC_LVT_LINT0] = 0x700;
1051     }
1052 }
1053
1054 static CPUReadMemoryFunc * const apic_mem_read[3] = {
1055     apic_mem_readb,
1056     apic_mem_readw,
1057     apic_mem_readl,
1058 };
1059
1060 static CPUWriteMemoryFunc * const apic_mem_write[3] = {
1061     apic_mem_writeb,
1062     apic_mem_writew,
1063     apic_mem_writel,
1064 };
1065
1066 APICState *apic_init(void *env, uint8_t apic_id)
1067 {
1068     DeviceState *dev;
1069     SysBusDevice *d;
1070     APICState *s;
1071     static int apic_mapped;
1072
1073     dev = qdev_create(NULL, "apic");
1074     qdev_prop_set_uint8(dev, "id", apic_id);
1075     qdev_prop_set_ptr(dev, "cpu_env", env);
1076     qdev_init_nofail(dev);
1077     d = sysbus_from_qdev(dev);
1078
1079     /* XXX: mapping more APICs at the same memory location */
1080     if (apic_mapped == 0) {
1081         /* NOTE: the APIC is directly connected to the CPU - it is not
1082            on the global memory bus. */
1083         /* XXX: what if the base changes? */
1084         sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
1085         apic_mapped = 1;
1086     }
1087
1088     msix_supported = 1;
1089
1090     s = DO_UPCAST(APICState, busdev.qdev, dev);
1091
1092     return s;
1093 }
1094
1095 static int apic_init1(SysBusDevice *dev)
1096 {
1097     APICState *s = FROM_SYSBUS(APICState, dev);
1098     int apic_io_memory;
1099     static int last_apic_idx;
1100
1101     if (last_apic_idx >= MAX_APICS) {
1102         return -1;
1103     }
1104     apic_io_memory = cpu_register_io_memory(apic_mem_read,
1105                                             apic_mem_write, NULL);
1106     sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
1107
1108     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1109     s->idx = last_apic_idx++;
1110     local_apics[s->idx] = s;
1111     return 0;
1112 }
1113
1114 static SysBusDeviceInfo apic_info = {
1115     .init = apic_init1,
1116     .qdev.name = "apic",
1117     .qdev.size = sizeof(APICState),
1118     .qdev.vmsd = &vmstate_apic,
1119     .qdev.reset = apic_reset,
1120     .qdev.no_user = 1,
1121     .qdev.props = (Property[]) {
1122         DEFINE_PROP_UINT8("id", APICState, id, -1),
1123         DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
1124         DEFINE_PROP_END_OF_LIST(),
1125     }
1126 };
1127
1128 static void apic_register_devices(void)
1129 {
1130     sysbus_register_withprop(&apic_info);
1131 }
1132
1133 device_init(apic_register_devices)