2 * qemu/kvm integration, x86 specific code
4 * Copyright (C) 2006-2008 Qumranet Technologies
6 * Licensed under the terms of the GNU GPL version 2 or higher.
10 #include "config-host.h"
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
22 #include <sys/ioctl.h>
27 #define MSR_IA32_TSC 0x10
29 static struct kvm_msr_list
*kvm_msr_list
;
30 extern unsigned int kvm_shadow_memory
;
31 static int kvm_has_msr_star
;
32 static int kvm_has_vm_hsave_pa
;
34 static int lm_capable_kernel
;
36 int kvm_set_tss_addr(kvm_context_t kvm
, unsigned long addr
)
38 #ifdef KVM_CAP_SET_TSS_ADDR
41 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_TSS_ADDR
);
43 r
= kvm_vm_ioctl(kvm_state
, KVM_SET_TSS_ADDR
, addr
);
45 fprintf(stderr
, "kvm_set_tss_addr: %m\n");
54 static int kvm_init_tss(kvm_context_t kvm
)
56 #ifdef KVM_CAP_SET_TSS_ADDR
59 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_TSS_ADDR
);
62 * this address is 3 pages before the bios, and the bios should present
65 r
= kvm_set_tss_addr(kvm
, 0xfeffd000);
67 fprintf(stderr
, "kvm_init_tss: unable to set tss addr\n");
76 static int kvm_set_identity_map_addr(kvm_context_t kvm
, uint64_t addr
)
78 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
81 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_IDENTITY_MAP_ADDR
);
83 r
= kvm_vm_ioctl(kvm_state
, KVM_SET_IDENTITY_MAP_ADDR
, &addr
);
85 fprintf(stderr
, "kvm_set_identity_map_addr: %m\n");
94 static int kvm_init_identity_map_page(kvm_context_t kvm
)
96 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
99 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_IDENTITY_MAP_ADDR
);
102 * this address is 4 pages before the bios, and the bios should present
103 * as unavaible memory
105 r
= kvm_set_identity_map_addr(kvm
, 0xfeffc000);
107 fprintf(stderr
, "kvm_init_identity_map_page: "
108 "unable to set identity mapping addr\n");
117 static int kvm_create_pit(kvm_context_t kvm
)
122 kvm
->pit_in_kernel
= 0;
123 if (!kvm
->no_pit_creation
) {
124 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_PIT
);
126 r
= kvm_vm_ioctl(kvm_state
, KVM_CREATE_PIT
);
128 kvm
->pit_in_kernel
= 1;
130 fprintf(stderr
, "Create kernel PIC irqchip failed\n");
139 int kvm_arch_create(kvm_context_t kvm
, unsigned long phys_mem_bytes
,
144 r
= kvm_init_tss(kvm
);
148 r
= kvm_init_identity_map_page(kvm
);
152 r
= kvm_create_pit(kvm
);
156 r
= kvm_init_coalesced_mmio(kvm
);
160 #ifdef KVM_EXIT_TPR_ACCESS
167 #ifdef KVM_EXIT_TPR_ACCESS
169 static int kvm_handle_tpr_access(CPUState
*env
)
171 struct kvm_run
*run
= env
->kvm_run
;
172 kvm_tpr_access_report(env
,
174 run
->tpr_access
.is_write
);
179 int kvm_enable_vapic(CPUState
*env
, uint64_t vapic
)
181 struct kvm_vapic_addr va
= {
185 return kvm_vcpu_ioctl(env
, KVM_SET_VAPIC_ADDR
, &va
);
190 int kvm_arch_run(CPUState
*env
)
193 struct kvm_run
*run
= env
->kvm_run
;
196 switch (run
->exit_reason
) {
197 #ifdef KVM_EXIT_SET_TPR
198 case KVM_EXIT_SET_TPR
:
201 #ifdef KVM_EXIT_TPR_ACCESS
202 case KVM_EXIT_TPR_ACCESS
:
203 r
= kvm_handle_tpr_access(env
);
214 #define MAX_ALIAS_SLOTS 4
218 } kvm_aliases
[MAX_ALIAS_SLOTS
];
220 static int get_alias_slot(uint64_t start
)
224 for (i
=0; i
<MAX_ALIAS_SLOTS
; i
++)
225 if (kvm_aliases
[i
].start
== start
)
229 static int get_free_alias_slot(void)
233 for (i
=0; i
<MAX_ALIAS_SLOTS
; i
++)
234 if (kvm_aliases
[i
].len
== 0)
239 static void register_alias(int slot
, uint64_t start
, uint64_t len
)
241 kvm_aliases
[slot
].start
= start
;
242 kvm_aliases
[slot
].len
= len
;
245 int kvm_create_memory_alias(kvm_context_t kvm
,
248 uint64_t target_phys
)
250 struct kvm_memory_alias alias
= {
252 .guest_phys_addr
= phys_start
,
254 .target_phys_addr
= target_phys
,
259 slot
= get_alias_slot(phys_start
);
261 slot
= get_free_alias_slot();
266 r
= kvm_vm_ioctl(kvm_state
, KVM_SET_MEMORY_ALIAS
, &alias
);
270 register_alias(slot
, phys_start
, len
);
274 int kvm_destroy_memory_alias(kvm_context_t kvm
, uint64_t phys_start
)
276 return kvm_create_memory_alias(kvm
, phys_start
, 0, 0);
279 #ifdef KVM_CAP_IRQCHIP
281 int kvm_get_lapic(CPUState
*env
, struct kvm_lapic_state
*s
)
285 if (!kvm_irqchip_in_kernel())
288 r
= kvm_vcpu_ioctl(env
, KVM_GET_LAPIC
, s
);
290 fprintf(stderr
, "KVM_GET_LAPIC failed\n");
294 int kvm_set_lapic(CPUState
*env
, struct kvm_lapic_state
*s
)
298 if (!kvm_irqchip_in_kernel())
301 r
= kvm_vcpu_ioctl(env
, KVM_SET_LAPIC
, s
);
304 fprintf(stderr
, "KVM_SET_LAPIC failed\n");
312 int kvm_get_pit(kvm_context_t kvm
, struct kvm_pit_state
*s
)
314 if (!kvm
->pit_in_kernel
)
316 return kvm_vm_ioctl(kvm_state
, KVM_GET_PIT
, s
);
319 int kvm_set_pit(kvm_context_t kvm
, struct kvm_pit_state
*s
)
321 if (!kvm
->pit_in_kernel
)
323 return kvm_vm_ioctl(kvm_state
, KVM_SET_PIT
, s
);
326 #ifdef KVM_CAP_PIT_STATE2
327 int kvm_get_pit2(kvm_context_t kvm
, struct kvm_pit_state2
*ps2
)
329 if (!kvm
->pit_in_kernel
)
331 return kvm_vm_ioctl(kvm_state
, KVM_GET_PIT2
, ps2
);
334 int kvm_set_pit2(kvm_context_t kvm
, struct kvm_pit_state2
*ps2
)
336 if (!kvm
->pit_in_kernel
)
338 return kvm_vm_ioctl(kvm_state
, KVM_SET_PIT2
, ps2
);
344 int kvm_has_pit_state2(kvm_context_t kvm
)
348 #ifdef KVM_CAP_PIT_STATE2
349 r
= kvm_check_extension(kvm_state
, KVM_CAP_PIT_STATE2
);
354 void kvm_show_code(CPUState
*env
)
356 #define SHOW_CODE_LEN 50
357 struct kvm_regs regs
;
358 struct kvm_sregs sregs
;
362 char code_str
[SHOW_CODE_LEN
* 3 + 1];
365 r
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
367 perror("KVM_GET_SREGS");
370 r
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
372 perror("KVM_GET_REGS");
375 rip
= sregs
.cs
.base
+ regs
.rip
;
376 back_offset
= regs
.rip
;
377 if (back_offset
> 20)
380 for (n
= -back_offset
; n
< SHOW_CODE_LEN
-back_offset
; ++n
) {
382 strcat(code_str
, " -->");
383 cpu_physical_memory_rw(rip
+ n
, &code
, 1, 1);
384 sprintf(code_str
+ strlen(code_str
), " %02x", code
);
386 fprintf(stderr
, "code:%s\n", code_str
);
391 * Returns available msr list. User must free.
393 struct kvm_msr_list
*kvm_get_msr_list(kvm_context_t kvm
)
395 struct kvm_msr_list sizer
, *msrs
;
399 r
= kvm_ioctl(kvm_state
, KVM_GET_MSR_INDEX_LIST
, &sizer
);
400 if (r
< 0 && r
!= -E2BIG
)
402 /* Old kernel modules had a bug and could write beyond the provided
403 memory. Allocate at least a safe amount of 1K. */
404 msrs
= qemu_malloc(MAX(1024, sizeof(*msrs
) +
405 sizer
.nmsrs
* sizeof(*msrs
->indices
)));
407 msrs
->nmsrs
= sizer
.nmsrs
;
408 r
= kvm_ioctl(kvm_state
, KVM_GET_MSR_INDEX_LIST
, msrs
);
417 int kvm_get_msrs(CPUState
*env
, struct kvm_msr_entry
*msrs
, int n
)
419 struct kvm_msrs
*kmsrs
= qemu_malloc(sizeof *kmsrs
+ n
* sizeof *msrs
);
423 memcpy(kmsrs
->entries
, msrs
, n
* sizeof *msrs
);
424 r
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, kmsrs
);
425 memcpy(msrs
, kmsrs
->entries
, n
* sizeof *msrs
);
430 int kvm_set_msrs(CPUState
*env
, struct kvm_msr_entry
*msrs
, int n
)
432 struct kvm_msrs
*kmsrs
= qemu_malloc(sizeof *kmsrs
+ n
* sizeof *msrs
);
436 memcpy(kmsrs
->entries
, msrs
, n
* sizeof *msrs
);
437 r
= kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, kmsrs
);
442 int kvm_get_mce_cap_supported(kvm_context_t kvm
, uint64_t *mce_cap
,
448 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_MCE
);
451 return kvm_ioctl(kvm_state
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
457 int kvm_setup_mce(CPUState
*env
, uint64_t *mcg_cap
)
460 return kvm_vcpu_ioctl(env
, KVM_X86_SETUP_MCE
, mcg_cap
);
466 int kvm_set_mce(CPUState
*env
, struct kvm_x86_mce
*m
)
469 return kvm_vcpu_ioctl(env
, KVM_X86_SET_MCE
, m
);
475 static void print_seg(FILE *file
, const char *name
, struct kvm_segment
*seg
)
478 "%s %04x (%08llx/%08x p %d dpl %d db %d s %d type %x l %d"
480 name
, seg
->selector
, seg
->base
, seg
->limit
, seg
->present
,
481 seg
->dpl
, seg
->db
, seg
->s
, seg
->type
, seg
->l
, seg
->g
,
485 static void print_dt(FILE *file
, const char *name
, struct kvm_dtable
*dt
)
487 fprintf(stderr
, "%s %llx/%x\n", name
, dt
->base
, dt
->limit
);
490 void kvm_show_regs(CPUState
*env
)
492 struct kvm_regs regs
;
493 struct kvm_sregs sregs
;
496 r
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
498 perror("KVM_GET_REGS");
502 "rax %016llx rbx %016llx rcx %016llx rdx %016llx\n"
503 "rsi %016llx rdi %016llx rsp %016llx rbp %016llx\n"
504 "r8 %016llx r9 %016llx r10 %016llx r11 %016llx\n"
505 "r12 %016llx r13 %016llx r14 %016llx r15 %016llx\n"
506 "rip %016llx rflags %08llx\n",
507 regs
.rax
, regs
.rbx
, regs
.rcx
, regs
.rdx
,
508 regs
.rsi
, regs
.rdi
, regs
.rsp
, regs
.rbp
,
509 regs
.r8
, regs
.r9
, regs
.r10
, regs
.r11
,
510 regs
.r12
, regs
.r13
, regs
.r14
, regs
.r15
,
511 regs
.rip
, regs
.rflags
);
512 r
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
514 perror("KVM_GET_SREGS");
517 print_seg(stderr
, "cs", &sregs
.cs
);
518 print_seg(stderr
, "ds", &sregs
.ds
);
519 print_seg(stderr
, "es", &sregs
.es
);
520 print_seg(stderr
, "ss", &sregs
.ss
);
521 print_seg(stderr
, "fs", &sregs
.fs
);
522 print_seg(stderr
, "gs", &sregs
.gs
);
523 print_seg(stderr
, "tr", &sregs
.tr
);
524 print_seg(stderr
, "ldt", &sregs
.ldt
);
525 print_dt(stderr
, "gdt", &sregs
.gdt
);
526 print_dt(stderr
, "idt", &sregs
.idt
);
527 fprintf(stderr
, "cr0 %llx cr2 %llx cr3 %llx cr4 %llx cr8 %llx"
529 sregs
.cr0
, sregs
.cr2
, sregs
.cr3
, sregs
.cr4
, sregs
.cr8
,
533 static void kvm_set_cr8(CPUState
*env
, uint64_t cr8
)
535 env
->kvm_run
->cr8
= cr8
;
538 int kvm_setup_cpuid(CPUState
*env
, int nent
,
539 struct kvm_cpuid_entry
*entries
)
541 struct kvm_cpuid
*cpuid
;
544 cpuid
= qemu_malloc(sizeof(*cpuid
) + nent
* sizeof(*entries
));
547 memcpy(cpuid
->entries
, entries
, nent
* sizeof(*entries
));
548 r
= kvm_vcpu_ioctl(env
, KVM_SET_CPUID
, cpuid
);
554 int kvm_setup_cpuid2(CPUState
*env
, int nent
,
555 struct kvm_cpuid_entry2
*entries
)
557 struct kvm_cpuid2
*cpuid
;
560 cpuid
= qemu_malloc(sizeof(*cpuid
) + nent
* sizeof(*entries
));
563 memcpy(cpuid
->entries
, entries
, nent
* sizeof(*entries
));
564 r
= kvm_vcpu_ioctl(env
, KVM_SET_CPUID2
, cpuid
);
569 int kvm_set_shadow_pages(kvm_context_t kvm
, unsigned int nrshadow_pages
)
571 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
574 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
,
575 KVM_CAP_MMU_SHADOW_CACHE_CONTROL
);
577 r
= kvm_vm_ioctl(kvm_state
, KVM_SET_NR_MMU_PAGES
, nrshadow_pages
);
579 fprintf(stderr
, "kvm_set_shadow_pages: %m\n");
588 int kvm_get_shadow_pages(kvm_context_t kvm
, unsigned int *nrshadow_pages
)
590 #ifdef KVM_CAP_MMU_SHADOW_CACHE_CONTROL
593 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
,
594 KVM_CAP_MMU_SHADOW_CACHE_CONTROL
);
596 *nrshadow_pages
= kvm_vm_ioctl(kvm_state
, KVM_GET_NR_MMU_PAGES
);
605 static int tpr_access_reporting(CPUState
*env
, int enabled
)
608 struct kvm_tpr_access_ctl tac
= {
612 r
= kvm_ioctl(kvm_state
, KVM_CHECK_EXTENSION
, KVM_CAP_VAPIC
);
615 return kvm_vcpu_ioctl(env
, KVM_TPR_ACCESS_REPORTING
, &tac
);
618 int kvm_enable_tpr_access_reporting(CPUState
*env
)
620 return tpr_access_reporting(env
, 1);
623 int kvm_disable_tpr_access_reporting(CPUState
*env
)
625 return tpr_access_reporting(env
, 0);
630 #ifdef KVM_CAP_EXT_CPUID
632 static struct kvm_cpuid2
*try_get_cpuid(kvm_context_t kvm
, int max
)
634 struct kvm_cpuid2
*cpuid
;
637 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
638 cpuid
= qemu_malloc(size
);
640 r
= kvm_ioctl(kvm_state
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
641 if (r
== 0 && cpuid
->nent
>= max
)
648 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
665 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm
, uint32_t function
, int reg
)
667 struct kvm_cpuid2
*cpuid
;
670 uint32_t cpuid_1_edx
;
672 if (!kvm_check_extension(kvm_state
, KVM_CAP_EXT_CPUID
)) {
677 while ((cpuid
= try_get_cpuid(kvm
, max
)) == NULL
) {
681 for (i
= 0; i
< cpuid
->nent
; ++i
) {
682 if (cpuid
->entries
[i
].function
== function
) {
685 ret
= cpuid
->entries
[i
].eax
;
688 ret
= cpuid
->entries
[i
].ebx
;
691 ret
= cpuid
->entries
[i
].ecx
;
694 ret
= cpuid
->entries
[i
].edx
;
696 /* kvm misreports the following features
698 ret
|= 1 << 12; /* MTRR */
699 ret
|= 1 << 16; /* PAT */
700 ret
|= 1 << 7; /* MCE */
701 ret
|= 1 << 14; /* MCA */
704 /* On Intel, kvm returns cpuid according to
705 * the Intel spec, so add missing bits
706 * according to the AMD spec:
708 if (function
== 0x80000001) {
709 cpuid_1_edx
= kvm_get_supported_cpuid(kvm
, 1, R_EDX
);
710 ret
|= cpuid_1_edx
& 0xdfeff7ff;
724 uint32_t kvm_get_supported_cpuid(kvm_context_t kvm
, uint32_t function
, int reg
)
730 int kvm_qemu_create_memory_alias(uint64_t phys_start
,
732 uint64_t target_phys
)
734 return kvm_create_memory_alias(kvm_context
, phys_start
, len
, target_phys
);
737 int kvm_qemu_destroy_memory_alias(uint64_t phys_start
)
739 return kvm_destroy_memory_alias(kvm_context
, phys_start
);
742 #ifdef KVM_CAP_ADJUST_CLOCK
743 static struct kvm_clock_data kvmclock_data
;
745 static void kvmclock_pre_save(void *opaque
)
747 struct kvm_clock_data
*cl
= opaque
;
749 kvm_vm_ioctl(kvm_state
, KVM_GET_CLOCK
, cl
);
752 static int kvmclock_post_load(void *opaque
, int version_id
)
754 struct kvm_clock_data
*cl
= opaque
;
756 return kvm_vm_ioctl(kvm_state
, KVM_SET_CLOCK
, cl
);
759 static const VMStateDescription vmstate_kvmclock
= {
762 .minimum_version_id
= 1,
763 .minimum_version_id_old
= 1,
764 .pre_save
= kvmclock_pre_save
,
765 .post_load
= kvmclock_post_load
,
766 .fields
= (VMStateField
[]) {
767 VMSTATE_U64(clock
, struct kvm_clock_data
),
768 VMSTATE_END_OF_LIST()
773 int kvm_arch_qemu_create_context(void)
776 struct utsname utsname
;
779 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
781 if (kvm_shadow_memory
)
782 kvm_set_shadow_pages(kvm_context
, kvm_shadow_memory
);
784 kvm_msr_list
= kvm_get_msr_list(kvm_context
);
787 for (i
= 0; i
< kvm_msr_list
->nmsrs
; ++i
) {
788 if (kvm_msr_list
->indices
[i
] == MSR_STAR
)
789 kvm_has_msr_star
= 1;
790 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
)
791 kvm_has_vm_hsave_pa
= 1;
794 #ifdef KVM_CAP_ADJUST_CLOCK
795 if (kvm_check_extension(kvm_state
, KVM_CAP_ADJUST_CLOCK
))
796 vmstate_register(0, &vmstate_kvmclock
, &kvmclock_data
);
801 static void set_msr_entry(struct kvm_msr_entry
*entry
, uint32_t index
,
804 entry
->index
= index
;
808 /* returns 0 on success, non-0 on failure */
809 static int get_msr_entry(struct kvm_msr_entry
*entry
, CPUState
*env
)
811 switch (entry
->index
) {
812 case MSR_IA32_SYSENTER_CS
:
813 env
->sysenter_cs
= entry
->data
;
815 case MSR_IA32_SYSENTER_ESP
:
816 env
->sysenter_esp
= entry
->data
;
818 case MSR_IA32_SYSENTER_EIP
:
819 env
->sysenter_eip
= entry
->data
;
822 env
->star
= entry
->data
;
826 env
->cstar
= entry
->data
;
828 case MSR_KERNELGSBASE
:
829 env
->kernelgsbase
= entry
->data
;
832 env
->fmask
= entry
->data
;
835 env
->lstar
= entry
->data
;
839 env
->tsc
= entry
->data
;
841 case MSR_VM_HSAVE_PA
:
842 env
->vm_hsave
= entry
->data
;
844 case MSR_KVM_SYSTEM_TIME
:
845 env
->system_time_msr
= entry
->data
;
847 case MSR_KVM_WALL_CLOCK
:
848 env
->wall_clock_msr
= entry
->data
;
851 printf("Warning unknown msr index 0x%x\n", entry
->index
);
857 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
859 lhs
->selector
= rhs
->selector
;
860 lhs
->base
= rhs
->base
;
861 lhs
->limit
= rhs
->limit
;
873 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
875 unsigned flags
= rhs
->flags
;
876 lhs
->selector
= rhs
->selector
;
877 lhs
->base
= rhs
->base
;
878 lhs
->limit
= rhs
->limit
;
879 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
880 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
881 lhs
->dpl
= rhs
->selector
& 3;
882 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
883 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
884 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
885 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
886 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
890 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
892 lhs
->selector
= rhs
->selector
;
893 lhs
->base
= rhs
->base
;
894 lhs
->limit
= rhs
->limit
;
896 (rhs
->type
<< DESC_TYPE_SHIFT
)
897 | (rhs
->present
* DESC_P_MASK
)
898 | (rhs
->dpl
<< DESC_DPL_SHIFT
)
899 | (rhs
->db
<< DESC_B_SHIFT
)
900 | (rhs
->s
* DESC_S_MASK
)
901 | (rhs
->l
<< DESC_L_SHIFT
)
902 | (rhs
->g
* DESC_G_MASK
)
903 | (rhs
->avl
* DESC_AVL_MASK
);
906 void kvm_arch_load_regs(CPUState
*env
)
908 struct kvm_regs regs
;
910 struct kvm_sregs sregs
;
911 struct kvm_msr_entry msrs
[100];
914 regs
.rax
= env
->regs
[R_EAX
];
915 regs
.rbx
= env
->regs
[R_EBX
];
916 regs
.rcx
= env
->regs
[R_ECX
];
917 regs
.rdx
= env
->regs
[R_EDX
];
918 regs
.rsi
= env
->regs
[R_ESI
];
919 regs
.rdi
= env
->regs
[R_EDI
];
920 regs
.rsp
= env
->regs
[R_ESP
];
921 regs
.rbp
= env
->regs
[R_EBP
];
923 regs
.r8
= env
->regs
[8];
924 regs
.r9
= env
->regs
[9];
925 regs
.r10
= env
->regs
[10];
926 regs
.r11
= env
->regs
[11];
927 regs
.r12
= env
->regs
[12];
928 regs
.r13
= env
->regs
[13];
929 regs
.r14
= env
->regs
[14];
930 regs
.r15
= env
->regs
[15];
933 regs
.rflags
= env
->eflags
;
936 kvm_set_regs(env
, ®s
);
938 memset(&fpu
, 0, sizeof fpu
);
939 fpu
.fsw
= env
->fpus
& ~(7 << 11);
940 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
942 for (i
= 0; i
< 8; ++i
)
943 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
944 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
945 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
946 fpu
.mxcsr
= env
->mxcsr
;
947 kvm_set_fpu(env
, &fpu
);
949 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
950 if (env
->interrupt_injected
>= 0) {
951 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
952 (uint64_t)1 << (env
->interrupt_injected
% 64);
955 if ((env
->eflags
& VM_MASK
)) {
956 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
957 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
958 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
959 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
960 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
961 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
963 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
964 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
965 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
966 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
967 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
968 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
970 if (env
->cr
[0] & CR0_PE_MASK
) {
971 /* force ss cpl to cs cpl */
972 sregs
.ss
.selector
= (sregs
.ss
.selector
& ~3) |
973 (sregs
.cs
.selector
& 3);
974 sregs
.ss
.dpl
= sregs
.ss
.selector
& 3;
978 set_seg(&sregs
.tr
, &env
->tr
);
979 set_seg(&sregs
.ldt
, &env
->ldt
);
981 sregs
.idt
.limit
= env
->idt
.limit
;
982 sregs
.idt
.base
= env
->idt
.base
;
983 sregs
.gdt
.limit
= env
->gdt
.limit
;
984 sregs
.gdt
.base
= env
->gdt
.base
;
986 sregs
.cr0
= env
->cr
[0];
987 sregs
.cr2
= env
->cr
[2];
988 sregs
.cr3
= env
->cr
[3];
989 sregs
.cr4
= env
->cr
[4];
991 sregs
.cr8
= cpu_get_apic_tpr(env
);
992 sregs
.apic_base
= cpu_get_apic_base(env
);
994 sregs
.efer
= env
->efer
;
996 kvm_set_sregs(env
, &sregs
);
1000 /* Remember to increase msrs size if you add new registers below */
1001 set_msr_entry(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
1002 set_msr_entry(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
1003 set_msr_entry(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
1004 if (kvm_has_msr_star
)
1005 set_msr_entry(&msrs
[n
++], MSR_STAR
, env
->star
);
1006 if (kvm_has_vm_hsave_pa
)
1007 set_msr_entry(&msrs
[n
++], MSR_VM_HSAVE_PA
, env
->vm_hsave
);
1008 #ifdef TARGET_X86_64
1009 if (lm_capable_kernel
) {
1010 set_msr_entry(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
1011 set_msr_entry(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
1012 set_msr_entry(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
1013 set_msr_entry(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
1016 set_msr_entry(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
, env
->system_time_msr
);
1017 set_msr_entry(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
1019 rc
= kvm_set_msrs(env
, msrs
, n
);
1021 perror("kvm_set_msrs FAILED");
1024 void kvm_load_tsc(CPUState
*env
)
1027 struct kvm_msr_entry msr
;
1029 set_msr_entry(&msr
, MSR_IA32_TSC
, env
->tsc
);
1031 rc
= kvm_set_msrs(env
, &msr
, 1);
1033 perror("kvm_set_tsc FAILED.\n");
1036 void kvm_arch_save_mpstate(CPUState
*env
)
1038 #ifdef KVM_CAP_MP_STATE
1040 struct kvm_mp_state mp_state
;
1042 r
= kvm_get_mpstate(env
, &mp_state
);
1046 env
->mp_state
= mp_state
.mp_state
;
1052 void kvm_arch_load_mpstate(CPUState
*env
)
1054 #ifdef KVM_CAP_MP_STATE
1055 struct kvm_mp_state mp_state
= { .mp_state
= env
->mp_state
};
1058 * -1 indicates that the host did not support GET_MP_STATE ioctl,
1059 * so don't touch it.
1061 if (env
->mp_state
!= -1)
1062 kvm_set_mpstate(env
, &mp_state
);
1066 void kvm_arch_save_regs(CPUState
*env
)
1068 struct kvm_regs regs
;
1070 struct kvm_sregs sregs
;
1071 struct kvm_msr_entry msrs
[100];
1073 uint32_t i
, n
, rc
, bit
;
1075 kvm_get_regs(env
, ®s
);
1077 env
->regs
[R_EAX
] = regs
.rax
;
1078 env
->regs
[R_EBX
] = regs
.rbx
;
1079 env
->regs
[R_ECX
] = regs
.rcx
;
1080 env
->regs
[R_EDX
] = regs
.rdx
;
1081 env
->regs
[R_ESI
] = regs
.rsi
;
1082 env
->regs
[R_EDI
] = regs
.rdi
;
1083 env
->regs
[R_ESP
] = regs
.rsp
;
1084 env
->regs
[R_EBP
] = regs
.rbp
;
1085 #ifdef TARGET_X86_64
1086 env
->regs
[8] = regs
.r8
;
1087 env
->regs
[9] = regs
.r9
;
1088 env
->regs
[10] = regs
.r10
;
1089 env
->regs
[11] = regs
.r11
;
1090 env
->regs
[12] = regs
.r12
;
1091 env
->regs
[13] = regs
.r13
;
1092 env
->regs
[14] = regs
.r14
;
1093 env
->regs
[15] = regs
.r15
;
1096 env
->eflags
= regs
.rflags
;
1097 env
->eip
= regs
.rip
;
1099 kvm_get_fpu(env
, &fpu
);
1100 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
1101 env
->fpus
= fpu
.fsw
;
1102 env
->fpuc
= fpu
.fcw
;
1103 for (i
= 0; i
< 8; ++i
)
1104 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
1105 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
1106 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
1107 env
->mxcsr
= fpu
.mxcsr
;
1109 kvm_get_sregs(env
, &sregs
);
1111 /* There can only be one pending IRQ set in the bitmap at a time, so try
1112 to find it and save its number instead (-1 for none). */
1113 env
->interrupt_injected
= -1;
1114 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
1115 if (sregs
.interrupt_bitmap
[i
]) {
1116 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
1117 env
->interrupt_injected
= i
* 64 + bit
;
1122 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1123 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1124 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1125 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1126 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1127 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1129 get_seg(&env
->tr
, &sregs
.tr
);
1130 get_seg(&env
->ldt
, &sregs
.ldt
);
1132 env
->idt
.limit
= sregs
.idt
.limit
;
1133 env
->idt
.base
= sregs
.idt
.base
;
1134 env
->gdt
.limit
= sregs
.gdt
.limit
;
1135 env
->gdt
.base
= sregs
.gdt
.base
;
1137 env
->cr
[0] = sregs
.cr0
;
1138 env
->cr
[2] = sregs
.cr2
;
1139 env
->cr
[3] = sregs
.cr3
;
1140 env
->cr
[4] = sregs
.cr4
;
1142 cpu_set_apic_base(env
, sregs
.apic_base
);
1144 env
->efer
= sregs
.efer
;
1145 //cpu_set_apic_tpr(env, sregs.cr8);
1147 #define HFLAG_COPY_MASK ~( \
1148 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1149 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1150 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1151 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1155 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1156 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1157 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1158 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1159 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1160 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
1161 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
1163 if (env
->efer
& MSR_EFER_LMA
) {
1164 hflags
|= HF_LMA_MASK
;
1167 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1168 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1170 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1171 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1172 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1173 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1174 if (!(env
->cr
[0] & CR0_PE_MASK
) ||
1175 (env
->eflags
& VM_MASK
) ||
1176 !(hflags
& HF_CS32_MASK
)) {
1177 hflags
|= HF_ADDSEG_MASK
;
1179 hflags
|= ((env
->segs
[R_DS
].base
|
1180 env
->segs
[R_ES
].base
|
1181 env
->segs
[R_SS
].base
) != 0) <<
1185 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
1189 /* Remember to increase msrs size if you add new registers below */
1190 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
1191 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
1192 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
1193 if (kvm_has_msr_star
)
1194 msrs
[n
++].index
= MSR_STAR
;
1195 msrs
[n
++].index
= MSR_IA32_TSC
;
1196 if (kvm_has_vm_hsave_pa
)
1197 msrs
[n
++].index
= MSR_VM_HSAVE_PA
;
1198 #ifdef TARGET_X86_64
1199 if (lm_capable_kernel
) {
1200 msrs
[n
++].index
= MSR_CSTAR
;
1201 msrs
[n
++].index
= MSR_KERNELGSBASE
;
1202 msrs
[n
++].index
= MSR_FMASK
;
1203 msrs
[n
++].index
= MSR_LSTAR
;
1206 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
1207 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
1209 rc
= kvm_get_msrs(env
, msrs
, n
);
1211 perror("kvm_get_msrs FAILED");
1214 n
= rc
; /* actual number of MSRs */
1215 for (i
=0 ; i
<n
; i
++) {
1216 if (get_msr_entry(&msrs
[i
], env
))
1222 static void do_cpuid_ent(struct kvm_cpuid_entry2
*e
, uint32_t function
,
1223 uint32_t count
, CPUState
*env
)
1225 env
->regs
[R_EAX
] = function
;
1226 env
->regs
[R_ECX
] = count
;
1227 qemu_kvm_cpuid_on_env(env
);
1228 e
->function
= function
;
1231 e
->eax
= env
->regs
[R_EAX
];
1232 e
->ebx
= env
->regs
[R_EBX
];
1233 e
->ecx
= env
->regs
[R_ECX
];
1234 e
->edx
= env
->regs
[R_EDX
];
1237 struct kvm_para_features
{
1240 } para_features
[] = {
1241 #ifdef KVM_CAP_CLOCKSOURCE
1242 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
1244 #ifdef KVM_CAP_NOP_IO_DELAY
1245 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
1247 #ifdef KVM_CAP_PV_MMU
1248 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
1250 #ifdef KVM_CAP_CR3_CACHE
1251 { KVM_CAP_CR3_CACHE
, KVM_FEATURE_CR3_CACHE
},
1256 static int get_para_features(kvm_context_t kvm_context
)
1258 int i
, features
= 0;
1260 for (i
= 0; i
< ARRAY_SIZE(para_features
)-1; i
++) {
1261 if (kvm_check_extension(kvm_state
, para_features
[i
].cap
))
1262 features
|= (1 << para_features
[i
].feature
);
1268 static void kvm_trim_features(uint32_t *features
, uint32_t supported
)
1273 for (i
= 0; i
< 32; ++i
) {
1275 if ((*features
& mask
) && !(supported
& mask
)) {
1281 int kvm_arch_init_vcpu(CPUState
*cenv
)
1283 struct kvm_cpuid_entry2 cpuid_ent
[100];
1284 #ifdef KVM_CPUID_SIGNATURE
1285 struct kvm_cpuid_entry2
*pv_ent
;
1286 uint32_t signature
[3];
1290 uint32_t i
, j
, limit
;
1292 qemu_kvm_load_lapic(cenv
);
1294 cenv
->interrupt_injected
= -1;
1296 #ifdef KVM_CPUID_SIGNATURE
1297 /* Paravirtualization CPUIDs */
1298 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
1299 pv_ent
= &cpuid_ent
[cpuid_nent
++];
1300 memset(pv_ent
, 0, sizeof(*pv_ent
));
1301 pv_ent
->function
= KVM_CPUID_SIGNATURE
;
1303 pv_ent
->ebx
= signature
[0];
1304 pv_ent
->ecx
= signature
[1];
1305 pv_ent
->edx
= signature
[2];
1307 pv_ent
= &cpuid_ent
[cpuid_nent
++];
1308 memset(pv_ent
, 0, sizeof(*pv_ent
));
1309 pv_ent
->function
= KVM_CPUID_FEATURES
;
1310 pv_ent
->eax
= get_para_features(kvm_context
);
1313 kvm_trim_features(&cenv
->cpuid_features
,
1314 kvm_arch_get_supported_cpuid(cenv
, 1, R_EDX
));
1316 /* prevent the hypervisor bit from being cleared by the kernel */
1317 i
= cenv
->cpuid_ext_features
& CPUID_EXT_HYPERVISOR
;
1318 kvm_trim_features(&cenv
->cpuid_ext_features
,
1319 kvm_arch_get_supported_cpuid(cenv
, 1, R_ECX
));
1320 cenv
->cpuid_ext_features
|= i
;
1322 kvm_trim_features(&cenv
->cpuid_ext2_features
,
1323 kvm_arch_get_supported_cpuid(cenv
, 0x80000001, R_EDX
));
1324 kvm_trim_features(&cenv
->cpuid_ext3_features
,
1325 kvm_arch_get_supported_cpuid(cenv
, 0x80000001, R_ECX
));
1329 copy
.regs
[R_EAX
] = 0;
1330 qemu_kvm_cpuid_on_env(©
);
1331 limit
= copy
.regs
[R_EAX
];
1333 for (i
= 0; i
<= limit
; ++i
) {
1334 if (i
== 4 || i
== 0xb || i
== 0xd) {
1335 for (j
= 0; ; ++j
) {
1336 do_cpuid_ent(&cpuid_ent
[cpuid_nent
], i
, j
, ©
);
1338 cpuid_ent
[cpuid_nent
].flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
1339 cpuid_ent
[cpuid_nent
].index
= j
;
1343 if (i
== 4 && copy
.regs
[R_EAX
] == 0)
1345 if (i
== 0xb && !(copy
.regs
[R_ECX
] & 0xff00))
1347 if (i
== 0xd && copy
.regs
[R_EAX
] == 0)
1351 do_cpuid_ent(&cpuid_ent
[cpuid_nent
++], i
, 0, ©
);
1354 copy
.regs
[R_EAX
] = 0x80000000;
1355 qemu_kvm_cpuid_on_env(©
);
1356 limit
= copy
.regs
[R_EAX
];
1358 for (i
= 0x80000000; i
<= limit
; ++i
)
1359 do_cpuid_ent(&cpuid_ent
[cpuid_nent
++], i
, 0, ©
);
1361 kvm_setup_cpuid2(cenv
, cpuid_nent
, cpuid_ent
);
1364 if (((cenv
->cpuid_version
>> 8)&0xF) >= 6
1365 && (cenv
->cpuid_features
&(CPUID_MCE
|CPUID_MCA
)) == (CPUID_MCE
|CPUID_MCA
)
1366 && kvm_check_extension(kvm_state
, KVM_CAP_MCE
) > 0) {
1370 if (kvm_get_mce_cap_supported(kvm_context
, &mcg_cap
, &banks
))
1371 perror("kvm_get_mce_cap_supported FAILED");
1373 if (banks
> MCE_BANKS_DEF
)
1374 banks
= MCE_BANKS_DEF
;
1375 mcg_cap
&= MCE_CAP_DEF
;
1377 if (kvm_setup_mce(cenv
, &mcg_cap
))
1378 perror("kvm_setup_mce FAILED");
1380 cenv
->mcg_cap
= mcg_cap
;
1385 #ifdef KVM_EXIT_TPR_ACCESS
1386 kvm_tpr_vcpu_start(cenv
);
1391 int kvm_arch_halt(CPUState
*env
)
1394 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1395 (env
->eflags
& IF_MASK
)) &&
1396 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1402 int kvm_arch_pre_run(CPUState
*env
, struct kvm_run
*run
)
1404 if (env
->update_vapic
) {
1405 kvm_tpr_enable_vapic(env
);
1407 if (!kvm_irqchip_in_kernel())
1408 kvm_set_cr8(env
, cpu_get_apic_tpr(env
));
1412 int kvm_arch_has_work(CPUState
*env
)
1414 if (((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1415 (env
->eflags
& IF_MASK
)) ||
1416 (env
->interrupt_request
& CPU_INTERRUPT_NMI
))
1421 int kvm_arch_try_push_interrupts(void *opaque
)
1423 CPUState
*env
= cpu_single_env
;
1426 if (kvm_is_ready_for_interrupt_injection(env
) &&
1427 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1428 (env
->eflags
& IF_MASK
)) {
1429 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1430 irq
= cpu_get_pic_interrupt(env
);
1432 r
= kvm_inject_irq(env
, irq
);
1434 printf("cpu %d fail inject %x\n", env
->cpu_index
, irq
);
1438 return (env
->interrupt_request
& CPU_INTERRUPT_HARD
) != 0;
1441 #ifdef KVM_CAP_USER_NMI
1442 void kvm_arch_push_nmi(void *opaque
)
1444 CPUState
*env
= cpu_single_env
;
1447 if (likely(!(env
->interrupt_request
& CPU_INTERRUPT_NMI
)))
1450 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
1451 r
= kvm_inject_nmi(env
);
1453 printf("cpu %d fail inject NMI\n", env
->cpu_index
);
1455 #endif /* KVM_CAP_USER_NMI */
1457 void kvm_arch_cpu_reset(CPUState
*env
)
1459 env
->interrupt_injected
= -1;
1460 kvm_arch_load_regs(env
);
1461 if (!cpu_is_bsp(env
)) {
1462 if (kvm_irqchip_in_kernel()) {
1463 #ifdef KVM_CAP_MP_STATE
1464 kvm_reset_mpstate(env
);
1467 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1473 int kvm_arch_insert_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1475 uint8_t int3
= 0xcc;
1477 if (cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
1478 cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 1))
1483 int kvm_arch_remove_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1487 if (cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
1488 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1))
1493 #ifdef KVM_CAP_SET_GUEST_DEBUG
1500 static int nb_hw_breakpoint
;
1502 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
1506 for (n
= 0; n
< nb_hw_breakpoint
; n
++)
1507 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
1508 (hw_breakpoint
[n
].len
== len
|| len
== -1))
1513 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1514 target_ulong len
, int type
)
1517 case GDB_BREAKPOINT_HW
:
1520 case GDB_WATCHPOINT_WRITE
:
1521 case GDB_WATCHPOINT_ACCESS
:
1528 if (addr
& (len
- 1))
1539 if (nb_hw_breakpoint
== 4)
1542 if (find_hw_breakpoint(addr
, len
, type
) >= 0)
1545 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
1546 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
1547 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
1553 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1554 target_ulong len
, int type
)
1558 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
1563 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
1568 void kvm_arch_remove_all_hw_breakpoints(void)
1570 nb_hw_breakpoint
= 0;
1573 static CPUWatchpoint hw_watchpoint
;
1575 int kvm_arch_debug(struct kvm_debug_exit_arch
*arch_info
)
1580 if (arch_info
->exception
== 1) {
1581 if (arch_info
->dr6
& (1 << 14)) {
1582 if (cpu_single_env
->singlestep_enabled
)
1585 for (n
= 0; n
< 4; n
++)
1586 if (arch_info
->dr6
& (1 << n
))
1587 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
1593 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1594 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1595 hw_watchpoint
.flags
= BP_MEM_WRITE
;
1599 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1600 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1601 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
1605 } else if (kvm_find_sw_breakpoint(cpu_single_env
, arch_info
->pc
))
1609 kvm_update_guest_debug(cpu_single_env
,
1610 (arch_info
->exception
== 1) ?
1611 KVM_GUESTDBG_INJECT_DB
: KVM_GUESTDBG_INJECT_BP
);
1616 void kvm_arch_update_guest_debug(CPUState
*env
, struct kvm_guest_debug
*dbg
)
1618 const uint8_t type_code
[] = {
1619 [GDB_BREAKPOINT_HW
] = 0x0,
1620 [GDB_WATCHPOINT_WRITE
] = 0x1,
1621 [GDB_WATCHPOINT_ACCESS
] = 0x3
1623 const uint8_t len_code
[] = {
1624 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1628 if (kvm_sw_breakpoints_active(env
))
1629 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
1631 if (nb_hw_breakpoint
> 0) {
1632 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
1633 dbg
->arch
.debugreg
[7] = 0x0600;
1634 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
1635 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
1636 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
1637 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
1638 (len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
1644 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
1645 void kvm_arch_do_ioperm(void *_data
)
1647 struct ioperm_data
*data
= _data
;
1648 ioperm(data
->start_port
, data
->num
, data
->turn_on
);
1653 * Setup x86 specific IRQ routing
1655 int kvm_arch_init_irq_routing(void)
1659 if (kvm_irqchip
&& kvm_has_gsi_routing(kvm_context
)) {
1660 kvm_clear_gsi_routes(kvm_context
);
1661 for (i
= 0; i
< 8; ++i
) {
1664 r
= kvm_add_irq_route(kvm_context
, i
, KVM_IRQCHIP_PIC_MASTER
, i
);
1668 for (i
= 8; i
< 16; ++i
) {
1669 r
= kvm_add_irq_route(kvm_context
, i
, KVM_IRQCHIP_PIC_SLAVE
, i
- 8);
1673 for (i
= 0; i
< 24; ++i
) {
1675 r
= kvm_add_irq_route(kvm_context
, i
, KVM_IRQCHIP_IOAPIC
, 2);
1676 } else if (i
!= 2) {
1677 r
= kvm_add_irq_route(kvm_context
, i
, KVM_IRQCHIP_IOAPIC
, i
);
1682 kvm_commit_irq_routes(kvm_context
);
1687 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
1690 return kvm_get_supported_cpuid(kvm_context
, function
, reg
);
1693 void kvm_arch_process_irqchip_events(CPUState
*env
)
1695 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1696 kvm_cpu_synchronize_state(env
);
1699 if (env
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
1700 kvm_cpu_synchronize_state(env
);